tx39power.c revision 1.21 1 1.21 chs /* $NetBSD: tx39power.c,v 1.21 2012/10/27 17:17:54 chs Exp $ */
2 1.1 uch
3 1.6 uch /*-
4 1.7 uch * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc.
5 1.7 uch * All rights reserved.
6 1.7 uch *
7 1.7 uch * This code is derived from software contributed to The NetBSD Foundation
8 1.7 uch * by UCHIYAMA Yasushi.
9 1.1 uch *
10 1.1 uch * Redistribution and use in source and binary forms, with or without
11 1.1 uch * modification, are permitted provided that the following conditions
12 1.1 uch * are met:
13 1.1 uch * 1. Redistributions of source code must retain the above copyright
14 1.1 uch * notice, this list of conditions and the following disclaimer.
15 1.6 uch * 2. Redistributions in binary form must reproduce the above copyright
16 1.6 uch * notice, this list of conditions and the following disclaimer in the
17 1.6 uch * documentation and/or other materials provided with the distribution.
18 1.1 uch *
19 1.7 uch * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 1.7 uch * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 1.7 uch * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 1.7 uch * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 1.7 uch * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 1.7 uch * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 1.7 uch * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 1.7 uch * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 1.7 uch * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 1.7 uch * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 1.7 uch * POSSIBILITY OF SUCH DAMAGE.
30 1.1 uch */
31 1.13 lukem
32 1.13 lukem #include <sys/cdefs.h>
33 1.21 chs __KERNEL_RCSID(0, "$NetBSD: tx39power.c,v 1.21 2012/10/27 17:17:54 chs Exp $");
34 1.6 uch
35 1.10 uch #include "opt_tx39power_debug.h"
36 1.1 uch
37 1.1 uch #include <sys/param.h>
38 1.1 uch #include <sys/systm.h>
39 1.1 uch #include <sys/device.h>
40 1.1 uch
41 1.1 uch #include <machine/bus.h>
42 1.1 uch #include <machine/intr.h>
43 1.7 uch #include <machine/config_hook.h>
44 1.1 uch
45 1.1 uch #include <hpcmips/tx/tx39var.h>
46 1.1 uch #include <hpcmips/tx/tx39icureg.h>
47 1.1 uch #include <hpcmips/tx/tx39powerreg.h>
48 1.8 uch
49 1.10 uch #ifdef TX39POWER_DEBUG
50 1.10 uch #define DPRINTF_ENABLE
51 1.10 uch #define DPRINTF_DEBUG tx39power_debug
52 1.10 uch #endif
53 1.10 uch #include <machine/debug.h>
54 1.10 uch
55 1.10 uch #ifdef TX39POWER_DEBUG
56 1.8 uch #define DUMP_REGS(x) __tx39power_dump(x)
57 1.8 uch #else
58 1.8 uch #define DUMP_REGS(x) ((void)0)
59 1.8 uch #endif
60 1.1 uch
61 1.10 uch #define ISSETPRINT(r, m) dbg_bitmask_print(r, TX39_POWERCTRL_##m, #m)
62 1.1 uch
63 1.21 chs int tx39power_match(device_t, cfdata_t, void *);
64 1.21 chs void tx39power_attach(device_t, device_t, void *);
65 1.1 uch
66 1.1 uch struct tx39power_softc {
67 1.21 chs device_t sc_dev;
68 1.1 uch tx_chipset_tag_t sc_tc;
69 1.7 uch
70 1.7 uch /* save interrupt status for resume */
71 1.7 uch txreg_t sc_icu_state[TX39_INTRSET_MAX + 1];
72 1.1 uch };
73 1.1 uch
74 1.21 chs CFATTACH_DECL_NEW(tx39power, sizeof(struct tx39power_softc),
75 1.12 thorpej tx39power_match, tx39power_attach, NULL, NULL);
76 1.1 uch
77 1.7 uch void tx39power_suspend_cpu(void); /* automatic hardware resume */
78 1.7 uch
79 1.7 uch static int tx39power_intr_p(void *);
80 1.7 uch static int tx39power_intr_n(void *);
81 1.7 uch static int tx39power_ok_intr_p(void *);
82 1.7 uch static int tx39power_ok_intr_n(void *);
83 1.7 uch static int tx39power_button_intr_p(void *);
84 1.7 uch static int tx39power_button_intr_n(void *);
85 1.10 uch #ifdef TX39POWER_DEBUG
86 1.8 uch static void __tx39power_dump(struct tx39power_softc *);
87 1.7 uch #endif
88 1.7 uch
89 1.1 uch int
90 1.21 chs tx39power_match(device_t parent, cfdata_t cf, void *aux)
91 1.1 uch {
92 1.9 uch return (ATTACH_FIRST);
93 1.1 uch }
94 1.1 uch
95 1.1 uch void
96 1.21 chs tx39power_attach(device_t parent, device_t self, void *aux)
97 1.1 uch {
98 1.1 uch struct txsim_attach_args *ta = aux;
99 1.21 chs struct tx39power_softc *sc = device_private(self);
100 1.1 uch tx_chipset_tag_t tc;
101 1.1 uch txreg_t reg;
102 1.1 uch
103 1.21 chs sc->sc_dev = self;
104 1.1 uch tc = sc->sc_tc = ta->ta_tc;
105 1.4 uch tx_conf_register_power(tc, self);
106 1.4 uch
107 1.2 uch printf("\n");
108 1.8 uch DUMP_REGS(sc);
109 1.8 uch
110 1.8 uch /* power button setting */
111 1.8 uch reg = tx_conf_read(tc, TX39_POWERCTRL_REG);
112 1.8 uch reg |= TX39_POWERCTRL_DBNCONBUTN;
113 1.8 uch tx_conf_write(tc, TX39_POWERCTRL_REG, reg);
114 1.8 uch
115 1.8 uch /* enable stop timer */
116 1.2 uch reg = tx_conf_read(tc, TX39_POWERCTRL_REG);
117 1.3 uch reg &= ~(TX39_POWERCTRL_STPTIMERVAL_MASK <<
118 1.9 uch TX39_POWERCTRL_STPTIMERVAL_SHIFT);
119 1.8 uch reg = TX39_POWERCTRL_STPTIMERVAL_SET(reg,
120 1.9 uch TX39_POWERCTRL_STPTIMERVAL_MAX);
121 1.2 uch reg |= TX39_POWERCTRL_ENSTPTIMER;
122 1.2 uch tx_conf_write(tc, TX39_POWERCTRL_REG, reg);
123 1.1 uch
124 1.8 uch /* install power event handler */
125 1.8 uch /* low priority */
126 1.1 uch tx_intr_establish(tc, MAKEINTR(5, TX39_INTRSTATUS5_POSPWRINT),
127 1.9 uch IST_EDGE, IPL_CLOCK,
128 1.9 uch tx39power_intr_p, sc);
129 1.1 uch tx_intr_establish(tc, MAKEINTR(5, TX39_INTRSTATUS5_NEGPWRINT),
130 1.9 uch IST_EDGE, IPL_CLOCK,
131 1.9 uch tx39power_intr_n, sc);
132 1.8 uch /* high priority */
133 1.1 uch tx_intr_establish(tc, MAKEINTR(5, TX39_INTRSTATUS5_POSPWROKINT),
134 1.9 uch IST_EDGE, IPL_CLOCK,
135 1.9 uch tx39power_ok_intr_p, sc);
136 1.1 uch tx_intr_establish(tc, MAKEINTR(5, TX39_INTRSTATUS5_NEGPWROKINT),
137 1.9 uch IST_EDGE, IPL_CLOCK,
138 1.9 uch tx39power_ok_intr_n, sc);
139 1.8 uch /* user driven event */
140 1.1 uch tx_intr_establish(tc, MAKEINTR(5, TX39_INTRSTATUS5_POSONBUTNINT),
141 1.9 uch IST_EDGE, IPL_CLOCK,
142 1.9 uch tx39power_button_intr_p, sc);
143 1.7 uch tx_intr_establish(tc, MAKEINTR(5, TX39_INTRSTATUS5_NEGONBUTNINT),
144 1.9 uch IST_EDGE, IPL_CLOCK,
145 1.9 uch tx39power_button_intr_n, sc);
146 1.7 uch }
147 1.7 uch
148 1.7 uch void
149 1.20 matt tx39power_suspend_cpu(void) /* I assume already splhigh */
150 1.7 uch {
151 1.7 uch tx_chipset_tag_t tc = tx_conf_get_tag();
152 1.7 uch struct tx39power_softc *sc = tc->tc_powert;
153 1.7 uch txreg_t reg, *iregs = sc->sc_icu_state;
154 1.7 uch
155 1.21 chs printf ("%s: CPU sleep\n", device_xname(sc->sc_dev));
156 1.15 perry __asm volatile(".set noreorder");
157 1.7 uch reg = tx_conf_read(tc, TX39_POWERCTRL_REG);
158 1.7 uch reg |= TX39_POWERCTRL_STOPCPU;
159 1.7 uch /* save interrupt state */
160 1.7 uch iregs[0] = tx_conf_read(tc, TX39_INTRENABLE6_REG);
161 1.7 uch iregs[1] = tx_conf_read(tc, TX39_INTRENABLE1_REG);
162 1.7 uch iregs[2] = tx_conf_read(tc, TX39_INTRENABLE2_REG);
163 1.7 uch iregs[3] = tx_conf_read(tc, TX39_INTRENABLE3_REG);
164 1.7 uch iregs[4] = tx_conf_read(tc, TX39_INTRENABLE4_REG);
165 1.7 uch iregs[5] = tx_conf_read(tc, TX39_INTRENABLE5_REG);
166 1.7 uch #ifdef TX392X
167 1.7 uch iregs[7] = tx_conf_read(tc, TX39_INTRENABLE7_REG);
168 1.7 uch iregs[8] = tx_conf_read(tc, TX39_INTRENABLE8_REG);
169 1.7 uch #endif
170 1.7 uch /* disable all interrupt (don't disable GLOBALEN) */
171 1.7 uch tx_conf_write(tc, TX39_INTRENABLE6_REG, TX39_INTRENABLE6_GLOBALEN);
172 1.7 uch tx_conf_write(tc, TX39_INTRENABLE1_REG, 0);
173 1.7 uch tx_conf_write(tc, TX39_INTRENABLE2_REG, 0);
174 1.7 uch tx_conf_write(tc, TX39_INTRENABLE3_REG, 0);
175 1.7 uch tx_conf_write(tc, TX39_INTRENABLE4_REG, 0);
176 1.7 uch tx_conf_write(tc, TX39_INTRENABLE5_REG, 0);
177 1.7 uch #ifdef TX392X
178 1.7 uch tx_conf_write(tc, TX39_INTRENABLE7_REG, 0);
179 1.7 uch tx_conf_write(tc, TX39_INTRENABLE8_REG, 0);
180 1.7 uch #endif
181 1.7 uch /* enable power button interrupt only */
182 1.7 uch tx_conf_write(tc, TX39_INTRCLEAR5_REG, TX39_INTRSTATUS5_NEGONBUTNINT);
183 1.7 uch tx_conf_write(tc, TX39_INTRENABLE5_REG, TX39_INTRSTATUS5_NEGONBUTNINT);
184 1.18 tsutsui __asm volatile(".set push; .set mips2; sync; .set pop");
185 1.7 uch
186 1.7 uch /* stop CPU clock */
187 1.7 uch tx_conf_write(tc, TX39_POWERCTRL_REG, reg);
188 1.18 tsutsui __asm volatile(".set push; .set mips2; sync; .set pop");
189 1.7 uch /* wait until power button pressed */
190 1.7 uch /* clear interrupt */
191 1.7 uch tx_conf_write(tc, TX39_INTRCLEAR5_REG, TX39_INTRSTATUS5_NEGONBUTNINT);
192 1.8 uch #ifdef TX392X
193 1.8 uch /* Clear WARMSTART bit to reset vector(0xbfc00000) work correctly */
194 1.8 uch reg = tx_conf_read(tc, TX39_POWERCTRL_REG);
195 1.8 uch reg &= ~TX39_POWERCTRL_WARMSTART;
196 1.8 uch tx_conf_write(tc, TX39_POWERCTRL_REG, reg);
197 1.8 uch #endif
198 1.7 uch
199 1.7 uch /* restore interrupt state */
200 1.7 uch tx_conf_write(tc, TX39_INTRENABLE6_REG, iregs[0]);
201 1.7 uch tx_conf_write(tc, TX39_INTRENABLE1_REG, iregs[1]);
202 1.7 uch tx_conf_write(tc, TX39_INTRENABLE2_REG, iregs[2]);
203 1.7 uch tx_conf_write(tc, TX39_INTRENABLE3_REG, iregs[3]);
204 1.7 uch tx_conf_write(tc, TX39_INTRENABLE4_REG, iregs[4]);
205 1.7 uch tx_conf_write(tc, TX39_INTRENABLE5_REG, iregs[5]);
206 1.7 uch #ifdef TX392X
207 1.7 uch tx_conf_write(tc, TX39_INTRENABLE7_REG, iregs[7]);
208 1.7 uch tx_conf_write(tc, TX39_INTRENABLE8_REG, iregs[8]);
209 1.5 uch #endif
210 1.15 perry __asm volatile(".set reorder");
211 1.1 uch
212 1.21 chs printf ("%s: CPU wakeup\n", device_xname(sc->sc_dev));
213 1.1 uch }
214 1.1 uch
215 1.7 uch static int
216 1.7 uch tx39power_button_intr_p(void *arg)
217 1.1 uch {
218 1.7 uch config_hook_call(CONFIG_HOOK_BUTTONEVENT,
219 1.9 uch CONFIG_HOOK_BUTTONEVENT_POWER,
220 1.9 uch (void *)1 /* on */);
221 1.9 uch
222 1.9 uch return (0);
223 1.7 uch }
224 1.6 uch
225 1.7 uch static int
226 1.7 uch tx39power_button_intr_n(void *arg)
227 1.7 uch {
228 1.7 uch config_hook_call(CONFIG_HOOK_BUTTONEVENT,
229 1.9 uch CONFIG_HOOK_BUTTONEVENT_POWER,
230 1.9 uch (void *)0 /* off */);
231 1.8 uch DUMP_REGS(arg);
232 1.9 uch
233 1.9 uch return (0);
234 1.1 uch }
235 1.1 uch
236 1.1 uch int
237 1.7 uch tx39power_intr_p(void *arg)
238 1.7 uch {
239 1.8 uch /* low priority event */
240 1.7 uch printf("power_p\n");
241 1.8 uch DUMP_REGS(arg);
242 1.9 uch
243 1.9 uch return (0);
244 1.7 uch }
245 1.7 uch
246 1.7 uch static int
247 1.7 uch tx39power_intr_n(void *arg)
248 1.1 uch {
249 1.8 uch /* low priority event */
250 1.7 uch printf("power_n\n");
251 1.8 uch DUMP_REGS(arg);
252 1.9 uch
253 1.9 uch return (0);
254 1.1 uch }
255 1.1 uch
256 1.7 uch static int
257 1.7 uch tx39power_ok_intr_p(void *arg)
258 1.1 uch {
259 1.8 uch /* high priority event */
260 1.5 uch printf("power NG\n");
261 1.8 uch DUMP_REGS(arg);
262 1.7 uch config_hook_call(CONFIG_HOOK_PMEVENT,
263 1.9 uch CONFIG_HOOK_PMEVENT_SUSPENDREQ, NULL);
264 1.9 uch
265 1.9 uch return (0);
266 1.1 uch }
267 1.7 uch
268 1.7 uch static int
269 1.7 uch tx39power_ok_intr_n(void *arg)
270 1.7 uch {
271 1.8 uch /* high priority event */
272 1.7 uch printf("power OK\n");
273 1.8 uch DUMP_REGS(arg);
274 1.9 uch
275 1.9 uch return (0);
276 1.7 uch }
277 1.7 uch
278 1.10 uch #ifdef TX39POWER_DEBUG
279 1.7 uch static void
280 1.7 uch __tx39power_dump (struct tx39power_softc *sc)
281 1.7 uch {
282 1.7 uch tx_chipset_tag_t tc = sc->sc_tc;
283 1.8 uch txreg_t reg;
284 1.7 uch
285 1.7 uch reg = tx_conf_read(tc, TX39_POWERCTRL_REG);
286 1.7 uch ISSETPRINT(reg, ONBUTN);
287 1.7 uch ISSETPRINT(reg, PWRINT);
288 1.7 uch ISSETPRINT(reg, PWROK);
289 1.7 uch #ifdef TX392X
290 1.7 uch ISSETPRINT(reg, PWROKNMI);
291 1.7 uch #endif /* TX392X */
292 1.7 uch ISSETPRINT(reg, SLOWBUS);
293 1.7 uch #ifdef TX391X
294 1.7 uch ISSETPRINT(reg, DIVMOD);
295 1.7 uch #endif /* TX391X */
296 1.7 uch ISSETPRINT(reg, ENSTPTIMER);
297 1.7 uch ISSETPRINT(reg, ENFORCESHUTDWN);
298 1.7 uch ISSETPRINT(reg, FORCESHUTDWN);
299 1.7 uch ISSETPRINT(reg, FORCESHUTDWNOCC);
300 1.7 uch ISSETPRINT(reg, SELC2MS);
301 1.7 uch #ifdef TX392X
302 1.7 uch ISSETPRINT(reg, WARMSTART);
303 1.7 uch #endif /* TX392X */
304 1.7 uch ISSETPRINT(reg, BPDBVCC3);
305 1.7 uch ISSETPRINT(reg, STOPCPU);
306 1.7 uch ISSETPRINT(reg, DBNCONBUTN);
307 1.7 uch ISSETPRINT(reg, COLDSTART);
308 1.7 uch ISSETPRINT(reg, PWRCS);
309 1.7 uch ISSETPRINT(reg, VCCON);
310 1.7 uch #ifdef TX391X
311 1.7 uch printf("VIDRF=%d ", TX39_POWERCTRL_VIDRF(reg));
312 1.7 uch #endif /* TX391X */
313 1.7 uch printf("STPTIMERVAL=%d ", TX39_POWERCTRL_STPTIMERVAL(reg));
314 1.7 uch printf("\n");
315 1.7 uch }
316 1.10 uch #endif /* TX39POWER_DEBUG */
317