tx39sib.c revision 1.16 1 1.16 drochner /* $NetBSD: tx39sib.c,v 1.16 2005/08/26 13:19:36 drochner Exp $ */
2 1.1 uch
3 1.8 uch /*-
4 1.8 uch * Copyright (c) 2000 The NetBSD Foundation, Inc.
5 1.1 uch * All rights reserved.
6 1.1 uch *
7 1.8 uch * This code is derived from software contributed to The NetBSD Foundation
8 1.8 uch * by UCHIYAMA Yasushi.
9 1.8 uch *
10 1.1 uch * Redistribution and use in source and binary forms, with or without
11 1.1 uch * modification, are permitted provided that the following conditions
12 1.1 uch * are met:
13 1.1 uch * 1. Redistributions of source code must retain the above copyright
14 1.1 uch * notice, this list of conditions and the following disclaimer.
15 1.8 uch * 2. Redistributions in binary form must reproduce the above copyright
16 1.8 uch * notice, this list of conditions and the following disclaimer in the
17 1.8 uch * documentation and/or other materials provided with the distribution.
18 1.8 uch * 3. All advertising materials mentioning features or use of this software
19 1.8 uch * must display the following acknowledgement:
20 1.8 uch * This product includes software developed by the NetBSD
21 1.8 uch * Foundation, Inc. and its contributors.
22 1.8 uch * 4. Neither the name of The NetBSD Foundation nor the names of its
23 1.8 uch * contributors may be used to endorse or promote products derived
24 1.8 uch * from this software without specific prior written permission.
25 1.1 uch *
26 1.8 uch * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 1.8 uch * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 1.8 uch * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 1.8 uch * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 1.8 uch * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 1.8 uch * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 1.8 uch * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 1.8 uch * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 1.8 uch * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 1.8 uch * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 1.8 uch * POSSIBILITY OF SUCH DAMAGE.
37 1.1 uch */
38 1.1 uch
39 1.1 uch /*
40 1.1 uch * TX39 SIB (Serial Interface Bus) module.
41 1.1 uch */
42 1.14 lukem
43 1.14 lukem #include <sys/cdefs.h>
44 1.16 drochner __KERNEL_RCSID(0, "$NetBSD: tx39sib.c,v 1.16 2005/08/26 13:19:36 drochner Exp $");
45 1.14 lukem
46 1.2 uch #undef TX39SIBDEBUG
47 1.1 uch
48 1.1 uch #include <sys/param.h>
49 1.1 uch #include <sys/systm.h>
50 1.1 uch #include <sys/device.h>
51 1.1 uch
52 1.1 uch #include <machine/bus.h>
53 1.1 uch #include <machine/intr.h>
54 1.1 uch
55 1.1 uch #include <hpcmips/tx/tx39var.h>
56 1.1 uch #include <hpcmips/tx/tx39icureg.h>
57 1.1 uch #include <hpcmips/tx/tx39sibvar.h>
58 1.1 uch #include <hpcmips/tx/tx39sibreg.h>
59 1.1 uch
60 1.1 uch #include "locators.h"
61 1.1 uch
62 1.1 uch #ifdef TX39SIBDEBUG
63 1.4 uch int tx39sibdebug = 0;
64 1.4 uch #define DPRINTF(arg) if (tx39sibdebug) printf arg;
65 1.1 uch #else
66 1.1 uch #define DPRINTF(arg)
67 1.1 uch #endif
68 1.1 uch
69 1.8 uch int tx39sib_match(struct device *, struct cfdata *, void *);
70 1.8 uch void tx39sib_attach(struct device *, struct device *, void *);
71 1.8 uch int tx39sib_print(void *, const char *);
72 1.15 drochner int tx39sib_search(struct device *, struct cfdata *,
73 1.16 drochner const int *, void *);
74 1.1 uch
75 1.2 uch #define TX39_CLK2X 18432000
76 1.2 uch const int sibsclk_divide_table[8] = {
77 1.2 uch 2, 3, 4, 5, 6, 8, 10, 12
78 1.2 uch };
79 1.2 uch
80 1.2 uch struct tx39sib_param {
81 1.2 uch /* SIB clock rate */
82 1.2 uch int sp_clock;
83 1.2 uch /*
84 1.2 uch * SIBMCLK = 18.432MHz = (CLK2X /4)
85 1.2 uch * SIBSCLK = SIBMCLK / sp_clock
86 1.2 uch * sp_clock start end divide module
87 1.2 uch * 0 7 8 2
88 1.2 uch * 1 6 8 3
89 1.2 uch * 2 6 9 4
90 1.2 uch * 3 5 9 5
91 1.2 uch * 4 5 10 6
92 1.2 uch * 5 4 11 8
93 1.2 uch * 6 3 12 10
94 1.2 uch * 7 2 13 12
95 1.2 uch */
96 1.2 uch /* sampling rate */
97 1.2 uch int sp_snd_rate; /* SNDFSDIV + 1 */
98 1.2 uch int sp_tel_rate; /* TELFSDIV + 1 */
99 1.2 uch /*
100 1.4 uch * Fs = (SIBSCLK * 2) / ((FSDIV + 1) * 64)
101 1.2 uch * FSDIV + 1 sampling rate
102 1.2 uch * 15 19.2k (1.6% error vs. CD-XA)
103 1.2 uch * 13 22.154k (0.47% error vs. CD-Audio)
104 1.2 uch * 22 7.85k (1.8% error vs. 8k)
105 1.2 uch */
106 1.2 uch /* data format 16/8bit */
107 1.2 uch int sp_sf0sndmode;
108 1.2 uch int sp_sf0telmode;
109 1.2 uch };
110 1.2 uch
111 1.4 uch struct tx39sib_param tx39sib_param_default_3912 = {
112 1.5 uch 0, /* SIBSCLK = 9.216MHz (div2) */
113 1.4 uch #if 0 /* setting sample */
114 1.4 uch 40, /* audio: 7.2kHz */
115 1.4 uch 26, /* audio: CD-Audio(/4) 11.077kHz*/
116 1.4 uch 6, /* audio: 48kHz */
117 1.4 uch #endif
118 1.4 uch 13, /* audio: CD-Audio(/2 = 22.050) 22.154kHz*/
119 1.4 uch 40, /* telecom: 7.2kHz */
120 1.4 uch TX39_SIBCTRL_SND16, /* Audio 16bit mono */
121 1.4 uch TX39_SIBCTRL_TEL16 /* Telecom 16bit mono */
122 1.4 uch };
123 1.4 uch
124 1.4 uch struct tx39sib_param tx39sib_param_default_3922 = {
125 1.5 uch 7, /* SIBSCLK = 9.216MHz (div1) */
126 1.5 uch 13, /* audio: CD-Audio(/2 = 22.050) 22.154kHz*/
127 1.2 uch 40, /* telecom: 7.2kHz */
128 1.2 uch TX39_SIBCTRL_SND16, /* Audio 16bit mono */
129 1.2 uch TX39_SIBCTRL_TEL16 /* Telecom 16bit mono */
130 1.2 uch };
131 1.2 uch
132 1.1 uch struct tx39sib_softc {
133 1.1 uch struct device sc_dev;
134 1.1 uch tx_chipset_tag_t sc_tc;
135 1.1 uch
136 1.2 uch struct tx39sib_param sc_param;
137 1.1 uch int sc_attached;
138 1.1 uch };
139 1.1 uch
140 1.8 uch __inline int __txsibsf0_ready(tx_chipset_tag_t);
141 1.4 uch #ifdef TX39SIBDEBUG
142 1.8 uch void tx39sib_dump(struct tx39sib_softc *);
143 1.4 uch #endif
144 1.1 uch
145 1.12 thorpej CFATTACH_DECL(tx39sib, sizeof(struct tx39sib_softc),
146 1.12 thorpej tx39sib_match, tx39sib_attach, NULL, NULL);
147 1.1 uch
148 1.1 uch int
149 1.8 uch tx39sib_match(struct device *parent, struct cfdata *cf, void *aux)
150 1.1 uch {
151 1.8 uch return (ATTACH_FIRST);
152 1.1 uch }
153 1.1 uch
154 1.1 uch void
155 1.8 uch tx39sib_attach(struct device *parent, struct device *self, void *aux)
156 1.1 uch {
157 1.1 uch struct txsim_attach_args *ta = aux;
158 1.1 uch struct tx39sib_softc *sc = (void*)self;
159 1.1 uch tx_chipset_tag_t tc;
160 1.2 uch
161 1.1 uch sc->sc_tc = tc = ta->ta_tc;
162 1.1 uch
163 1.2 uch /* set default param */
164 1.4 uch #ifdef TX391X
165 1.4 uch sc->sc_param = tx39sib_param_default_3912;
166 1.4 uch #endif /* TX391X */
167 1.4 uch #ifdef TX392X
168 1.4 uch sc->sc_param = tx39sib_param_default_3922;
169 1.4 uch #endif /* TX392X */
170 1.4 uch
171 1.2 uch #define MHZ(a) ((a) / 1000000), (((a) % 1000000) / 1000)
172 1.2 uch printf(": %d.%03d MHz", MHZ(tx39sib_clock(self)));
173 1.2 uch
174 1.1 uch printf("\n");
175 1.1 uch #ifdef TX39SIBDEBUG
176 1.4 uch if (tx39sibdebug)
177 1.4 uch tx39sib_dump(sc);
178 1.1 uch #endif
179 1.2 uch /* enable subframe0 */
180 1.2 uch tx39sib_enable1(self);
181 1.2 uch /* enable SIB */
182 1.2 uch tx39sib_enable2(self);
183 1.2 uch
184 1.2 uch #ifdef TX39SIBDEBUG
185 1.4 uch if (tx39sibdebug)
186 1.4 uch tx39sib_dump(sc);
187 1.2 uch #endif
188 1.2 uch
189 1.15 drochner config_search_ia(tx39sib_search, self, "txsibif", tx39sib_print);
190 1.2 uch }
191 1.2 uch
192 1.2 uch void
193 1.8 uch tx39sib_enable1(struct device *dev)
194 1.2 uch {
195 1.2 uch struct tx39sib_softc *sc = (void*)dev;
196 1.2 uch struct tx39sib_param *param = &sc->sc_param;
197 1.2 uch tx_chipset_tag_t tc = sc->sc_tc;
198 1.2 uch
199 1.2 uch txreg_t reg;
200 1.2 uch
201 1.2 uch /* disable SIB */
202 1.2 uch tx39sib_disable(dev);
203 1.2 uch
204 1.2 uch /* setup */
205 1.2 uch reg = 0;
206 1.2 uch /* SIB clock rate */
207 1.2 uch reg = TX39_SIBCTRL_SCLKDIV_SET(reg, param->sp_clock);
208 1.2 uch /* sampling rate (sound) */
209 1.2 uch reg = TX39_SIBCTRL_SNDFSDIV_SET(reg, param->sp_snd_rate - 1);
210 1.2 uch /* sampling rate (telecom) */
211 1.2 uch reg = TX39_SIBCTRL_TELFSDIV_SET(reg, param->sp_tel_rate - 1);
212 1.2 uch /* data format (8/16bit) */
213 1.2 uch reg |= param->sp_sf0sndmode;
214 1.2 uch reg |= param->sp_sf0telmode;
215 1.2 uch tx_conf_write(tc, TX39_SIBCTRL_REG, reg);
216 1.2 uch
217 1.2 uch /* DMA */
218 1.2 uch reg = tx_conf_read(tc, TX39_SIBDMACTRL_REG);
219 1.2 uch reg &= ~(TX39_SIBDMACTRL_ENDMARXSND |
220 1.8 uch TX39_SIBDMACTRL_ENDMATXSND |
221 1.8 uch TX39_SIBDMACTRL_ENDMARXTEL |
222 1.8 uch TX39_SIBDMACTRL_ENDMATXTEL);
223 1.2 uch tx_conf_write(tc, TX39_SIBDMACTRL_REG, reg);
224 1.2 uch
225 1.1 uch /*
226 1.2 uch * Enable subframe0 (BETTY)
227 1.1 uch */
228 1.1 uch reg = tx_conf_read(tc, TX39_SIBCTRL_REG);
229 1.1 uch reg |= TX39_SIBCTRL_ENSF0;
230 1.1 uch tx_conf_write(tc, TX39_SIBCTRL_REG, reg);
231 1.2 uch }
232 1.2 uch
233 1.2 uch void
234 1.8 uch tx39sib_enable2(struct device *dev)
235 1.2 uch {
236 1.2 uch struct tx39sib_softc *sc = (void*)dev;
237 1.2 uch tx_chipset_tag_t tc = sc->sc_tc;
238 1.2 uch txreg_t reg;
239 1.2 uch
240 1.2 uch reg = tx_conf_read(tc, TX39_SIBCTRL_REG);
241 1.2 uch reg |= TX39_SIBCTRL_ENSIB;
242 1.2 uch tx_conf_write(tc, TX39_SIBCTRL_REG, reg);
243 1.2 uch }
244 1.1 uch
245 1.2 uch void
246 1.8 uch tx39sib_disable(struct device *dev)
247 1.2 uch {
248 1.2 uch struct tx39sib_softc *sc = (void*)dev;
249 1.2 uch tx_chipset_tag_t tc = sc->sc_tc;
250 1.2 uch txreg_t reg;
251 1.2 uch /* disable codec side */
252 1.2 uch /* notyet */
253 1.2 uch
254 1.2 uch /* disable TX39 side */
255 1.1 uch reg = tx_conf_read(tc, TX39_SIBCTRL_REG);
256 1.2 uch reg &= ~(TX39_SIBCTRL_ENTEL | TX39_SIBCTRL_ENSND);
257 1.1 uch tx_conf_write(tc, TX39_SIBCTRL_REG, reg);
258 1.1 uch
259 1.2 uch /*
260 1.2 uch * Disable subframe0/1 (BETTY/external codec)
261 1.1 uch */
262 1.1 uch reg = tx_conf_read(tc, TX39_SIBCTRL_REG);
263 1.2 uch reg &= ~TX39_SIBCTRL_ENSF0;
264 1.2 uch reg &= ~(TX39_SIBCTRL_ENSF1 | TX39_SIBCTRL_SELTELSF1 |
265 1.8 uch TX39_SIBCTRL_SELSNDSF1);
266 1.1 uch tx_conf_write(tc, TX39_SIBCTRL_REG, reg);
267 1.1 uch
268 1.2 uch /* disable TX39SIB module */
269 1.2 uch reg &= ~TX39_SIBCTRL_ENSIB;
270 1.2 uch tx_conf_write(tc, TX39_SIBCTRL_REG, reg);
271 1.1 uch }
272 1.1 uch
273 1.2 uch int
274 1.8 uch tx39sib_clock(struct device *dev)
275 1.2 uch {
276 1.2 uch struct tx39sib_softc *sc = (void*)dev;
277 1.2 uch
278 1.8 uch return (TX39_CLK2X / sibsclk_divide_table[sc->sc_param.sp_clock]);
279 1.2 uch }
280 1.1 uch
281 1.1 uch int
282 1.15 drochner tx39sib_search(struct device *parent, struct cfdata *cf,
283 1.16 drochner const int *ldesc, void *aux)
284 1.1 uch {
285 1.1 uch struct tx39sib_softc *sc = (void*)parent;
286 1.1 uch struct txsib_attach_args sa;
287 1.1 uch
288 1.1 uch sa.sa_tc = sc->sc_tc;
289 1.1 uch sa.sa_slot = cf->cf_loc[TXSIBIFCF_SLOT];
290 1.2 uch sa.sa_snd_rate = sc->sc_param.sp_snd_rate;
291 1.2 uch sa.sa_tel_rate = sc->sc_param.sp_tel_rate;
292 1.1 uch
293 1.1 uch if (sa.sa_slot == TXSIBIFCF_SLOT_DEFAULT) {
294 1.1 uch printf("tx39sib_search: wildcarded slot, skipping\n");
295 1.8 uch return (0);
296 1.1 uch }
297 1.1 uch
298 1.1 uch if (!(sc->sc_attached & (1 << sa.sa_slot)) &&/* not attached slot */
299 1.10 thorpej config_match(parent, cf, &sa)) {
300 1.1 uch config_attach(parent, cf, &sa, tx39sib_print);
301 1.1 uch sc->sc_attached |= (1 << sa.sa_slot);
302 1.1 uch }
303 1.1 uch
304 1.8 uch return (0);
305 1.1 uch }
306 1.1 uch
307 1.1 uch int
308 1.8 uch tx39sib_print(void *aux, const char *pnp)
309 1.1 uch {
310 1.1 uch struct txsib_attach_args *sa = aux;
311 1.1 uch
312 1.13 thorpej aprint_normal(" slot %d", sa->sa_slot);
313 1.1 uch
314 1.8 uch return (QUIET);
315 1.1 uch }
316 1.1 uch
317 1.1 uch /*
318 1.1 uch * sync access method. don't use runtime.
319 1.1 uch */
320 1.1 uch
321 1.8 uch __inline__ int
322 1.8 uch __txsibsf0_ready(tx_chipset_tag_t tc)
323 1.1 uch {
324 1.1 uch int i;
325 1.1 uch
326 1.1 uch tx_conf_write(tc, TX39_INTRSTATUS1_REG, TX39_INTRSTATUS1_SIBSF0INT);
327 1.1 uch for (i = 0; (!(tx_conf_read(tc, TX39_INTRSTATUS1_REG) &
328 1.8 uch TX39_INTRSTATUS1_SIBSF0INT)) && i < 1000; i++) {
329 1.6 uch if (i > 100 && !(i % 100)) {
330 1.6 uch printf("sf0 busy loop: retry count %d\n", i);
331 1.6 uch }
332 1.6 uch }
333 1.6 uch
334 1.6 uch if (i >= 1000) {
335 1.1 uch printf("sf0 busy\n");
336 1.8 uch return (0);
337 1.1 uch }
338 1.1 uch
339 1.8 uch return (1);
340 1.1 uch }
341 1.1 uch
342 1.1 uch void
343 1.8 uch txsibsf0_reg_write(tx_chipset_tag_t tc, int addr, u_int16_t val)
344 1.1 uch {
345 1.1 uch txreg_t reg;
346 1.1 uch
347 1.1 uch reg = txsibsf0_read(tc, addr);
348 1.1 uch reg |= TX39_SIBSF0_WRITE;
349 1.1 uch TX39_SIBSF0_REGDATA_CLR(reg);
350 1.1 uch reg = TX39_SIBSF0_REGDATA_SET(reg, val);
351 1.1 uch
352 1.1 uch __txsibsf0_ready(tc);
353 1.1 uch tx_conf_write(tc, TX39_SIBSF0CTRL_REG, reg);
354 1.1 uch }
355 1.1 uch
356 1.1 uch u_int16_t
357 1.8 uch txsibsf0_reg_read(tx_chipset_tag_t tc, int addr)
358 1.1 uch {
359 1.8 uch return (TX39_SIBSF0_REGDATA(txsibsf0_read(tc, addr)));
360 1.1 uch }
361 1.1 uch
362 1.1 uch u_int32_t
363 1.8 uch txsibsf0_read(tx_chipset_tag_t tc, int addr)
364 1.1 uch {
365 1.1 uch txreg_t reg;
366 1.1 uch int retry = 3;
367 1.1 uch
368 1.1 uch do {
369 1.1 uch reg = TX39_SIBSF0_REGADDR_SET(0, addr);
370 1.1 uch __txsibsf0_ready(tc);
371 1.1 uch tx_conf_write(tc, TX39_SIBSF0CTRL_REG, reg);
372 1.1 uch
373 1.1 uch __txsibsf0_ready(tc);
374 1.1 uch reg = tx_conf_read(tc, TX39_SIBSF0STAT_REG);
375 1.1 uch
376 1.1 uch } while ((TX39_SIBSF0_REGADDR(reg) != addr) && --retry > 0);
377 1.1 uch
378 1.1 uch if (retry <= 0)
379 1.1 uch printf("txsibsf0_read: command failed\n");
380 1.1 uch
381 1.8 uch return (reg);
382 1.1 uch }
383 1.1 uch
384 1.4 uch #ifdef TX39SIBDEBUG
385 1.8 uch #define ISSETPRINT_CTRL(r, m) \
386 1.9 uch dbg_bitmask_print(r, TX39_SIBCTRL_##m, #m)
387 1.8 uch #define ISSETPRINT_DMACTRL(r, m) \
388 1.9 uch dbg_bitmask_print(r, TX39_SIBDMACTRL_##m, #m)
389 1.1 uch
390 1.1 uch void
391 1.8 uch tx39sib_dump(struct tx39sib_softc *sc)
392 1.1 uch {
393 1.1 uch tx_chipset_tag_t tc = sc->sc_tc;
394 1.1 uch txreg_t reg;
395 1.1 uch
396 1.1 uch reg = tx_conf_read(tc, TX39_SIBCTRL_REG);
397 1.1 uch ISSETPRINT_CTRL(reg, SIBIRQ);
398 1.1 uch ISSETPRINT_CTRL(reg, ENCNTTEST);
399 1.1 uch ISSETPRINT_CTRL(reg, ENDMATEST);
400 1.1 uch ISSETPRINT_CTRL(reg, SNDMONO);
401 1.1 uch ISSETPRINT_CTRL(reg, RMONOSNDIN);
402 1.1 uch ISSETPRINT_CTRL(reg, TEL16);
403 1.1 uch ISSETPRINT_CTRL(reg, SND16);
404 1.1 uch ISSETPRINT_CTRL(reg, SELTELSF1);
405 1.1 uch ISSETPRINT_CTRL(reg, SELSNDSF1);
406 1.1 uch ISSETPRINT_CTRL(reg, ENTEL);
407 1.1 uch ISSETPRINT_CTRL(reg, ENSND);
408 1.1 uch ISSETPRINT_CTRL(reg, SIBLOOP);
409 1.1 uch ISSETPRINT_CTRL(reg, ENSF1);
410 1.1 uch ISSETPRINT_CTRL(reg, ENSF0);
411 1.1 uch ISSETPRINT_CTRL(reg, ENSIB);
412 1.1 uch printf("\n");
413 1.1 uch printf("SCLKDIV %d\n", TX39_SIBCTRL_SCLKDIV(reg));
414 1.1 uch printf("TELFSDIV %d\n", TX39_SIBCTRL_TELFSDIV(reg));
415 1.1 uch printf("SNDFSDIV %d\n", TX39_SIBCTRL_SNDFSDIV(reg));
416 1.1 uch
417 1.1 uch reg = tx_conf_read(tc, TX39_SIBDMACTRL_REG);
418 1.1 uch ISSETPRINT_DMACTRL(reg, SNDBUFF1TIME);
419 1.1 uch ISSETPRINT_DMACTRL(reg, SNDDMALOOP);
420 1.1 uch ISSETPRINT_DMACTRL(reg, ENDMARXSND);
421 1.1 uch ISSETPRINT_DMACTRL(reg, ENDMATXSND);
422 1.1 uch ISSETPRINT_DMACTRL(reg, TELBUFF1TIME);
423 1.1 uch ISSETPRINT_DMACTRL(reg, TELDMALOOP);
424 1.1 uch ISSETPRINT_DMACTRL(reg, ENDMARXTEL);
425 1.1 uch ISSETPRINT_DMACTRL(reg, ENDMATXTEL);
426 1.1 uch printf("\n");
427 1.1 uch printf("SNDDMAPTR %d\n", TX39_SIBDMACTRL_TELDMAPTR(reg));
428 1.1 uch printf("TELDMAPTR %d\n", TX39_SIBDMACTRL_SNDDMAPTR(reg));
429 1.1 uch
430 1.1 uch }
431 1.4 uch #endif /* TX39SIBDEBUG */
432