tx39sib.c revision 1.23 1 1.23 thorpej /* $NetBSD: tx39sib.c,v 1.23 2021/08/07 16:18:54 thorpej Exp $ */
2 1.1 uch
3 1.8 uch /*-
4 1.8 uch * Copyright (c) 2000 The NetBSD Foundation, Inc.
5 1.1 uch * All rights reserved.
6 1.1 uch *
7 1.8 uch * This code is derived from software contributed to The NetBSD Foundation
8 1.8 uch * by UCHIYAMA Yasushi.
9 1.8 uch *
10 1.1 uch * Redistribution and use in source and binary forms, with or without
11 1.1 uch * modification, are permitted provided that the following conditions
12 1.1 uch * are met:
13 1.1 uch * 1. Redistributions of source code must retain the above copyright
14 1.1 uch * notice, this list of conditions and the following disclaimer.
15 1.8 uch * 2. Redistributions in binary form must reproduce the above copyright
16 1.8 uch * notice, this list of conditions and the following disclaimer in the
17 1.8 uch * documentation and/or other materials provided with the distribution.
18 1.1 uch *
19 1.8 uch * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 1.8 uch * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 1.8 uch * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 1.8 uch * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 1.8 uch * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 1.8 uch * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 1.8 uch * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 1.8 uch * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 1.8 uch * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 1.8 uch * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 1.8 uch * POSSIBILITY OF SUCH DAMAGE.
30 1.1 uch */
31 1.1 uch
32 1.1 uch /*
33 1.1 uch * TX39 SIB (Serial Interface Bus) module.
34 1.1 uch */
35 1.14 lukem
36 1.14 lukem #include <sys/cdefs.h>
37 1.23 thorpej __KERNEL_RCSID(0, "$NetBSD: tx39sib.c,v 1.23 2021/08/07 16:18:54 thorpej Exp $");
38 1.14 lukem
39 1.2 uch #undef TX39SIBDEBUG
40 1.1 uch
41 1.1 uch #include <sys/param.h>
42 1.1 uch #include <sys/systm.h>
43 1.1 uch #include <sys/device.h>
44 1.1 uch
45 1.1 uch #include <machine/bus.h>
46 1.1 uch #include <machine/intr.h>
47 1.1 uch
48 1.1 uch #include <hpcmips/tx/tx39var.h>
49 1.1 uch #include <hpcmips/tx/tx39icureg.h>
50 1.1 uch #include <hpcmips/tx/tx39sibvar.h>
51 1.1 uch #include <hpcmips/tx/tx39sibreg.h>
52 1.1 uch
53 1.1 uch #include "locators.h"
54 1.1 uch
55 1.1 uch #ifdef TX39SIBDEBUG
56 1.4 uch int tx39sibdebug = 0;
57 1.4 uch #define DPRINTF(arg) if (tx39sibdebug) printf arg;
58 1.1 uch #else
59 1.1 uch #define DPRINTF(arg)
60 1.1 uch #endif
61 1.1 uch
62 1.21 chs int tx39sib_match(device_t, cfdata_t, void *);
63 1.21 chs void tx39sib_attach(device_t, device_t, void *);
64 1.8 uch int tx39sib_print(void *, const char *);
65 1.21 chs int tx39sib_search(device_t, cfdata_t, const int *, void *);
66 1.1 uch
67 1.2 uch #define TX39_CLK2X 18432000
68 1.2 uch const int sibsclk_divide_table[8] = {
69 1.2 uch 2, 3, 4, 5, 6, 8, 10, 12
70 1.2 uch };
71 1.2 uch
72 1.2 uch struct tx39sib_param {
73 1.2 uch /* SIB clock rate */
74 1.2 uch int sp_clock;
75 1.2 uch /*
76 1.2 uch * SIBMCLK = 18.432MHz = (CLK2X /4)
77 1.2 uch * SIBSCLK = SIBMCLK / sp_clock
78 1.2 uch * sp_clock start end divide module
79 1.2 uch * 0 7 8 2
80 1.2 uch * 1 6 8 3
81 1.2 uch * 2 6 9 4
82 1.2 uch * 3 5 9 5
83 1.2 uch * 4 5 10 6
84 1.2 uch * 5 4 11 8
85 1.2 uch * 6 3 12 10
86 1.2 uch * 7 2 13 12
87 1.2 uch */
88 1.2 uch /* sampling rate */
89 1.2 uch int sp_snd_rate; /* SNDFSDIV + 1 */
90 1.2 uch int sp_tel_rate; /* TELFSDIV + 1 */
91 1.2 uch /*
92 1.4 uch * Fs = (SIBSCLK * 2) / ((FSDIV + 1) * 64)
93 1.2 uch * FSDIV + 1 sampling rate
94 1.2 uch * 15 19.2k (1.6% error vs. CD-XA)
95 1.2 uch * 13 22.154k (0.47% error vs. CD-Audio)
96 1.2 uch * 22 7.85k (1.8% error vs. 8k)
97 1.2 uch */
98 1.2 uch /* data format 16/8bit */
99 1.2 uch int sp_sf0sndmode;
100 1.2 uch int sp_sf0telmode;
101 1.2 uch };
102 1.2 uch
103 1.4 uch struct tx39sib_param tx39sib_param_default_3912 = {
104 1.5 uch 0, /* SIBSCLK = 9.216MHz (div2) */
105 1.4 uch #if 0 /* setting sample */
106 1.4 uch 40, /* audio: 7.2kHz */
107 1.4 uch 26, /* audio: CD-Audio(/4) 11.077kHz*/
108 1.4 uch 6, /* audio: 48kHz */
109 1.4 uch #endif
110 1.4 uch 13, /* audio: CD-Audio(/2 = 22.050) 22.154kHz*/
111 1.4 uch 40, /* telecom: 7.2kHz */
112 1.4 uch TX39_SIBCTRL_SND16, /* Audio 16bit mono */
113 1.4 uch TX39_SIBCTRL_TEL16 /* Telecom 16bit mono */
114 1.4 uch };
115 1.4 uch
116 1.4 uch struct tx39sib_param tx39sib_param_default_3922 = {
117 1.5 uch 7, /* SIBSCLK = 9.216MHz (div1) */
118 1.5 uch 13, /* audio: CD-Audio(/2 = 22.050) 22.154kHz*/
119 1.2 uch 40, /* telecom: 7.2kHz */
120 1.2 uch TX39_SIBCTRL_SND16, /* Audio 16bit mono */
121 1.2 uch TX39_SIBCTRL_TEL16 /* Telecom 16bit mono */
122 1.2 uch };
123 1.2 uch
124 1.1 uch struct tx39sib_softc {
125 1.1 uch tx_chipset_tag_t sc_tc;
126 1.1 uch
127 1.2 uch struct tx39sib_param sc_param;
128 1.1 uch int sc_attached;
129 1.1 uch };
130 1.1 uch
131 1.18 perry inline int __txsibsf0_ready(tx_chipset_tag_t);
132 1.4 uch #ifdef TX39SIBDEBUG
133 1.8 uch void tx39sib_dump(struct tx39sib_softc *);
134 1.4 uch #endif
135 1.1 uch
136 1.21 chs CFATTACH_DECL_NEW(tx39sib, sizeof(struct tx39sib_softc),
137 1.12 thorpej tx39sib_match, tx39sib_attach, NULL, NULL);
138 1.1 uch
139 1.1 uch int
140 1.21 chs tx39sib_match(device_t parent, cfdata_t cf, void *aux)
141 1.1 uch {
142 1.8 uch return (ATTACH_FIRST);
143 1.1 uch }
144 1.1 uch
145 1.1 uch void
146 1.21 chs tx39sib_attach(device_t parent, device_t self, void *aux)
147 1.1 uch {
148 1.1 uch struct txsim_attach_args *ta = aux;
149 1.21 chs struct tx39sib_softc *sc = device_private(self);
150 1.1 uch tx_chipset_tag_t tc;
151 1.2 uch
152 1.1 uch sc->sc_tc = tc = ta->ta_tc;
153 1.1 uch
154 1.2 uch /* set default param */
155 1.4 uch #ifdef TX391X
156 1.4 uch sc->sc_param = tx39sib_param_default_3912;
157 1.4 uch #endif /* TX391X */
158 1.4 uch #ifdef TX392X
159 1.4 uch sc->sc_param = tx39sib_param_default_3922;
160 1.4 uch #endif /* TX392X */
161 1.4 uch
162 1.2 uch #define MHZ(a) ((a) / 1000000), (((a) % 1000000) / 1000)
163 1.2 uch printf(": %d.%03d MHz", MHZ(tx39sib_clock(self)));
164 1.2 uch
165 1.1 uch printf("\n");
166 1.1 uch #ifdef TX39SIBDEBUG
167 1.4 uch if (tx39sibdebug)
168 1.4 uch tx39sib_dump(sc);
169 1.1 uch #endif
170 1.2 uch /* enable subframe0 */
171 1.2 uch tx39sib_enable1(self);
172 1.2 uch /* enable SIB */
173 1.2 uch tx39sib_enable2(self);
174 1.2 uch
175 1.2 uch #ifdef TX39SIBDEBUG
176 1.4 uch if (tx39sibdebug)
177 1.4 uch tx39sib_dump(sc);
178 1.2 uch #endif
179 1.2 uch
180 1.22 thorpej config_search(self, NULL,
181 1.23 thorpej CFARGS(.search = tx39sib_search));
182 1.2 uch }
183 1.2 uch
184 1.2 uch void
185 1.21 chs tx39sib_enable1(device_t dev)
186 1.2 uch {
187 1.21 chs struct tx39sib_softc *sc = device_private(dev);
188 1.2 uch struct tx39sib_param *param = &sc->sc_param;
189 1.2 uch tx_chipset_tag_t tc = sc->sc_tc;
190 1.2 uch
191 1.2 uch txreg_t reg;
192 1.2 uch
193 1.2 uch /* disable SIB */
194 1.2 uch tx39sib_disable(dev);
195 1.2 uch
196 1.2 uch /* setup */
197 1.2 uch reg = 0;
198 1.2 uch /* SIB clock rate */
199 1.2 uch reg = TX39_SIBCTRL_SCLKDIV_SET(reg, param->sp_clock);
200 1.2 uch /* sampling rate (sound) */
201 1.2 uch reg = TX39_SIBCTRL_SNDFSDIV_SET(reg, param->sp_snd_rate - 1);
202 1.2 uch /* sampling rate (telecom) */
203 1.2 uch reg = TX39_SIBCTRL_TELFSDIV_SET(reg, param->sp_tel_rate - 1);
204 1.2 uch /* data format (8/16bit) */
205 1.2 uch reg |= param->sp_sf0sndmode;
206 1.2 uch reg |= param->sp_sf0telmode;
207 1.2 uch tx_conf_write(tc, TX39_SIBCTRL_REG, reg);
208 1.2 uch
209 1.2 uch /* DMA */
210 1.2 uch reg = tx_conf_read(tc, TX39_SIBDMACTRL_REG);
211 1.2 uch reg &= ~(TX39_SIBDMACTRL_ENDMARXSND |
212 1.8 uch TX39_SIBDMACTRL_ENDMATXSND |
213 1.8 uch TX39_SIBDMACTRL_ENDMARXTEL |
214 1.8 uch TX39_SIBDMACTRL_ENDMATXTEL);
215 1.2 uch tx_conf_write(tc, TX39_SIBDMACTRL_REG, reg);
216 1.2 uch
217 1.1 uch /*
218 1.2 uch * Enable subframe0 (BETTY)
219 1.1 uch */
220 1.1 uch reg = tx_conf_read(tc, TX39_SIBCTRL_REG);
221 1.1 uch reg |= TX39_SIBCTRL_ENSF0;
222 1.1 uch tx_conf_write(tc, TX39_SIBCTRL_REG, reg);
223 1.2 uch }
224 1.2 uch
225 1.2 uch void
226 1.21 chs tx39sib_enable2(device_t dev)
227 1.2 uch {
228 1.21 chs struct tx39sib_softc *sc = device_private(dev);
229 1.2 uch tx_chipset_tag_t tc = sc->sc_tc;
230 1.2 uch txreg_t reg;
231 1.2 uch
232 1.2 uch reg = tx_conf_read(tc, TX39_SIBCTRL_REG);
233 1.2 uch reg |= TX39_SIBCTRL_ENSIB;
234 1.2 uch tx_conf_write(tc, TX39_SIBCTRL_REG, reg);
235 1.2 uch }
236 1.1 uch
237 1.2 uch void
238 1.21 chs tx39sib_disable(device_t dev)
239 1.2 uch {
240 1.21 chs struct tx39sib_softc *sc = device_private(dev);
241 1.2 uch tx_chipset_tag_t tc = sc->sc_tc;
242 1.2 uch txreg_t reg;
243 1.2 uch /* disable codec side */
244 1.2 uch /* notyet */
245 1.2 uch
246 1.2 uch /* disable TX39 side */
247 1.1 uch reg = tx_conf_read(tc, TX39_SIBCTRL_REG);
248 1.2 uch reg &= ~(TX39_SIBCTRL_ENTEL | TX39_SIBCTRL_ENSND);
249 1.1 uch tx_conf_write(tc, TX39_SIBCTRL_REG, reg);
250 1.1 uch
251 1.2 uch /*
252 1.2 uch * Disable subframe0/1 (BETTY/external codec)
253 1.1 uch */
254 1.1 uch reg = tx_conf_read(tc, TX39_SIBCTRL_REG);
255 1.2 uch reg &= ~TX39_SIBCTRL_ENSF0;
256 1.2 uch reg &= ~(TX39_SIBCTRL_ENSF1 | TX39_SIBCTRL_SELTELSF1 |
257 1.8 uch TX39_SIBCTRL_SELSNDSF1);
258 1.1 uch tx_conf_write(tc, TX39_SIBCTRL_REG, reg);
259 1.1 uch
260 1.2 uch /* disable TX39SIB module */
261 1.2 uch reg &= ~TX39_SIBCTRL_ENSIB;
262 1.2 uch tx_conf_write(tc, TX39_SIBCTRL_REG, reg);
263 1.1 uch }
264 1.1 uch
265 1.2 uch int
266 1.21 chs tx39sib_clock(device_t dev)
267 1.2 uch {
268 1.21 chs struct tx39sib_softc *sc = device_private(dev);
269 1.2 uch
270 1.8 uch return (TX39_CLK2X / sibsclk_divide_table[sc->sc_param.sp_clock]);
271 1.2 uch }
272 1.1 uch
273 1.1 uch int
274 1.21 chs tx39sib_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux)
275 1.1 uch {
276 1.21 chs struct tx39sib_softc *sc = device_private(parent);
277 1.1 uch struct txsib_attach_args sa;
278 1.1 uch
279 1.1 uch sa.sa_tc = sc->sc_tc;
280 1.1 uch sa.sa_slot = cf->cf_loc[TXSIBIFCF_SLOT];
281 1.2 uch sa.sa_snd_rate = sc->sc_param.sp_snd_rate;
282 1.2 uch sa.sa_tel_rate = sc->sc_param.sp_tel_rate;
283 1.1 uch
284 1.1 uch if (sa.sa_slot == TXSIBIFCF_SLOT_DEFAULT) {
285 1.1 uch printf("tx39sib_search: wildcarded slot, skipping\n");
286 1.8 uch return (0);
287 1.1 uch }
288 1.1 uch
289 1.1 uch if (!(sc->sc_attached & (1 << sa.sa_slot)) &&/* not attached slot */
290 1.22 thorpej config_probe(parent, cf, &sa)) {
291 1.23 thorpej config_attach(parent, cf, &sa, tx39sib_print, CFARGS_NONE);
292 1.1 uch sc->sc_attached |= (1 << sa.sa_slot);
293 1.1 uch }
294 1.1 uch
295 1.8 uch return (0);
296 1.1 uch }
297 1.1 uch
298 1.1 uch int
299 1.8 uch tx39sib_print(void *aux, const char *pnp)
300 1.1 uch {
301 1.1 uch struct txsib_attach_args *sa = aux;
302 1.1 uch
303 1.13 thorpej aprint_normal(" slot %d", sa->sa_slot);
304 1.1 uch
305 1.8 uch return (QUIET);
306 1.1 uch }
307 1.1 uch
308 1.1 uch /*
309 1.1 uch * sync access method. don't use runtime.
310 1.1 uch */
311 1.1 uch
312 1.19 perry inline int
313 1.8 uch __txsibsf0_ready(tx_chipset_tag_t tc)
314 1.1 uch {
315 1.1 uch int i;
316 1.1 uch
317 1.1 uch tx_conf_write(tc, TX39_INTRSTATUS1_REG, TX39_INTRSTATUS1_SIBSF0INT);
318 1.1 uch for (i = 0; (!(tx_conf_read(tc, TX39_INTRSTATUS1_REG) &
319 1.8 uch TX39_INTRSTATUS1_SIBSF0INT)) && i < 1000; i++) {
320 1.6 uch if (i > 100 && !(i % 100)) {
321 1.6 uch printf("sf0 busy loop: retry count %d\n", i);
322 1.6 uch }
323 1.6 uch }
324 1.6 uch
325 1.6 uch if (i >= 1000) {
326 1.1 uch printf("sf0 busy\n");
327 1.8 uch return (0);
328 1.1 uch }
329 1.1 uch
330 1.8 uch return (1);
331 1.1 uch }
332 1.1 uch
333 1.1 uch void
334 1.8 uch txsibsf0_reg_write(tx_chipset_tag_t tc, int addr, u_int16_t val)
335 1.1 uch {
336 1.1 uch txreg_t reg;
337 1.1 uch
338 1.1 uch reg = txsibsf0_read(tc, addr);
339 1.1 uch reg |= TX39_SIBSF0_WRITE;
340 1.1 uch TX39_SIBSF0_REGDATA_CLR(reg);
341 1.1 uch reg = TX39_SIBSF0_REGDATA_SET(reg, val);
342 1.1 uch
343 1.1 uch __txsibsf0_ready(tc);
344 1.1 uch tx_conf_write(tc, TX39_SIBSF0CTRL_REG, reg);
345 1.1 uch }
346 1.1 uch
347 1.1 uch u_int16_t
348 1.8 uch txsibsf0_reg_read(tx_chipset_tag_t tc, int addr)
349 1.1 uch {
350 1.8 uch return (TX39_SIBSF0_REGDATA(txsibsf0_read(tc, addr)));
351 1.1 uch }
352 1.1 uch
353 1.1 uch u_int32_t
354 1.8 uch txsibsf0_read(tx_chipset_tag_t tc, int addr)
355 1.1 uch {
356 1.1 uch txreg_t reg;
357 1.1 uch int retry = 3;
358 1.1 uch
359 1.1 uch do {
360 1.1 uch reg = TX39_SIBSF0_REGADDR_SET(0, addr);
361 1.1 uch __txsibsf0_ready(tc);
362 1.1 uch tx_conf_write(tc, TX39_SIBSF0CTRL_REG, reg);
363 1.1 uch
364 1.1 uch __txsibsf0_ready(tc);
365 1.1 uch reg = tx_conf_read(tc, TX39_SIBSF0STAT_REG);
366 1.1 uch
367 1.1 uch } while ((TX39_SIBSF0_REGADDR(reg) != addr) && --retry > 0);
368 1.1 uch
369 1.1 uch if (retry <= 0)
370 1.1 uch printf("txsibsf0_read: command failed\n");
371 1.1 uch
372 1.8 uch return (reg);
373 1.1 uch }
374 1.1 uch
375 1.4 uch #ifdef TX39SIBDEBUG
376 1.8 uch #define ISSETPRINT_CTRL(r, m) \
377 1.9 uch dbg_bitmask_print(r, TX39_SIBCTRL_##m, #m)
378 1.8 uch #define ISSETPRINT_DMACTRL(r, m) \
379 1.9 uch dbg_bitmask_print(r, TX39_SIBDMACTRL_##m, #m)
380 1.1 uch
381 1.1 uch void
382 1.8 uch tx39sib_dump(struct tx39sib_softc *sc)
383 1.1 uch {
384 1.1 uch tx_chipset_tag_t tc = sc->sc_tc;
385 1.1 uch txreg_t reg;
386 1.1 uch
387 1.1 uch reg = tx_conf_read(tc, TX39_SIBCTRL_REG);
388 1.1 uch ISSETPRINT_CTRL(reg, SIBIRQ);
389 1.1 uch ISSETPRINT_CTRL(reg, ENCNTTEST);
390 1.1 uch ISSETPRINT_CTRL(reg, ENDMATEST);
391 1.1 uch ISSETPRINT_CTRL(reg, SNDMONO);
392 1.1 uch ISSETPRINT_CTRL(reg, RMONOSNDIN);
393 1.1 uch ISSETPRINT_CTRL(reg, TEL16);
394 1.1 uch ISSETPRINT_CTRL(reg, SND16);
395 1.1 uch ISSETPRINT_CTRL(reg, SELTELSF1);
396 1.1 uch ISSETPRINT_CTRL(reg, SELSNDSF1);
397 1.1 uch ISSETPRINT_CTRL(reg, ENTEL);
398 1.1 uch ISSETPRINT_CTRL(reg, ENSND);
399 1.1 uch ISSETPRINT_CTRL(reg, SIBLOOP);
400 1.1 uch ISSETPRINT_CTRL(reg, ENSF1);
401 1.1 uch ISSETPRINT_CTRL(reg, ENSF0);
402 1.1 uch ISSETPRINT_CTRL(reg, ENSIB);
403 1.1 uch printf("\n");
404 1.1 uch printf("SCLKDIV %d\n", TX39_SIBCTRL_SCLKDIV(reg));
405 1.1 uch printf("TELFSDIV %d\n", TX39_SIBCTRL_TELFSDIV(reg));
406 1.1 uch printf("SNDFSDIV %d\n", TX39_SIBCTRL_SNDFSDIV(reg));
407 1.1 uch
408 1.1 uch reg = tx_conf_read(tc, TX39_SIBDMACTRL_REG);
409 1.1 uch ISSETPRINT_DMACTRL(reg, SNDBUFF1TIME);
410 1.1 uch ISSETPRINT_DMACTRL(reg, SNDDMALOOP);
411 1.1 uch ISSETPRINT_DMACTRL(reg, ENDMARXSND);
412 1.1 uch ISSETPRINT_DMACTRL(reg, ENDMATXSND);
413 1.1 uch ISSETPRINT_DMACTRL(reg, TELBUFF1TIME);
414 1.1 uch ISSETPRINT_DMACTRL(reg, TELDMALOOP);
415 1.1 uch ISSETPRINT_DMACTRL(reg, ENDMARXTEL);
416 1.1 uch ISSETPRINT_DMACTRL(reg, ENDMATXTEL);
417 1.1 uch printf("\n");
418 1.1 uch printf("SNDDMAPTR %d\n", TX39_SIBDMACTRL_TELDMAPTR(reg));
419 1.1 uch printf("TELDMAPTR %d\n", TX39_SIBDMACTRL_SNDDMAPTR(reg));
420 1.1 uch
421 1.1 uch }
422 1.4 uch #endif /* TX39SIBDEBUG */
423