tx39sib.c revision 1.4 1 1.4 uch /* $NetBSD: tx39sib.c,v 1.4 2000/03/03 19:54:36 uch Exp $ */
2 1.1 uch
3 1.1 uch /*
4 1.1 uch * Copyright (c) 2000, by UCHIYAMA Yasushi
5 1.1 uch * All rights reserved.
6 1.1 uch *
7 1.1 uch * Redistribution and use in source and binary forms, with or without
8 1.1 uch * modification, are permitted provided that the following conditions
9 1.1 uch * are met:
10 1.1 uch * 1. Redistributions of source code must retain the above copyright
11 1.1 uch * notice, this list of conditions and the following disclaimer.
12 1.1 uch * 2. The name of the developer may NOT be used to endorse or promote products
13 1.1 uch * derived from this software without specific prior written permission.
14 1.1 uch *
15 1.1 uch * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 1.1 uch * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 1.1 uch * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 1.1 uch * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 1.1 uch * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 1.1 uch * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 1.1 uch * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 1.1 uch * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 1.1 uch * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 1.1 uch * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 1.1 uch * SUCH DAMAGE.
26 1.1 uch *
27 1.1 uch */
28 1.1 uch
29 1.1 uch /*
30 1.1 uch * TX39 SIB (Serial Interface Bus) module.
31 1.1 uch */
32 1.2 uch #undef TX39SIBDEBUG
33 1.1 uch #include "opt_tx39_debug.h"
34 1.1 uch
35 1.1 uch #include <sys/param.h>
36 1.1 uch #include <sys/systm.h>
37 1.1 uch #include <sys/device.h>
38 1.1 uch
39 1.1 uch #include <machine/bus.h>
40 1.1 uch #include <machine/intr.h>
41 1.1 uch
42 1.1 uch #include <hpcmips/tx/tx39var.h>
43 1.1 uch #include <hpcmips/tx/tx39icureg.h>
44 1.1 uch #include <hpcmips/tx/tx39sibvar.h>
45 1.1 uch #include <hpcmips/tx/tx39sibreg.h>
46 1.1 uch
47 1.1 uch #include "locators.h"
48 1.1 uch
49 1.1 uch #ifdef TX39SIBDEBUG
50 1.4 uch int tx39sibdebug = 0;
51 1.4 uch #define DPRINTF(arg) if (tx39sibdebug) printf arg;
52 1.1 uch #else
53 1.1 uch #define DPRINTF(arg)
54 1.1 uch #endif
55 1.1 uch
56 1.1 uch int tx39sib_match __P((struct device*, struct cfdata*, void*));
57 1.1 uch void tx39sib_attach __P((struct device*, struct device*, void*));
58 1.1 uch int tx39sib_print __P((void*, const char*));
59 1.1 uch int tx39sib_search __P((struct device*, struct cfdata*, void*));
60 1.1 uch
61 1.2 uch #define TX39_CLK2X 18432000
62 1.2 uch const int sibsclk_divide_table[8] = {
63 1.2 uch 2, 3, 4, 5, 6, 8, 10, 12
64 1.2 uch };
65 1.2 uch
66 1.2 uch struct tx39sib_param {
67 1.2 uch /* SIB clock rate */
68 1.2 uch int sp_clock;
69 1.2 uch /*
70 1.2 uch * SIBMCLK = 18.432MHz = (CLK2X /4)
71 1.2 uch * SIBSCLK = SIBMCLK / sp_clock
72 1.2 uch * sp_clock start end divide module
73 1.2 uch * 0 7 8 2
74 1.2 uch * 1 6 8 3
75 1.2 uch * 2 6 9 4
76 1.2 uch * 3 5 9 5
77 1.2 uch * 4 5 10 6
78 1.2 uch * 5 4 11 8
79 1.2 uch * 6 3 12 10
80 1.2 uch * 7 2 13 12
81 1.2 uch */
82 1.2 uch /* sampling rate */
83 1.2 uch int sp_snd_rate; /* SNDFSDIV + 1 */
84 1.2 uch int sp_tel_rate; /* TELFSDIV + 1 */
85 1.2 uch /*
86 1.4 uch * Fs = (SIBSCLK * 2) / ((FSDIV + 1) * 64)
87 1.2 uch * FSDIV + 1 sampling rate
88 1.2 uch * 15 19.2k (1.6% error vs. CD-XA)
89 1.2 uch * 13 22.154k (0.47% error vs. CD-Audio)
90 1.2 uch * 22 7.85k (1.8% error vs. 8k)
91 1.2 uch */
92 1.2 uch /* data format 16/8bit */
93 1.2 uch int sp_sf0sndmode;
94 1.2 uch int sp_sf0telmode;
95 1.2 uch };
96 1.2 uch
97 1.4 uch struct tx39sib_param tx39sib_param_default_3912 = {
98 1.2 uch 0, /* SIBSCLK = 9.216MHz */
99 1.4 uch #if 0 /* setting sample */
100 1.4 uch 40, /* audio: 7.2kHz */
101 1.4 uch 26, /* audio: CD-Audio(/4) 11.077kHz*/
102 1.4 uch 6, /* audio: 48kHz */
103 1.4 uch #endif
104 1.4 uch 13, /* audio: CD-Audio(/2 = 22.050) 22.154kHz*/
105 1.4 uch 40, /* telecom: 7.2kHz */
106 1.4 uch TX39_SIBCTRL_SND16, /* Audio 16bit mono */
107 1.4 uch TX39_SIBCTRL_TEL16 /* Telecom 16bit mono */
108 1.4 uch };
109 1.4 uch
110 1.4 uch struct tx39sib_param tx39sib_param_default_3922 = {
111 1.4 uch 0, /* SIBSCLK = 9.216MHz */
112 1.4 uch 13, /* audio: CD-Audio(/4) 11.077kHz */
113 1.2 uch 40, /* telecom: 7.2kHz */
114 1.2 uch TX39_SIBCTRL_SND16, /* Audio 16bit mono */
115 1.2 uch TX39_SIBCTRL_TEL16 /* Telecom 16bit mono */
116 1.2 uch };
117 1.2 uch
118 1.1 uch struct tx39sib_softc {
119 1.1 uch struct device sc_dev;
120 1.1 uch tx_chipset_tag_t sc_tc;
121 1.1 uch
122 1.2 uch struct tx39sib_param sc_param;
123 1.1 uch int sc_attached;
124 1.1 uch };
125 1.1 uch
126 1.1 uch __inline int __txsibsf0_ready __P((tx_chipset_tag_t));
127 1.4 uch #ifdef TX39SIBDEBUG
128 1.1 uch void tx39sib_dump __P((struct tx39sib_softc*));
129 1.4 uch #endif
130 1.1 uch
131 1.1 uch struct cfattach tx39sib_ca = {
132 1.1 uch sizeof(struct tx39sib_softc), tx39sib_match, tx39sib_attach
133 1.1 uch };
134 1.1 uch
135 1.1 uch int
136 1.1 uch tx39sib_match(parent, cf, aux)
137 1.1 uch struct device *parent;
138 1.1 uch struct cfdata *cf;
139 1.1 uch void *aux;
140 1.1 uch {
141 1.1 uch return 1;
142 1.1 uch }
143 1.1 uch
144 1.1 uch void
145 1.1 uch tx39sib_attach(parent, self, aux)
146 1.1 uch struct device *parent;
147 1.1 uch struct device *self;
148 1.1 uch void *aux;
149 1.1 uch {
150 1.1 uch struct txsim_attach_args *ta = aux;
151 1.1 uch struct tx39sib_softc *sc = (void*)self;
152 1.1 uch tx_chipset_tag_t tc;
153 1.2 uch
154 1.1 uch sc->sc_tc = tc = ta->ta_tc;
155 1.1 uch
156 1.2 uch /* set default param */
157 1.4 uch #ifdef TX391X
158 1.4 uch sc->sc_param = tx39sib_param_default_3912;
159 1.4 uch #endif /* TX391X */
160 1.4 uch #ifdef TX392X
161 1.4 uch sc->sc_param = tx39sib_param_default_3922;
162 1.4 uch #endif /* TX392X */
163 1.4 uch
164 1.2 uch #define MHZ(a) ((a) / 1000000), (((a) % 1000000) / 1000)
165 1.2 uch printf(": %d.%03d MHz", MHZ(tx39sib_clock(self)));
166 1.2 uch
167 1.1 uch printf("\n");
168 1.1 uch #ifdef TX39SIBDEBUG
169 1.4 uch if (tx39sibdebug)
170 1.4 uch tx39sib_dump(sc);
171 1.1 uch #endif
172 1.2 uch /* enable subframe0 */
173 1.2 uch tx39sib_enable1(self);
174 1.2 uch /* enable SIB */
175 1.2 uch tx39sib_enable2(self);
176 1.2 uch
177 1.2 uch #ifdef TX39SIBDEBUG
178 1.4 uch if (tx39sibdebug)
179 1.4 uch tx39sib_dump(sc);
180 1.2 uch #endif
181 1.2 uch
182 1.2 uch config_search(tx39sib_search, self, tx39sib_print);
183 1.2 uch }
184 1.2 uch
185 1.2 uch void
186 1.2 uch tx39sib_enable1(dev)
187 1.2 uch struct device *dev;
188 1.2 uch {
189 1.2 uch struct tx39sib_softc *sc = (void*)dev;
190 1.2 uch struct tx39sib_param *param = &sc->sc_param;
191 1.2 uch tx_chipset_tag_t tc = sc->sc_tc;
192 1.2 uch
193 1.2 uch txreg_t reg;
194 1.2 uch
195 1.2 uch /* disable SIB */
196 1.2 uch tx39sib_disable(dev);
197 1.2 uch
198 1.2 uch /* setup */
199 1.2 uch reg = 0;
200 1.2 uch /* SIB clock rate */
201 1.2 uch reg = TX39_SIBCTRL_SCLKDIV_SET(reg, param->sp_clock);
202 1.2 uch /* sampling rate (sound) */
203 1.2 uch reg = TX39_SIBCTRL_SNDFSDIV_SET(reg, param->sp_snd_rate - 1);
204 1.2 uch /* sampling rate (telecom) */
205 1.2 uch reg = TX39_SIBCTRL_TELFSDIV_SET(reg, param->sp_tel_rate - 1);
206 1.2 uch /* data format (8/16bit) */
207 1.2 uch reg |= param->sp_sf0sndmode;
208 1.2 uch reg |= param->sp_sf0telmode;
209 1.2 uch tx_conf_write(tc, TX39_SIBCTRL_REG, reg);
210 1.2 uch
211 1.2 uch /* DMA */
212 1.2 uch reg = tx_conf_read(tc, TX39_SIBDMACTRL_REG);
213 1.2 uch reg &= ~(TX39_SIBDMACTRL_ENDMARXSND |
214 1.2 uch TX39_SIBDMACTRL_ENDMATXSND |
215 1.2 uch TX39_SIBDMACTRL_ENDMARXTEL |
216 1.2 uch TX39_SIBDMACTRL_ENDMATXTEL);
217 1.2 uch tx_conf_write(tc, TX39_SIBDMACTRL_REG, reg);
218 1.2 uch
219 1.1 uch /*
220 1.2 uch * Enable subframe0 (BETTY)
221 1.1 uch */
222 1.1 uch reg = tx_conf_read(tc, TX39_SIBCTRL_REG);
223 1.1 uch reg |= TX39_SIBCTRL_ENSF0;
224 1.1 uch tx_conf_write(tc, TX39_SIBCTRL_REG, reg);
225 1.2 uch }
226 1.2 uch
227 1.2 uch void
228 1.2 uch tx39sib_enable2(dev)
229 1.2 uch struct device *dev;
230 1.2 uch {
231 1.2 uch struct tx39sib_softc *sc = (void*)dev;
232 1.2 uch tx_chipset_tag_t tc = sc->sc_tc;
233 1.2 uch txreg_t reg;
234 1.2 uch
235 1.2 uch reg = tx_conf_read(tc, TX39_SIBCTRL_REG);
236 1.2 uch reg |= TX39_SIBCTRL_ENSIB;
237 1.2 uch tx_conf_write(tc, TX39_SIBCTRL_REG, reg);
238 1.2 uch }
239 1.1 uch
240 1.2 uch void
241 1.2 uch tx39sib_disable(dev)
242 1.2 uch struct device *dev;
243 1.2 uch {
244 1.2 uch struct tx39sib_softc *sc = (void*)dev;
245 1.2 uch tx_chipset_tag_t tc = sc->sc_tc;
246 1.2 uch txreg_t reg;
247 1.2 uch /* disable codec side */
248 1.2 uch /* notyet */
249 1.2 uch
250 1.2 uch /* disable TX39 side */
251 1.1 uch reg = tx_conf_read(tc, TX39_SIBCTRL_REG);
252 1.2 uch reg &= ~(TX39_SIBCTRL_ENTEL | TX39_SIBCTRL_ENSND);
253 1.1 uch tx_conf_write(tc, TX39_SIBCTRL_REG, reg);
254 1.1 uch
255 1.2 uch /*
256 1.2 uch * Disable subframe0/1 (BETTY/external codec)
257 1.1 uch */
258 1.1 uch reg = tx_conf_read(tc, TX39_SIBCTRL_REG);
259 1.2 uch reg &= ~TX39_SIBCTRL_ENSF0;
260 1.2 uch reg &= ~(TX39_SIBCTRL_ENSF1 | TX39_SIBCTRL_SELTELSF1 |
261 1.2 uch TX39_SIBCTRL_SELSNDSF1);
262 1.1 uch tx_conf_write(tc, TX39_SIBCTRL_REG, reg);
263 1.1 uch
264 1.2 uch /* disable TX39SIB module */
265 1.2 uch reg &= ~TX39_SIBCTRL_ENSIB;
266 1.2 uch tx_conf_write(tc, TX39_SIBCTRL_REG, reg);
267 1.1 uch }
268 1.1 uch
269 1.2 uch int
270 1.2 uch tx39sib_clock(dev)
271 1.2 uch struct device *dev;
272 1.2 uch {
273 1.2 uch struct tx39sib_softc *sc = (void*)dev;
274 1.2 uch
275 1.2 uch return TX39_CLK2X / sibsclk_divide_table[sc->sc_param.sp_clock];
276 1.2 uch }
277 1.1 uch
278 1.1 uch int
279 1.1 uch tx39sib_search(parent, cf, aux)
280 1.1 uch struct device *parent;
281 1.1 uch struct cfdata *cf;
282 1.1 uch void *aux;
283 1.1 uch {
284 1.1 uch struct tx39sib_softc *sc = (void*)parent;
285 1.1 uch struct txsib_attach_args sa;
286 1.1 uch
287 1.1 uch sa.sa_tc = sc->sc_tc;
288 1.1 uch sa.sa_slot = cf->cf_loc[TXSIBIFCF_SLOT];
289 1.2 uch sa.sa_snd_rate = sc->sc_param.sp_snd_rate;
290 1.2 uch sa.sa_tel_rate = sc->sc_param.sp_tel_rate;
291 1.1 uch
292 1.1 uch if (sa.sa_slot == TXSIBIFCF_SLOT_DEFAULT) {
293 1.1 uch printf("tx39sib_search: wildcarded slot, skipping\n");
294 1.1 uch return 0;
295 1.1 uch }
296 1.1 uch
297 1.1 uch if (!(sc->sc_attached & (1 << sa.sa_slot)) &&/* not attached slot */
298 1.1 uch (*cf->cf_attach->ca_match)(parent, cf, &sa)) {
299 1.1 uch config_attach(parent, cf, &sa, tx39sib_print);
300 1.1 uch sc->sc_attached |= (1 << sa.sa_slot);
301 1.1 uch }
302 1.1 uch
303 1.1 uch return 0;
304 1.1 uch }
305 1.1 uch
306 1.1 uch int
307 1.1 uch tx39sib_print(aux, pnp)
308 1.1 uch void *aux;
309 1.1 uch const char *pnp;
310 1.1 uch {
311 1.1 uch struct txsib_attach_args *sa = aux;
312 1.1 uch
313 1.1 uch printf(" slot %d", sa->sa_slot);
314 1.1 uch
315 1.1 uch return QUIET;
316 1.1 uch }
317 1.1 uch
318 1.1 uch /*
319 1.1 uch * sync access method. don't use runtime.
320 1.1 uch */
321 1.1 uch
322 1.1 uch __inline int
323 1.1 uch __txsibsf0_ready(tc)
324 1.1 uch tx_chipset_tag_t tc;
325 1.1 uch {
326 1.1 uch int i;
327 1.1 uch
328 1.1 uch tx_conf_write(tc, TX39_INTRSTATUS1_REG, TX39_INTRSTATUS1_SIBSF0INT);
329 1.1 uch for (i = 0; (!(tx_conf_read(tc, TX39_INTRSTATUS1_REG) &
330 1.4 uch TX39_INTRSTATUS1_SIBSF0INT)) && i < 200; i++)
331 1.1 uch ;
332 1.4 uch if (i >= 200) {
333 1.1 uch printf("sf0 busy\n");
334 1.1 uch return 0;
335 1.4 uch } else if (i > 100) {
336 1.1 uch printf("sf0 busy loop:%d\n", i);
337 1.1 uch return 0;
338 1.1 uch }
339 1.1 uch
340 1.1 uch return 1;
341 1.1 uch }
342 1.1 uch
343 1.1 uch void
344 1.1 uch txsibsf0_reg_write(tc, addr, val)
345 1.1 uch tx_chipset_tag_t tc;
346 1.1 uch int addr;
347 1.1 uch u_int16_t val;
348 1.1 uch {
349 1.1 uch txreg_t reg;
350 1.1 uch
351 1.1 uch reg = txsibsf0_read(tc, addr);
352 1.1 uch reg |= TX39_SIBSF0_WRITE;
353 1.1 uch TX39_SIBSF0_REGDATA_CLR(reg);
354 1.1 uch reg = TX39_SIBSF0_REGDATA_SET(reg, val);
355 1.1 uch
356 1.1 uch __txsibsf0_ready(tc);
357 1.1 uch tx_conf_write(tc, TX39_SIBSF0CTRL_REG, reg);
358 1.1 uch }
359 1.1 uch
360 1.1 uch u_int16_t
361 1.1 uch txsibsf0_reg_read(tc, addr)
362 1.1 uch tx_chipset_tag_t tc;
363 1.1 uch int addr;
364 1.1 uch {
365 1.1 uch return TX39_SIBSF0_REGDATA(txsibsf0_read(tc, addr));
366 1.1 uch }
367 1.1 uch
368 1.1 uch u_int32_t
369 1.1 uch txsibsf0_read(tc, addr)
370 1.1 uch tx_chipset_tag_t tc;
371 1.1 uch int addr;
372 1.1 uch {
373 1.1 uch txreg_t reg;
374 1.1 uch int retry = 3;
375 1.1 uch
376 1.1 uch do {
377 1.1 uch reg = TX39_SIBSF0_REGADDR_SET(0, addr);
378 1.1 uch __txsibsf0_ready(tc);
379 1.1 uch tx_conf_write(tc, TX39_SIBSF0CTRL_REG, reg);
380 1.1 uch
381 1.1 uch __txsibsf0_ready(tc);
382 1.1 uch reg = tx_conf_read(tc, TX39_SIBSF0STAT_REG);
383 1.1 uch
384 1.1 uch } while ((TX39_SIBSF0_REGADDR(reg) != addr) && --retry > 0);
385 1.1 uch
386 1.1 uch if (retry <= 0)
387 1.1 uch printf("txsibsf0_read: command failed\n");
388 1.1 uch
389 1.1 uch return reg;
390 1.1 uch }
391 1.1 uch
392 1.4 uch #ifdef TX39SIBDEBUG
393 1.1 uch #define ISSETPRINT_CTRL(r, m) \
394 1.1 uch __is_set_print(r, TX39_SIBCTRL_##m, #m)
395 1.1 uch #define ISSETPRINT_DMACTRL(r, m) \
396 1.1 uch __is_set_print(r, TX39_SIBDMACTRL_##m, #m)
397 1.1 uch
398 1.1 uch void
399 1.1 uch tx39sib_dump(sc)
400 1.1 uch struct tx39sib_softc *sc;
401 1.1 uch {
402 1.1 uch tx_chipset_tag_t tc = sc->sc_tc;
403 1.1 uch txreg_t reg;
404 1.1 uch
405 1.1 uch reg = tx_conf_read(tc, TX39_SIBCTRL_REG);
406 1.1 uch ISSETPRINT_CTRL(reg, SIBIRQ);
407 1.1 uch ISSETPRINT_CTRL(reg, ENCNTTEST);
408 1.1 uch ISSETPRINT_CTRL(reg, ENDMATEST);
409 1.1 uch ISSETPRINT_CTRL(reg, SNDMONO);
410 1.1 uch ISSETPRINT_CTRL(reg, RMONOSNDIN);
411 1.1 uch ISSETPRINT_CTRL(reg, TEL16);
412 1.1 uch ISSETPRINT_CTRL(reg, SND16);
413 1.1 uch ISSETPRINT_CTRL(reg, SELTELSF1);
414 1.1 uch ISSETPRINT_CTRL(reg, SELSNDSF1);
415 1.1 uch ISSETPRINT_CTRL(reg, ENTEL);
416 1.1 uch ISSETPRINT_CTRL(reg, ENSND);
417 1.1 uch ISSETPRINT_CTRL(reg, SIBLOOP);
418 1.1 uch ISSETPRINT_CTRL(reg, ENSF1);
419 1.1 uch ISSETPRINT_CTRL(reg, ENSF0);
420 1.1 uch ISSETPRINT_CTRL(reg, ENSIB);
421 1.1 uch printf("\n");
422 1.1 uch printf("SCLKDIV %d\n", TX39_SIBCTRL_SCLKDIV(reg));
423 1.1 uch printf("TELFSDIV %d\n", TX39_SIBCTRL_TELFSDIV(reg));
424 1.1 uch printf("SNDFSDIV %d\n", TX39_SIBCTRL_SNDFSDIV(reg));
425 1.1 uch
426 1.1 uch reg = tx_conf_read(tc, TX39_SIBDMACTRL_REG);
427 1.1 uch ISSETPRINT_DMACTRL(reg, SNDBUFF1TIME);
428 1.1 uch ISSETPRINT_DMACTRL(reg, SNDDMALOOP);
429 1.1 uch ISSETPRINT_DMACTRL(reg, ENDMARXSND);
430 1.1 uch ISSETPRINT_DMACTRL(reg, ENDMATXSND);
431 1.1 uch ISSETPRINT_DMACTRL(reg, TELBUFF1TIME);
432 1.1 uch ISSETPRINT_DMACTRL(reg, TELDMALOOP);
433 1.1 uch ISSETPRINT_DMACTRL(reg, ENDMARXTEL);
434 1.1 uch ISSETPRINT_DMACTRL(reg, ENDMATXTEL);
435 1.1 uch printf("\n");
436 1.1 uch printf("SNDDMAPTR %d\n", TX39_SIBDMACTRL_TELDMAPTR(reg));
437 1.1 uch printf("TELDMAPTR %d\n", TX39_SIBDMACTRL_SNDDMAPTR(reg));
438 1.1 uch
439 1.1 uch }
440 1.4 uch #endif /* TX39SIBDEBUG */
441