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tx39sib.c revision 1.7.4.1
      1  1.7.4.1  nathanw /*	$NetBSD: tx39sib.c,v 1.7.4.1 2001/06/21 19:24:33 nathanw Exp $ */
      2      1.1      uch 
      3  1.7.4.1  nathanw /*-
      4  1.7.4.1  nathanw  * Copyright (c) 2000 The NetBSD Foundation, Inc.
      5      1.1      uch  * All rights reserved.
      6      1.1      uch  *
      7  1.7.4.1  nathanw  * This code is derived from software contributed to The NetBSD Foundation
      8  1.7.4.1  nathanw  * by UCHIYAMA Yasushi.
      9  1.7.4.1  nathanw  *
     10      1.1      uch  * Redistribution and use in source and binary forms, with or without
     11      1.1      uch  * modification, are permitted provided that the following conditions
     12      1.1      uch  * are met:
     13      1.1      uch  * 1. Redistributions of source code must retain the above copyright
     14      1.1      uch  *    notice, this list of conditions and the following disclaimer.
     15  1.7.4.1  nathanw  * 2. Redistributions in binary form must reproduce the above copyright
     16  1.7.4.1  nathanw  *    notice, this list of conditions and the following disclaimer in the
     17  1.7.4.1  nathanw  *    documentation and/or other materials provided with the distribution.
     18  1.7.4.1  nathanw  * 3. All advertising materials mentioning features or use of this software
     19  1.7.4.1  nathanw  *    must display the following acknowledgement:
     20  1.7.4.1  nathanw  *        This product includes software developed by the NetBSD
     21  1.7.4.1  nathanw  *        Foundation, Inc. and its contributors.
     22  1.7.4.1  nathanw  * 4. Neither the name of The NetBSD Foundation nor the names of its
     23  1.7.4.1  nathanw  *    contributors may be used to endorse or promote products derived
     24  1.7.4.1  nathanw  *    from this software without specific prior written permission.
     25      1.1      uch  *
     26  1.7.4.1  nathanw  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     27  1.7.4.1  nathanw  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     28  1.7.4.1  nathanw  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     29  1.7.4.1  nathanw  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     30  1.7.4.1  nathanw  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     31  1.7.4.1  nathanw  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     32  1.7.4.1  nathanw  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     33  1.7.4.1  nathanw  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     34  1.7.4.1  nathanw  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     35  1.7.4.1  nathanw  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     36  1.7.4.1  nathanw  * POSSIBILITY OF SUCH DAMAGE.
     37      1.1      uch  */
     38      1.1      uch 
     39      1.1      uch /*
     40      1.1      uch  * TX39 SIB (Serial Interface Bus) module.
     41      1.1      uch  */
     42      1.2      uch #undef TX39SIBDEBUG
     43      1.1      uch #include "opt_tx39_debug.h"
     44      1.1      uch 
     45      1.1      uch #include <sys/param.h>
     46      1.1      uch #include <sys/systm.h>
     47      1.1      uch #include <sys/device.h>
     48      1.1      uch 
     49      1.1      uch #include <machine/bus.h>
     50      1.1      uch #include <machine/intr.h>
     51      1.1      uch 
     52      1.1      uch #include <hpcmips/tx/tx39var.h>
     53      1.1      uch #include <hpcmips/tx/tx39icureg.h>
     54      1.1      uch #include <hpcmips/tx/tx39sibvar.h>
     55      1.1      uch #include <hpcmips/tx/tx39sibreg.h>
     56      1.1      uch 
     57      1.1      uch #include "locators.h"
     58      1.1      uch 
     59      1.1      uch #ifdef TX39SIBDEBUG
     60      1.4      uch int	tx39sibdebug = 0;
     61      1.4      uch #define	DPRINTF(arg) if (tx39sibdebug) printf arg;
     62      1.1      uch #else
     63      1.1      uch #define	DPRINTF(arg)
     64      1.1      uch #endif
     65      1.1      uch 
     66  1.7.4.1  nathanw int	tx39sib_match(struct device *, struct cfdata *, void *);
     67  1.7.4.1  nathanw void	tx39sib_attach(struct device *, struct device *, void *);
     68  1.7.4.1  nathanw int	tx39sib_print(void *, const char *);
     69  1.7.4.1  nathanw int	tx39sib_search(struct device *, struct cfdata *, void *);
     70      1.1      uch 
     71      1.2      uch #define TX39_CLK2X	18432000
     72      1.2      uch const int sibsclk_divide_table[8] = {
     73      1.2      uch 	2, 3, 4, 5, 6, 8, 10, 12
     74      1.2      uch };
     75      1.2      uch 
     76      1.2      uch struct tx39sib_param {
     77      1.2      uch 	/* SIB clock rate */
     78      1.2      uch 	int sp_clock;
     79      1.2      uch /*
     80      1.2      uch  *	SIBMCLK = 18.432MHz = (CLK2X /4)
     81      1.2      uch  *	SIBSCLK = SIBMCLK / sp_clock
     82      1.2      uch  *	sp_clock	start	end	divide module
     83      1.2      uch  *	0		7	8	2
     84      1.2      uch  *	1		6	8	3
     85      1.2      uch  *	2		6	9	4
     86      1.2      uch  *	3		5	9	5
     87      1.2      uch  *	4		5	10	6
     88      1.2      uch  *	5		4	11	8
     89      1.2      uch  *	6		3	12	10
     90      1.2      uch  *	7		2	13	12
     91      1.2      uch  */
     92      1.2      uch 	/* sampling rate */
     93      1.2      uch 	int sp_snd_rate; /* SNDFSDIV + 1 */
     94      1.2      uch 	int sp_tel_rate; /* TELFSDIV + 1 */
     95      1.2      uch /*
     96      1.4      uch  *	Fs = (SIBSCLK * 2) / ((FSDIV + 1) * 64)
     97      1.2      uch  *	FSDIV + 1	sampling rate
     98      1.2      uch  *	15		19.2k		(1.6% error vs. CD-XA)
     99      1.2      uch  *	13		22.154k		(0.47% error vs. CD-Audio)
    100      1.2      uch  *	22		7.85k		(1.8% error vs. 8k)
    101      1.2      uch  */
    102      1.2      uch 	/* data format 16/8bit */
    103      1.2      uch 	int sp_sf0sndmode;
    104      1.2      uch 	int sp_sf0telmode;
    105      1.2      uch };
    106      1.2      uch 
    107      1.4      uch struct tx39sib_param tx39sib_param_default_3912 = {
    108      1.5      uch 	0,			/* SIBSCLK = 9.216MHz (div2) */
    109      1.4      uch #if 0 /* setting sample */
    110      1.4      uch 	40,			/* audio: 7.2kHz */
    111      1.4      uch 	26,			/* audio: CD-Audio(/4) 11.077kHz*/
    112      1.4      uch 	6,			/* audio: 48kHz */
    113      1.4      uch #endif
    114      1.4      uch 	13,			/* audio: CD-Audio(/2 = 22.050) 22.154kHz*/
    115      1.4      uch 	40,			/* telecom: 7.2kHz */
    116      1.4      uch 	TX39_SIBCTRL_SND16,	/* Audio 16bit mono */
    117      1.4      uch 	TX39_SIBCTRL_TEL16	/* Telecom 16bit mono */
    118      1.4      uch };
    119      1.4      uch 
    120      1.4      uch struct tx39sib_param tx39sib_param_default_3922 = {
    121      1.5      uch 	7,			/* SIBSCLK = 9.216MHz (div1) */
    122      1.5      uch 	13,			/* audio: CD-Audio(/2 = 22.050) 22.154kHz*/
    123      1.2      uch 	40,			/* telecom: 7.2kHz */
    124      1.2      uch 	TX39_SIBCTRL_SND16,	/* Audio 16bit mono */
    125      1.2      uch 	TX39_SIBCTRL_TEL16	/* Telecom 16bit mono */
    126      1.2      uch };
    127      1.2      uch 
    128      1.1      uch struct tx39sib_softc {
    129      1.1      uch 	struct	device sc_dev;
    130      1.1      uch 	tx_chipset_tag_t sc_tc;
    131      1.1      uch 
    132      1.2      uch 	struct tx39sib_param sc_param;
    133      1.1      uch 	int sc_attached;
    134      1.1      uch };
    135      1.1      uch 
    136  1.7.4.1  nathanw __inline int	__txsibsf0_ready(tx_chipset_tag_t);
    137      1.4      uch #ifdef TX39SIBDEBUG
    138  1.7.4.1  nathanw void	tx39sib_dump(struct tx39sib_softc *);
    139      1.4      uch #endif
    140      1.1      uch 
    141      1.1      uch struct cfattach tx39sib_ca = {
    142      1.1      uch 	sizeof(struct tx39sib_softc), tx39sib_match, tx39sib_attach
    143      1.1      uch };
    144      1.1      uch 
    145      1.1      uch int
    146  1.7.4.1  nathanw tx39sib_match(struct device *parent, struct cfdata *cf, void *aux)
    147      1.1      uch {
    148  1.7.4.1  nathanw 	return (ATTACH_FIRST);
    149      1.1      uch }
    150      1.1      uch 
    151      1.1      uch void
    152  1.7.4.1  nathanw tx39sib_attach(struct device *parent, struct device *self, void *aux)
    153      1.1      uch {
    154      1.1      uch 	struct txsim_attach_args *ta = aux;
    155      1.1      uch 	struct tx39sib_softc *sc = (void*)self;
    156      1.1      uch 	tx_chipset_tag_t tc;
    157      1.2      uch 
    158      1.1      uch 	sc->sc_tc = tc = ta->ta_tc;
    159      1.1      uch 
    160      1.2      uch 	/* set default param */
    161      1.4      uch #ifdef TX391X
    162      1.4      uch 	sc->sc_param = tx39sib_param_default_3912;
    163      1.4      uch #endif /* TX391X */
    164      1.4      uch #ifdef TX392X
    165      1.4      uch 	sc->sc_param = tx39sib_param_default_3922;
    166      1.4      uch #endif /* TX392X */
    167      1.4      uch 
    168      1.2      uch #define MHZ(a) ((a) / 1000000), (((a) % 1000000) / 1000)
    169      1.2      uch 	printf(": %d.%03d MHz", MHZ(tx39sib_clock(self)));
    170      1.2      uch 
    171      1.1      uch 	printf("\n");
    172      1.1      uch #ifdef TX39SIBDEBUG
    173      1.4      uch 	if (tx39sibdebug)
    174      1.4      uch 		tx39sib_dump(sc);
    175      1.1      uch #endif
    176      1.2      uch 	/* enable subframe0 */
    177      1.2      uch 	tx39sib_enable1(self);
    178      1.2      uch 	/* enable SIB */
    179      1.2      uch 	tx39sib_enable2(self);
    180      1.2      uch 
    181      1.2      uch #ifdef TX39SIBDEBUG
    182      1.4      uch 	if (tx39sibdebug)
    183      1.4      uch 		tx39sib_dump(sc);
    184      1.2      uch #endif
    185      1.2      uch 
    186      1.2      uch 	config_search(tx39sib_search, self, tx39sib_print);
    187      1.2      uch }
    188      1.2      uch 
    189      1.2      uch void
    190  1.7.4.1  nathanw tx39sib_enable1(struct device *dev)
    191      1.2      uch {
    192      1.2      uch 	struct tx39sib_softc *sc = (void*)dev;
    193      1.2      uch 	struct tx39sib_param *param = &sc->sc_param;
    194      1.2      uch 	tx_chipset_tag_t tc = sc->sc_tc;
    195      1.2      uch 
    196      1.2      uch 	txreg_t reg;
    197      1.2      uch 
    198      1.2      uch 	/* disable SIB */
    199      1.2      uch 	tx39sib_disable(dev);
    200      1.2      uch 
    201      1.2      uch 	/* setup */
    202      1.2      uch 	reg = 0;
    203      1.2      uch 	/*  SIB clock rate */
    204      1.2      uch 	reg = TX39_SIBCTRL_SCLKDIV_SET(reg, param->sp_clock);
    205      1.2      uch 	/*  sampling rate (sound) */
    206      1.2      uch 	reg = TX39_SIBCTRL_SNDFSDIV_SET(reg, param->sp_snd_rate - 1);
    207      1.2      uch 	/*  sampling rate (telecom) */
    208      1.2      uch 	reg = TX39_SIBCTRL_TELFSDIV_SET(reg, param->sp_tel_rate - 1);
    209      1.2      uch 	/*  data format (8/16bit) */
    210      1.2      uch 	reg |= param->sp_sf0sndmode;
    211      1.2      uch 	reg |= param->sp_sf0telmode;
    212      1.2      uch 	tx_conf_write(tc, TX39_SIBCTRL_REG, reg);
    213      1.2      uch 
    214      1.2      uch 	/* DMA */
    215      1.2      uch 	reg = tx_conf_read(tc, TX39_SIBDMACTRL_REG);
    216      1.2      uch 	reg &= ~(TX39_SIBDMACTRL_ENDMARXSND |
    217  1.7.4.1  nathanw 	    TX39_SIBDMACTRL_ENDMATXSND |
    218  1.7.4.1  nathanw 	    TX39_SIBDMACTRL_ENDMARXTEL |
    219  1.7.4.1  nathanw 	    TX39_SIBDMACTRL_ENDMATXTEL);
    220      1.2      uch 	tx_conf_write(tc, TX39_SIBDMACTRL_REG, reg);
    221      1.2      uch 
    222      1.1      uch 	/*
    223      1.2      uch 	 * Enable subframe0 (BETTY)
    224      1.1      uch 	 */
    225      1.1      uch 	reg = tx_conf_read(tc, TX39_SIBCTRL_REG);
    226      1.1      uch 	reg |= TX39_SIBCTRL_ENSF0;
    227      1.1      uch 	tx_conf_write(tc, TX39_SIBCTRL_REG, reg);
    228      1.2      uch }
    229      1.2      uch 
    230      1.2      uch void
    231  1.7.4.1  nathanw tx39sib_enable2(struct device *dev)
    232      1.2      uch {
    233      1.2      uch 	struct tx39sib_softc *sc = (void*)dev;
    234      1.2      uch 	tx_chipset_tag_t tc = sc->sc_tc;
    235      1.2      uch 	txreg_t reg;
    236      1.2      uch 
    237      1.2      uch 	reg = tx_conf_read(tc, TX39_SIBCTRL_REG);
    238      1.2      uch 	reg |= TX39_SIBCTRL_ENSIB;
    239      1.2      uch 	tx_conf_write(tc, TX39_SIBCTRL_REG, reg);
    240      1.2      uch }
    241      1.1      uch 
    242      1.2      uch void
    243  1.7.4.1  nathanw tx39sib_disable(struct device *dev)
    244      1.2      uch {
    245      1.2      uch 	struct tx39sib_softc *sc = (void*)dev;
    246      1.2      uch 	tx_chipset_tag_t tc = sc->sc_tc;
    247      1.2      uch 	txreg_t reg;
    248      1.2      uch 	/* disable codec side */
    249      1.2      uch 	/* notyet */
    250      1.2      uch 
    251      1.2      uch 	/* disable TX39 side */
    252      1.1      uch 	reg = tx_conf_read(tc, TX39_SIBCTRL_REG);
    253      1.2      uch 	reg &= ~(TX39_SIBCTRL_ENTEL | TX39_SIBCTRL_ENSND);
    254      1.1      uch 	tx_conf_write(tc, TX39_SIBCTRL_REG, reg);
    255      1.1      uch 
    256      1.2      uch 	/*
    257      1.2      uch 	 * Disable subframe0/1 (BETTY/external codec)
    258      1.1      uch 	 */
    259      1.1      uch 	reg = tx_conf_read(tc, TX39_SIBCTRL_REG);
    260      1.2      uch 	reg &= ~TX39_SIBCTRL_ENSF0;
    261      1.2      uch 	reg &= ~(TX39_SIBCTRL_ENSF1 | TX39_SIBCTRL_SELTELSF1 |
    262  1.7.4.1  nathanw 	    TX39_SIBCTRL_SELSNDSF1);
    263      1.1      uch 	tx_conf_write(tc, TX39_SIBCTRL_REG, reg);
    264      1.1      uch 
    265      1.2      uch 	/* disable TX39SIB module */
    266      1.2      uch 	reg &= ~TX39_SIBCTRL_ENSIB;
    267      1.2      uch 	tx_conf_write(tc, TX39_SIBCTRL_REG, reg);
    268      1.1      uch }
    269      1.1      uch 
    270      1.2      uch int
    271  1.7.4.1  nathanw tx39sib_clock(struct device *dev)
    272      1.2      uch {
    273      1.2      uch 	struct tx39sib_softc *sc = (void*)dev;
    274      1.2      uch 
    275  1.7.4.1  nathanw 	return (TX39_CLK2X / sibsclk_divide_table[sc->sc_param.sp_clock]);
    276      1.2      uch }
    277      1.1      uch 
    278      1.1      uch int
    279  1.7.4.1  nathanw tx39sib_search(struct device *parent, struct cfdata *cf, void *aux)
    280      1.1      uch {
    281      1.1      uch 	struct tx39sib_softc *sc = (void*)parent;
    282      1.1      uch 	struct txsib_attach_args sa;
    283      1.1      uch 
    284      1.1      uch 	sa.sa_tc	= sc->sc_tc;
    285      1.1      uch 	sa.sa_slot	= cf->cf_loc[TXSIBIFCF_SLOT];
    286      1.2      uch 	sa.sa_snd_rate	= sc->sc_param.sp_snd_rate;
    287      1.2      uch 	sa.sa_tel_rate	= sc->sc_param.sp_tel_rate;
    288      1.1      uch 
    289      1.1      uch 	if (sa.sa_slot == TXSIBIFCF_SLOT_DEFAULT) {
    290      1.1      uch 		printf("tx39sib_search: wildcarded slot, skipping\n");
    291  1.7.4.1  nathanw 		return (0);
    292      1.1      uch 	}
    293      1.1      uch 
    294      1.1      uch 	if (!(sc->sc_attached & (1 << sa.sa_slot)) &&/* not attached slot */
    295      1.1      uch 	    (*cf->cf_attach->ca_match)(parent, cf, &sa)) {
    296      1.1      uch 		config_attach(parent, cf, &sa, tx39sib_print);
    297      1.1      uch 		sc->sc_attached |= (1 << sa.sa_slot);
    298      1.1      uch 	}
    299      1.1      uch 
    300  1.7.4.1  nathanw 	return (0);
    301      1.1      uch }
    302      1.1      uch 
    303      1.1      uch int
    304  1.7.4.1  nathanw tx39sib_print(void *aux, const char *pnp)
    305      1.1      uch {
    306      1.1      uch 	struct txsib_attach_args *sa = aux;
    307      1.1      uch 
    308      1.1      uch 	printf(" slot %d", sa->sa_slot);
    309      1.1      uch 
    310  1.7.4.1  nathanw 	return (QUIET);
    311      1.1      uch }
    312      1.1      uch 
    313      1.1      uch /*
    314      1.1      uch  * sync access method. don't use runtime.
    315      1.1      uch  */
    316      1.1      uch 
    317  1.7.4.1  nathanw __inline__ int
    318  1.7.4.1  nathanw __txsibsf0_ready(tx_chipset_tag_t tc)
    319      1.1      uch {
    320      1.1      uch 	int i;
    321      1.1      uch 
    322      1.1      uch 	tx_conf_write(tc, TX39_INTRSTATUS1_REG, TX39_INTRSTATUS1_SIBSF0INT);
    323      1.1      uch 	for (i = 0; (!(tx_conf_read(tc, TX39_INTRSTATUS1_REG) &
    324  1.7.4.1  nathanw 	    TX39_INTRSTATUS1_SIBSF0INT)) && i < 1000; i++) {
    325      1.6      uch 		if (i > 100 && !(i % 100)) {
    326      1.6      uch 			printf("sf0 busy loop: retry count %d\n", i);
    327      1.6      uch 		}
    328      1.6      uch 	}
    329      1.6      uch 
    330      1.6      uch 	if (i >= 1000) {
    331      1.1      uch 		printf("sf0 busy\n");
    332  1.7.4.1  nathanw 		return (0);
    333      1.1      uch 	}
    334      1.1      uch 
    335  1.7.4.1  nathanw 	return (1);
    336      1.1      uch }
    337      1.1      uch 
    338      1.1      uch void
    339  1.7.4.1  nathanw txsibsf0_reg_write(tx_chipset_tag_t tc, int addr, u_int16_t val)
    340      1.1      uch {
    341      1.1      uch 	txreg_t reg;
    342      1.1      uch 
    343      1.1      uch 	reg = txsibsf0_read(tc, addr);
    344      1.1      uch 	reg |= TX39_SIBSF0_WRITE;
    345      1.1      uch 	TX39_SIBSF0_REGDATA_CLR(reg);
    346      1.1      uch 	reg = TX39_SIBSF0_REGDATA_SET(reg, val);
    347      1.1      uch 
    348      1.1      uch 	__txsibsf0_ready(tc);
    349      1.1      uch 	tx_conf_write(tc, TX39_SIBSF0CTRL_REG, reg);
    350      1.1      uch }
    351      1.1      uch 
    352      1.1      uch u_int16_t
    353  1.7.4.1  nathanw txsibsf0_reg_read(tx_chipset_tag_t tc, int addr)
    354      1.1      uch {
    355  1.7.4.1  nathanw 	return (TX39_SIBSF0_REGDATA(txsibsf0_read(tc, addr)));
    356      1.1      uch }
    357      1.1      uch 
    358      1.1      uch u_int32_t
    359  1.7.4.1  nathanw txsibsf0_read(tx_chipset_tag_t tc, int addr)
    360      1.1      uch {
    361      1.1      uch 	txreg_t reg;
    362      1.1      uch 	int retry = 3;
    363      1.1      uch 
    364      1.1      uch 	do {
    365      1.1      uch 		reg = TX39_SIBSF0_REGADDR_SET(0, addr);
    366      1.1      uch 		__txsibsf0_ready(tc);
    367      1.1      uch 		tx_conf_write(tc, TX39_SIBSF0CTRL_REG, reg);
    368      1.1      uch 
    369      1.1      uch 		__txsibsf0_ready(tc);
    370      1.1      uch 		reg = tx_conf_read(tc, TX39_SIBSF0STAT_REG);
    371      1.1      uch 
    372      1.1      uch 	} while ((TX39_SIBSF0_REGADDR(reg) != addr) && --retry > 0);
    373      1.1      uch 
    374      1.1      uch 	if (retry <= 0)
    375      1.1      uch 		printf("txsibsf0_read: command failed\n");
    376      1.1      uch 
    377  1.7.4.1  nathanw 	return (reg);
    378      1.1      uch }
    379      1.1      uch 
    380      1.4      uch #ifdef TX39SIBDEBUG
    381  1.7.4.1  nathanw #define ISSETPRINT_CTRL(r, m)						\
    382      1.1      uch 	__is_set_print(r, TX39_SIBCTRL_##m, #m)
    383  1.7.4.1  nathanw #define ISSETPRINT_DMACTRL(r, m)					\
    384      1.1      uch 	__is_set_print(r, TX39_SIBDMACTRL_##m, #m)
    385      1.1      uch 
    386      1.1      uch void
    387  1.7.4.1  nathanw tx39sib_dump(struct tx39sib_softc *sc)
    388      1.1      uch {
    389      1.1      uch 	tx_chipset_tag_t tc = sc->sc_tc;
    390      1.1      uch 	txreg_t reg;
    391      1.1      uch 
    392      1.1      uch 	reg = tx_conf_read(tc, TX39_SIBCTRL_REG);
    393      1.1      uch 	ISSETPRINT_CTRL(reg, SIBIRQ);
    394      1.1      uch 	ISSETPRINT_CTRL(reg, ENCNTTEST);
    395      1.1      uch 	ISSETPRINT_CTRL(reg, ENDMATEST);
    396      1.1      uch 	ISSETPRINT_CTRL(reg, SNDMONO);
    397      1.1      uch 	ISSETPRINT_CTRL(reg, RMONOSNDIN);
    398      1.1      uch 	ISSETPRINT_CTRL(reg, TEL16);
    399      1.1      uch 	ISSETPRINT_CTRL(reg, SND16);
    400      1.1      uch 	ISSETPRINT_CTRL(reg, SELTELSF1);
    401      1.1      uch 	ISSETPRINT_CTRL(reg, SELSNDSF1);
    402      1.1      uch 	ISSETPRINT_CTRL(reg, ENTEL);
    403      1.1      uch 	ISSETPRINT_CTRL(reg, ENSND);
    404      1.1      uch 	ISSETPRINT_CTRL(reg, SIBLOOP);
    405      1.1      uch 	ISSETPRINT_CTRL(reg, ENSF1);
    406      1.1      uch 	ISSETPRINT_CTRL(reg, ENSF0);
    407      1.1      uch 	ISSETPRINT_CTRL(reg, ENSIB);
    408      1.1      uch 	printf("\n");
    409      1.1      uch 	printf("SCLKDIV %d\n", TX39_SIBCTRL_SCLKDIV(reg));
    410      1.1      uch 	printf("TELFSDIV %d\n", TX39_SIBCTRL_TELFSDIV(reg));
    411      1.1      uch 	printf("SNDFSDIV %d\n", TX39_SIBCTRL_SNDFSDIV(reg));
    412      1.1      uch 
    413      1.1      uch 	reg = tx_conf_read(tc, TX39_SIBDMACTRL_REG);
    414      1.1      uch 	ISSETPRINT_DMACTRL(reg, SNDBUFF1TIME);
    415      1.1      uch 	ISSETPRINT_DMACTRL(reg, SNDDMALOOP);
    416      1.1      uch 	ISSETPRINT_DMACTRL(reg, ENDMARXSND);
    417      1.1      uch 	ISSETPRINT_DMACTRL(reg, ENDMATXSND);
    418      1.1      uch 	ISSETPRINT_DMACTRL(reg, TELBUFF1TIME);
    419      1.1      uch 	ISSETPRINT_DMACTRL(reg, TELDMALOOP);
    420      1.1      uch 	ISSETPRINT_DMACTRL(reg, ENDMARXTEL);
    421      1.1      uch 	ISSETPRINT_DMACTRL(reg, ENDMATXTEL);
    422      1.1      uch 	printf("\n");
    423      1.1      uch 	printf("SNDDMAPTR %d\n", TX39_SIBDMACTRL_TELDMAPTR(reg));
    424      1.1      uch 	printf("TELDMAPTR %d\n", TX39_SIBDMACTRL_SNDDMAPTR(reg));
    425      1.1      uch 
    426      1.1      uch }
    427      1.4      uch #endif /* TX39SIBDEBUG */
    428