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tx39sibvar.h revision 1.2 
      1  1.2  uch /*	$NetBSD: tx39sibvar.h,v 1.2 2000/01/12 14:56:19 uch Exp $ */
      2  1.1  uch 
      3  1.1  uch /*
      4  1.1  uch  * Copyright (c) 2000, by UCHIYAMA Yasushi
      5  1.1  uch  * All rights reserved.
      6  1.1  uch  *
      7  1.1  uch  * Redistribution and use in source and binary forms, with or without
      8  1.1  uch  * modification, are permitted provided that the following conditions
      9  1.1  uch  * are met:
     10  1.1  uch  * 1. Redistributions of source code must retain the above copyright
     11  1.1  uch  *    notice, this list of conditions and the following disclaimer.
     12  1.1  uch  * 2. The name of the developer may NOT be used to endorse or promote products
     13  1.1  uch  *    derived from this software without specific prior written permission.
     14  1.1  uch  *
     15  1.1  uch  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
     16  1.1  uch  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     17  1.1  uch  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     18  1.1  uch  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
     19  1.1  uch  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     20  1.1  uch  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     21  1.1  uch  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     22  1.1  uch  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     23  1.1  uch  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     24  1.1  uch  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     25  1.1  uch  * SUCH DAMAGE.
     26  1.1  uch  *
     27  1.1  uch  */
     28  1.1  uch 
     29  1.1  uch struct txsib_attach_args {
     30  1.1  uch 	tx_chipset_tag_t sa_tc;
     31  1.2  uch 	int sa_snd_rate;
     32  1.2  uch 	int sa_tel_rate;
     33  1.1  uch 	int sa_slot; /* subframe 0 or subframe 1 */
     34  1.1  uch };
     35  1.1  uch 
     36  1.2  uch void	tx39sib_enable1 __P((struct device*));
     37  1.2  uch void	tx39sib_enable2 __P((struct device*));
     38  1.2  uch void	tx39sib_disable __P((struct device*));
     39  1.2  uch int	tx39sib_clock __P((struct device*));
     40  1.2  uch 
     41  1.1  uch /* subframe0 access sync method */
     42  1.1  uch void		txsibsf0_reg_write __P((tx_chipset_tag_t, int, u_int16_t));
     43  1.1  uch u_int16_t	txsibsf0_reg_read __P((tx_chipset_tag_t, int));
     44  1.1  uch u_int32_t	txsibsf0_read __P((tx_chipset_tag_t, int));
     45  1.2  uch 
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