1 1.3 martin /* $NetBSD: tx39spireg.h,v 1.3 2008/04/28 20:23:22 martin Exp $ */ 2 1.1 uch 3 1.2 uch /*- 4 1.2 uch * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 1.1 uch * All rights reserved. 6 1.1 uch * 7 1.2 uch * This code is derived from software contributed to The NetBSD Foundation 8 1.2 uch * by UCHIYAMA Yasushi. 9 1.2 uch * 10 1.1 uch * Redistribution and use in source and binary forms, with or without 11 1.1 uch * modification, are permitted provided that the following conditions 12 1.1 uch * are met: 13 1.1 uch * 1. Redistributions of source code must retain the above copyright 14 1.1 uch * notice, this list of conditions and the following disclaimer. 15 1.2 uch * 2. Redistributions in binary form must reproduce the above copyright 16 1.2 uch * notice, this list of conditions and the following disclaimer in the 17 1.2 uch * documentation and/or other materials provided with the distribution. 18 1.1 uch * 19 1.2 uch * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 1.2 uch * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 1.2 uch * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 1.2 uch * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 1.2 uch * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 1.2 uch * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 1.2 uch * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 1.2 uch * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 1.2 uch * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 1.2 uch * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 1.2 uch * POSSIBILITY OF SUCH DAMAGE. 30 1.1 uch */ 31 1.1 uch /* 32 1.1 uch * Toshiba TX3912/3922 SPI module 33 1.1 uch */ 34 1.1 uch 35 1.1 uch #define TX39_SPICTRL_REG 0x160 36 1.1 uch #define TX39_SPITXHOLD_REG 0x164 /* W */ 37 1.1 uch #define TX39_SPIRXHOLD_REG 0x164 /* R */ 38 1.1 uch 39 1.1 uch /* 40 1.1 uch * SPI Control Register 41 1.1 uch */ 42 1.1 uch /* R */ 43 1.1 uch #define TX39_SPICTRL_SPION 0x00020000 44 1.1 uch #define TX39_SPICTRL_EMPTY 0x00010000 45 1.1 uch /* R/W */ 46 1.1 uch #define TX39_SPICTRL_DELAYVAL_SHIFT 12 47 1.1 uch #define TX39_SPICTRL_DELAYVAL_MASK 0xf 48 1.2 uch #define TX39_SPICTRL_DELAYVAL(cr) \ 49 1.2 uch (((cr) >> TX39_SPICTRL_DELAYVAL_SHIFT) & \ 50 1.1 uch TX39_SPICTRL_DELAYVAL_MASK) 51 1.2 uch #define TX39_SPICTRL_DELAYVAL_SET(cr, val) \ 52 1.2 uch ((cr) | (((val) << TX39_SPICTRL_DELAYVAL_SHIFT) & \ 53 1.1 uch (TX39_SPICTRL_DELAYVAL_MASK << TX39_SPICTRL_DELAYVAL_SHIFT))) 54 1.1 uch /* SPICLK Rate = 7.3728MHz/(BAUDRATE*2 + 2) */ 55 1.1 uch #define TX39_SPICTRL_BAUDRATE_SHIFT 8 56 1.1 uch #define TX39_SPICTRL_BAUDRATE_MASK 0xf 57 1.2 uch #define TX39_SPICTRL_BAUDRATE(cr) \ 58 1.2 uch (((cr) >> TX39_SPICTRL_BAUDRATE_SHIFT) & \ 59 1.1 uch TX39_SPICTRL_BAUDRATE_MASK) 60 1.2 uch #define TX39_SPICTRL_BAUDRATE_SET(cr, val) \ 61 1.2 uch ((cr) | (((val) << TX39_SPICTRL_BAUDRATE_SHIFT) & \ 62 1.1 uch (TX39_SPICTRL_BAUDRATE_MASK << TX39_SPICTRL_BAUDRATE_SHIFT))) 63 1.1 uch #define TX39_SPICTRL_PHAPOL 0x00000020 64 1.1 uch #define TX39_SPICTRL_CLKPOL 0x00000010 65 1.1 uch #define TX39_SPICTRL_WORD 0x00000004 66 1.1 uch #define TX39_SPICTRL_LSB 0x00000002 67 1.1 uch #define TX39_SPICTRL_ENSPI 0x00000001 68 1.1 uch 69 1.1 uch /* 70 1.1 uch * SPI Transmitter Holding Register 71 1.1 uch */ 72 1.1 uch /* W */ 73 1.1 uch #define TX39_SPICTRL_TXDATA_SHIFT 0 74 1.1 uch #define TX39_SPICTRL_TXDATA_MASK 0xffff 75 1.2 uch #define TX39_SPICTRL_TXDATA_SET(cr, val) \ 76 1.2 uch ((cr) | (((val) << TX39_SPICTRL_TXDATA_SHIFT) & \ 77 1.1 uch (TX39_SPICTRL_TXDATA_MASK << TX39_SPICTRL_TXDATA_SHIFT))) 78 1.1 uch 79 1.1 uch /* 80 1.1 uch * SPI Receiver Holding Register 81 1.1 uch */ 82 1.1 uch /* R */ 83 1.1 uch #define TX39_SPICTRL_RXDATA_SHIFT 8 84 1.1 uch #define TX39_SPICTRL_RXDATA_MASK 0xf 85 1.2 uch #define TX39_SPICTRL_RXDATA(cr) \ 86 1.2 uch (((cr) >> TX39_SPICTRL_RXDATA_SHIFT) & \ 87 1.1 uch TX39_SPICTRL_RXDATA_MASK) 88
Indexes created Tue Oct 28 12:10:06 GMT 2025