1 1.5 martin /* $NetBSD: tx39timerreg.h,v 1.5 2008/04/28 20:23:22 martin Exp $ */ 2 1.1 uch 3 1.4 uch /*- 4 1.4 uch * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc. 5 1.1 uch * All rights reserved. 6 1.1 uch * 7 1.4 uch * This code is derived from software contributed to The NetBSD Foundation 8 1.4 uch * by UCHIYAMA Yasushi. 9 1.4 uch * 10 1.1 uch * Redistribution and use in source and binary forms, with or without 11 1.1 uch * modification, are permitted provided that the following conditions 12 1.1 uch * are met: 13 1.1 uch * 1. Redistributions of source code must retain the above copyright 14 1.1 uch * notice, this list of conditions and the following disclaimer. 15 1.4 uch * 2. Redistributions in binary form must reproduce the above copyright 16 1.4 uch * notice, this list of conditions and the following disclaimer in the 17 1.4 uch * documentation and/or other materials provided with the distribution. 18 1.1 uch * 19 1.4 uch * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 1.4 uch * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 1.4 uch * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 1.4 uch * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 1.4 uch * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 1.4 uch * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 1.4 uch * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 1.4 uch * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 1.4 uch * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 1.4 uch * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 1.4 uch * POSSIBILITY OF SUCH DAMAGE. 30 1.1 uch */ 31 1.4 uch 32 1.1 uch /* 33 1.1 uch * Toshiba TX3912/3922 Timer module 34 1.1 uch */ 35 1.4 uch #define TX39_TIMERRTCHI_REG 0x140 36 1.4 uch #define TX39_TIMERRTCLO_REG 0x144 37 1.4 uch #define TX39_TIMERALARMHI_REG 0x148 38 1.4 uch #define TX39_TIMERALARMLO_REG 0x14C 39 1.4 uch #define TX39_TIMERCONTROL_REG 0x150 40 1.4 uch #define TX39_TIMERPERIODIC_REG 0x154 41 1.1 uch 42 1.2 uch /* Periodic timer (1.15MHz) */ 43 1.2 uch #ifdef TX391X 44 1.2 uch /* 45 1.2 uch * TX3912 base clock is 36.864MHz 46 1.2 uch */ 47 1.4 uch #define TX39_TIMERCLK 1152000 48 1.2 uch #endif 49 1.2 uch #ifdef TX392X 50 1.2 uch /* 51 1.2 uch * TX3922 base clock seems to be 32.25MHz (Telios) 52 1.2 uch */ 53 1.4 uch #define TX39_TIMERCLK 1007812 54 1.2 uch #endif 55 1.2 uch 56 1.2 uch /* Real timer clock (32.768kHz) */ 57 1.4 uch #define TX39_RTCLOCK 32768 58 1.4 uch #define TX39_MSEC2RTC(m) ((TX39_RTCLOCK * (m)) / 1000) 59 1.2 uch 60 1.1 uch /* 61 1.1 uch * RTC Register High/Low 62 1.1 uch */ 63 1.1 uch /* R */ 64 1.4 uch #define TX39_TIMERRTCHI_SHIFT 0 65 1.1 uch #ifdef TX391X 66 1.4 uch #define TX39_TIMERRTCHI_MASK 0xff 67 1.1 uch #endif /* TX391X */ 68 1.1 uch #ifdef TX392X 69 1.4 uch #define TX39_TIMERRTCHI_MASK 0x7ff 70 1.1 uch #endif /* TX392X */ 71 1.1 uch 72 1.4 uch #define TX39_TIMERRTCHI(cr) ((cr) & TX39_TIMERRTCHI_MASK) 73 1.1 uch 74 1.1 uch /* 75 1.1 uch * Alarm Register High/Low 76 1.1 uch */ 77 1.1 uch /* R/W */ 78 1.4 uch #ifdef TX391X /* 40bit */ 79 1.4 uch #define TX39_TIMERALARMHI_SHIFT 0 80 1.4 uch #define TX39_TIMERALARMHI_MASK 0xff 81 1.1 uch #endif /* TX391X */ 82 1.4 uch #ifdef TX392X /* 43bit */ 83 1.4 uch #define TX39_TIMERALARMHI_SHIFT 0 84 1.4 uch #define TX39_TIMERALARMHI_MASK 0x7ff 85 1.1 uch #endif /* TX392X */ 86 1.4 uch 87 1.4 uch #define TX39_TIMERALARMHI(cr) ((cr) & TX39_TIMERALARMHI_MASK) 88 1.4 uch 89 1.1 uch /* 90 1.1 uch * Timer Control Register 91 1.1 uch */ 92 1.1 uch #define TX39_TIMERCONTROL_FREEZEPRE 0x00000080 93 1.1 uch #define TX39_TIMERCONTROL_FREEZERTC 0x00000040 94 1.1 uch #define TX39_TIMERCONTROL_FREEZETIMER 0x00000020 95 1.1 uch #define TX39_TIMERCONTROL_ENPERTIMER 0x00000010 96 1.2 uch #define TX39_TIMERCONTROL_RTCCLR 0x00000008 97 1.1 uch #define TX39_TIMERCONTROL_TESTCMS 0x00000004 /* Don't set */ 98 1.2 uch #define TX39_TIMERCONTROL_ENTESTCLK 0x00000002 /* Don't set */ 99 1.1 uch #define TX39_TIMERCONTROL_ENRTCTST 0x00000001 100 1.1 uch 101 1.1 uch /* 102 1.1 uch * Periodic Timer Register 103 1.1 uch */ 104 1.1 uch /* R */ 105 1.1 uch #define TX39_TIMERPERIODIC_PERCNT_SHIFT 15 106 1.1 uch #define TX39_TIMERPERIODIC_PERCNT_MASK 0xffff 107 1.4 uch #define TX39_TIMERPERIODIC_PERCNT(cr) \ 108 1.4 uch (((cr) >> TX39_TIMERPERIODIC_PERCNT_SHIFT) & \ 109 1.1 uch TX39_TIMERPERIODIC_PERCNT_MASK) 110 1.1 uch /* R/W */ 111 1.1 uch #define TX39_TIMERPERIODIC_PERVAL_SHIFT 0 112 1.1 uch #define TX39_TIMERPERIODIC_PERVAL_MASK 0xffff 113 1.4 uch #define TX39_TIMERPERIODIC_PERVAL(cr) \ 114 1.4 uch (((cr) >> TX39_TIMERPERIODIC_PERVAL_SHIFT) & \ 115 1.1 uch TX39_TIMERPERIODIC_PERVAL_MASK) 116 1.4 uch #define TX39_TIMERPERIODIC_PERVAL_SET(cr, val) \ 117 1.4 uch ((cr) | (((val) << TX39_TIMERPERIODIC_PERVAL_SHIFT) & \ 118 1.1 uch (TX39_TIMERPERIODIC_PERVAL_MASK << TX39_TIMERPERIODIC_PERVAL_SHIFT))) 119 1.4 uch #define TX39_TIMERPERIODIC_PERVAL_CLR(cr) ((cr) &= \ 120 1.2 uch ~(TX39_TIMERPERIODIC_PERVAL_MASK << TX39_TIMERPERIODIC_PERVAL_SHIFT)) 121 1.4 uch #define TX39_TIMERPERIODIC_INTRRATE(val) \ 122 1.2 uch ((val) + 1)/TX39_TIMERCLK /* unit:Hz */ 123 1.2 uch 124
Indexes created Tue Oct 28 02:10:10 GMT 2025