tx39timerreg.h revision 1.2
1 1.2 uch /* $NetBSD: tx39timerreg.h,v 1.2 1999/12/22 15:35:35 uch Exp $ */ 2 1.1 uch 3 1.1 uch /* 4 1.1 uch * Copyright (c) 1999, by UCHIYAMA Yasushi 5 1.1 uch * All rights reserved. 6 1.1 uch * 7 1.1 uch * Redistribution and use in source and binary forms, with or without 8 1.1 uch * modification, are permitted provided that the following conditions 9 1.1 uch * are met: 10 1.1 uch * 1. Redistributions of source code must retain the above copyright 11 1.1 uch * notice, this list of conditions and the following disclaimer. 12 1.1 uch * 2. The name of the developer may NOT be used to endorse or promote products 13 1.1 uch * derived from this software without specific prior written permission. 14 1.1 uch * 15 1.1 uch * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 1.1 uch * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 1.1 uch * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 1.1 uch * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 1.1 uch * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 1.1 uch * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 1.1 uch * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 1.1 uch * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 1.1 uch * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 1.1 uch * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 1.1 uch * SUCH DAMAGE. 26 1.1 uch * 27 1.1 uch */ 28 1.1 uch /* 29 1.1 uch * Toshiba TX3912/3922 Timer module 30 1.1 uch */ 31 1.1 uch 32 1.1 uch #define TX39_TIMERRTCHI_REG 0x140 33 1.2 uch #define TX39_TIMERRTCLO_REG 0x144 34 1.1 uch #define TX39_TIMERALARMHI_REG 0x148 35 1.1 uch #define TX39_TIMERALARMLO_REG 0x14C 36 1.1 uch #define TX39_TIMERCONTROL_REG 0x150 37 1.1 uch #define TX39_TIMERPERIODIC_REG 0x154 38 1.1 uch 39 1.2 uch /* Periodic timer (1.15MHz) */ 40 1.2 uch #ifdef TX391X 41 1.2 uch /* 42 1.2 uch * TX3912 base clock is 36.864MHz 43 1.2 uch */ 44 1.2 uch #define TX39_TIMERCLK 1152000 45 1.2 uch #endif 46 1.2 uch #ifdef TX392X 47 1.2 uch /* 48 1.2 uch * TX3922 base clock seems to be 32.25MHz (Telios) 49 1.2 uch */ 50 1.2 uch #define TX39_TIMERCLK 1007812 51 1.2 uch #endif 52 1.2 uch 53 1.2 uch /* Real timer clock (32.768kHz) */ 54 1.2 uch #define TX39_RTCLOCK 32768 55 1.2 uch 56 1.1 uch /* 57 1.1 uch * RTC Register High/Low 58 1.1 uch */ 59 1.1 uch /* R */ 60 1.1 uch #define TX39_TIMERRTCHI_SHIFT 0 61 1.1 uch #ifdef TX391X 62 1.1 uch #define TX39_TIMERRTCHI_MASK 0xff 63 1.1 uch #endif /* TX391X */ 64 1.1 uch #ifdef TX392X 65 1.1 uch #define TX39_TIMERRTCHI_MASK 0x7ff 66 1.1 uch #endif /* TX392X */ 67 1.1 uch 68 1.1 uch #define TX39_TIMERRTCHI(cr) \ 69 1.1 uch (((cr) >> TX39_TIMERRTCHI_SHIFT) & \ 70 1.2 uch TX39_TIMERRTCHI_MASK) 71 1.1 uch 72 1.1 uch /* 73 1.1 uch * Alarm Register High/Low 74 1.1 uch */ 75 1.1 uch /* R/W */ 76 1.1 uch #ifdef TX391X 77 1.1 uch #define TX39_TIMERALARMHI_SHIFT 0 78 1.1 uch #define TX39_TIMERALARMHI_MASK 0xff 79 1.1 uch #define TX39_TIMERALARMHI(cr) \ 80 1.1 uch (((cr) >> TX39_TIMERALARMHI_SHIFT) & \ 81 1.1 uch TX39_TIMERALARMHI_MASK) 82 1.1 uch #define TX39_TIMERALARMHI_SET(cr, val) \ 83 1.1 uch ((cr) | (((val) << TX39_TIMERALARMHI_SHIFT) & \ 84 1.1 uch (TX39_TIMERALARMHI_MASK << TX39_TIMERALARMHI_SHIFT))) 85 1.1 uch #endif /* TX391X */ 86 1.1 uch #ifdef TX392X 87 1.1 uch #define TX39_TIMERALARMHI_SHIFT 0 88 1.1 uch #define TX39_TIMERALARMHI_MASK 0x7ff 89 1.1 uch #define TX39_TIMERALARMHI(cr) \ 90 1.1 uch (((cr) >> TX39_TIMERALARMHI_SHIFT) & \ 91 1.1 uch TX39_TIMERALARMHI_MASK) 92 1.1 uch #define TX39_TIMERALARMHI_SET(cr, val) \ 93 1.1 uch ((cr) | (((val) << TX39_TIMERALARMHI_SHIFT) & \ 94 1.1 uch (TX39_TIMERALARMHI_MASK << TX39_TIMERALARMHI_SHIFT))) 95 1.1 uch #endif /* TX392X */ 96 1.1 uch /* 97 1.1 uch * Timer Control Register 98 1.1 uch */ 99 1.1 uch #define TX39_TIMERCONTROL_FREEZEPRE 0x00000080 100 1.1 uch #define TX39_TIMERCONTROL_FREEZERTC 0x00000040 101 1.1 uch #define TX39_TIMERCONTROL_FREEZETIMER 0x00000020 102 1.1 uch #define TX39_TIMERCONTROL_ENPERTIMER 0x00000010 103 1.2 uch #define TX39_TIMERCONTROL_RTCCLR 0x00000008 104 1.1 uch #define TX39_TIMERCONTROL_TESTCMS 0x00000004 /* Don't set */ 105 1.2 uch #define TX39_TIMERCONTROL_ENTESTCLK 0x00000002 /* Don't set */ 106 1.1 uch #define TX39_TIMERCONTROL_ENRTCTST 0x00000001 107 1.1 uch 108 1.1 uch /* 109 1.1 uch * Periodic Timer Register 110 1.1 uch */ 111 1.1 uch /* R */ 112 1.1 uch #define TX39_TIMERPERIODIC_PERCNT_SHIFT 15 113 1.1 uch #define TX39_TIMERPERIODIC_PERCNT_MASK 0xffff 114 1.1 uch #define TX39_TIMERPERIODIC_PERCNT(cr) \ 115 1.1 uch (((cr) >> TX39_TIMERPERIODIC_PERCNT_SHIFT) & \ 116 1.1 uch TX39_TIMERPERIODIC_PERCNT_MASK) 117 1.1 uch /* R/W */ 118 1.1 uch #define TX39_TIMERPERIODIC_PERVAL_SHIFT 0 119 1.1 uch #define TX39_TIMERPERIODIC_PERVAL_MASK 0xffff 120 1.1 uch #define TX39_TIMERPERIODIC_PERVAL(cr) \ 121 1.1 uch (((cr) >> TX39_TIMERPERIODIC_PERVAL_SHIFT) & \ 122 1.1 uch TX39_TIMERPERIODIC_PERVAL_MASK) 123 1.1 uch #define TX39_TIMERPERIODIC_PERVAL_SET(cr, val) \ 124 1.1 uch ((cr) | (((val) << TX39_TIMERPERIODIC_PERVAL_SHIFT) & \ 125 1.1 uch (TX39_TIMERPERIODIC_PERVAL_MASK << TX39_TIMERPERIODIC_PERVAL_SHIFT))) 126 1.2 uch #define TX39_TIMERPERIODIC_PERVAL_CLR(cr) ((cr) &= \ 127 1.2 uch ~(TX39_TIMERPERIODIC_PERVAL_MASK << TX39_TIMERPERIODIC_PERVAL_SHIFT)) 128 1.1 uch #define TX39_TIMERPERIODIC_INTRRATE(val) \ 129 1.2 uch ((val) + 1)/TX39_TIMERCLK /* unit:Hz */ 130 1.2 uch 131
Indexes created Wed Oct 29 18:09:52 GMT 2025