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tx39timerreg.h revision 1.3 
      1 /*	$NetBSD: tx39timerreg.h,v 1.3 2000/01/03 18:24:04 uch Exp $ */
      2 
      3 /*
      4  * Copyright (c) 1999, 2000 by UCHIYAMA Yasushi
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. The name of the developer may NOT be used to endorse or promote products
     13  *    derived from this software without specific prior written permission.
     14  *
     15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
     16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
     19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     25  * SUCH DAMAGE.
     26  *
     27  */
     28 /*
     29  * Toshiba TX3912/3922 Timer module
     30  */
     31 
     32 #define TX39_TIMERRTCHI_REG	0x140
     33 #define TX39_TIMERRTCLO_REG	0x144
     34 #define TX39_TIMERALARMHI_REG	0x148
     35 #define TX39_TIMERALARMLO_REG	0x14C
     36 #define TX39_TIMERCONTROL_REG	0x150
     37 #define	TX39_TIMERPERIODIC_REG	0x154
     38 
     39 /* Periodic timer (1.15MHz) */
     40 #ifdef TX391X
     41 /*
     42  * TX3912 base clock is 36.864MHz
     43  */
     44 #define TX39_TIMERCLK		1152000
     45 #endif
     46 #ifdef TX392X
     47 /*
     48  * TX3922 base clock seems to be 32.25MHz (Telios)
     49  */
     50 #define TX39_TIMERCLK		1007812
     51 #endif
     52 
     53 /* Real timer clock (32.768kHz) */
     54 #define TX39_RTCLOCK		32768
     55 #define TX39_MSEC2RTC(m)	((TX39_RTCLOCK * m) / 1000)
     56 
     57 /*
     58  *	RTC Register High/Low
     59  */
     60 /* R */
     61 #define TX39_TIMERRTCHI_SHIFT	0
     62 #ifdef TX391X
     63 #define TX39_TIMERRTCHI_MASK	0xff
     64 #endif /* TX391X */
     65 #ifdef TX392X
     66 #define TX39_TIMERRTCHI_MASK	0x7ff
     67 #endif /* TX392X */
     68 
     69 #define TX39_TIMERRTCHI(cr) \
     70 	(((cr) >> TX39_TIMERRTCHI_SHIFT) & \
     71 	TX39_TIMERRTCHI_MASK)
     72 
     73 /*
     74  *	Alarm Register High/Low
     75  */
     76 /* R/W */
     77 #ifdef TX391X
     78 #define TX39_TIMERALARMHI_SHIFT 0
     79 #define TX39_TIMERALARMHI_MASK	0xff
     80 #define TX39_TIMERALARMHI(cr) \
     81 	(((cr) >> TX39_TIMERALARMHI_SHIFT) & \
     82 	TX39_TIMERALARMHI_MASK)
     83 #define TX39_TIMERALARMHI_SET(cr, val) \
     84 	((cr) | (((val) << TX39_TIMERALARMHI_SHIFT) & \
     85 	(TX39_TIMERALARMHI_MASK << TX39_TIMERALARMHI_SHIFT)))
     86 #endif /* TX391X */
     87 #ifdef TX392X
     88 #define TX39_TIMERALARMHI_SHIFT 0
     89 #define TX39_TIMERALARMHI_MASK	0x7ff
     90 #define TX39_TIMERALARMHI(cr) \
     91 	(((cr) >> TX39_TIMERALARMHI_SHIFT) & \
     92 	TX39_TIMERALARMHI_MASK)
     93 #define TX39_TIMERALARMHI_SET(cr, val) \
     94 	((cr) | (((val) << TX39_TIMERALARMHI_SHIFT) & \
     95 	(TX39_TIMERALARMHI_MASK << TX39_TIMERALARMHI_SHIFT)))
     96 #endif /* TX392X */
     97 /*
     98  *	Timer Control Register
     99  */
    100 #define TX39_TIMERCONTROL_FREEZEPRE	0x00000080
    101 #define TX39_TIMERCONTROL_FREEZERTC	0x00000040
    102 #define TX39_TIMERCONTROL_FREEZETIMER	0x00000020
    103 #define TX39_TIMERCONTROL_ENPERTIMER	0x00000010
    104 #define TX39_TIMERCONTROL_RTCCLR	0x00000008
    105 #define TX39_TIMERCONTROL_TESTCMS	0x00000004	/* Don't set */
    106 #define TX39_TIMERCONTROL_ENTESTCLK	0x00000002	/* Don't set */
    107 #define TX39_TIMERCONTROL_ENRTCTST	0x00000001
    108 
    109 /*
    110  *	Periodic Timer Register
    111  */
    112 /* R */
    113 #define TX39_TIMERPERIODIC_PERCNT_SHIFT 15
    114 #define TX39_TIMERPERIODIC_PERCNT_MASK	0xffff
    115 #define TX39_TIMERPERIODIC_PERCNT(cr) \
    116 	(((cr) >> TX39_TIMERPERIODIC_PERCNT_SHIFT) & \
    117 	TX39_TIMERPERIODIC_PERCNT_MASK)
    118 /* R/W */
    119 #define TX39_TIMERPERIODIC_PERVAL_SHIFT 0
    120 #define TX39_TIMERPERIODIC_PERVAL_MASK	0xffff
    121 #define TX39_TIMERPERIODIC_PERVAL(cr) \
    122 	(((cr) >> TX39_TIMERPERIODIC_PERVAL_SHIFT) & \
    123 	TX39_TIMERPERIODIC_PERVAL_MASK)
    124 #define TX39_TIMERPERIODIC_PERVAL_SET(cr, val) \
    125 	((cr) | (((val) << TX39_TIMERPERIODIC_PERVAL_SHIFT) & \
    126 	(TX39_TIMERPERIODIC_PERVAL_MASK << TX39_TIMERPERIODIC_PERVAL_SHIFT)))
    127 #define TX39_TIMERPERIODIC_PERVAL_CLR(cr) ((cr) &= \
    128 	 ~(TX39_TIMERPERIODIC_PERVAL_MASK << TX39_TIMERPERIODIC_PERVAL_SHIFT))
    129 #define TX39_TIMERPERIODIC_INTRRATE(val) \
    130 	((val) + 1)/TX39_TIMERCLK /* unit:Hz */
    131 
    132