tx39uartreg.h revision 1.1
1 /* $NetBSD: tx39uartreg.h,v 1.1 1999/11/20 19:56:38 uch Exp $ */ 2 3 /* 4 * Copyright (c) 1999, by UCHIYAMA Yasushi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. The name of the developer may NOT be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 /* 29 * Toshiba TX3912/3922 UART module 30 */ 31 32 #define TX39_UARTACTRL1_REG 0x0b0 33 #define TX39_UARTACTRL2_REG 0x0b4 34 #define TX39_UARTADMACTRL1_REG 0x0b8 35 #define TX39_UARTADMACTRL2_REG 0x0bc 36 #define TX39_UARTADMACNT_REG 0x0c0 37 #define TX39_UARTATXHOLD_REG 0x0c4 38 #define TX39_UARTARXHOLD_REG 0x0c4 39 40 #define TX39_UARTBCTRL1_REG 0x0c8 41 #define TX39_UARTBCTRL2_REG 0x0cc 42 #define TX39_UARTBDMACTRL1_REG 0x0d0 43 #define TX39_UARTBDMACTRL2_REG 0x0d4 44 #define TX39_UARTBDMACNT_REG 0x0d8 45 #define TX39_UARTBTXHOLD_REG 0x0dc 46 #define TX39_UARTBRXHOLD_REG 0x0dc 47 48 #define TX39_UARTA_REG_START 0x0b0 49 #define TX39_UARTB_REG_START 0x0c8 50 #define TX39_UARTCTRL1_REG(x) \ 51 (((x) ? TX39_UARTB_REG_START : TX39_UARTA_REG_START)) 52 #define TX39_UARTCTRL2_REG(x) \ 53 (((x) ? TX39_UARTB_REG_START : TX39_UARTA_REG_START) + 4) 54 #define TX39_UARTDMACTRL1_REG(x) \ 55 (((x) ? TX39_UARTB_REG_START : TX39_UARTA_REG_START) + 8) 56 #define TX39_UARTDMACTRL2_REG(x) \ 57 (((x) ? TX39_UARTB_REG_START : TX39_UARTA_REG_START) + 12) 58 #define TX39_UARTDMACNT_REG(x) \ 59 (((x) ? TX39_UARTB_REG_START : TX39_UARTA_REG_START) + 16) 60 #define TX39_UARTTXHOLD_REG(x) \ 61 (((x) ? TX39_UARTB_REG_START : TX39_UARTA_REG_START) + 20) 62 #define TX39_UARTRXHOLD_REG(x) \ 63 (((x) ? TX39_UARTB_REG_START : TX39_UARTA_REG_START) + 20) 64 65 /* 66 * UART Control 1 Register 67 */ 68 /* R */ 69 #define TX39_UARTCTRL1_UARTON 0x80000000 70 #define TX39_UARTCTRL1_EMPTY 0x40000000 71 #define TX39_UARTCTRL1_PRXHOLDFULL 0x20000000 72 #define TX39_UARTCTRL1_RXHOLDFULL 0x10000000 73 /* R/W */ 74 #define TX39_UARTCTRL1_ENDMARX 0x00008000 75 #define TX39_UARTCTRL1_ENDMATX 0x00004000 76 #define TX39_UARTCTRL1_TESTMODE 0x00002000 77 #define TX39_UARTCTRL1_ENBREAHALT 0x00001000 78 #define TX39_UARTCTRL1_ENDMATEST 0x00000800 79 #define TX39_UARTCTRL1_ENDMALOOP 0x00000400 80 #define TX39_UARTCTRL1_PULSEOPT2 0x00000200 81 #define TX39_UARTCTRL1_PULSEOPT1 0x00000100 82 #define TX39_UARTCTRL1_DTINVERT 0x00000080 83 #define TX39_UARTCTRL1_DISTXD 0x00000040 84 #define TX39_UARTCTRL1_TWOSTOP 0x00000020 85 #define TX39_UARTCTRL1_LOOPBACK 0x00000010 86 #define TX39_UARTCTRL1_BIT7 0x00000008 87 #define TX39_UARTCTRL1_EVENPARITY 0x00000004 88 #define TX39_UARTCTRL1_ENPARITY 0x00000002 89 #define TX39_UARTCTRL1_ENUART 0x00000001 90 91 /* 92 * UART Control 2 Register 93 */ 94 /* W */ 95 /* 96 * BaudRate = UART Clock Hz / ((BAUDRATE + 1) * 16) 97 */ 98 #define TX3922_UARTCLOCKHZ 9216000 99 #define TX3912_UARTCLOCKHZ 3686400 100 101 #define TX39_UARTCTRL2_BAUDRATE_SHIFT 0 102 103 #define TX3912_UARTCTRL2_BAUDRATE_MASK 0x3ff 104 #define TX3922_UARTCTRL2_BAUDRATE_MASK 0x7ff 105 106 #ifdef TX391X 107 #define TX39_UARTCLOCKHZ TX3912_UARTCLOCKHZ 108 #define TX39_UARTCTRL2_BAUDRATE_MASK TX3912_UARTCTRL2_BAUDRATE_MASK 109 #elif defined TX392X 110 #define TX39_UARTCLOCKHZ TX3922_UARTCLOCKHZ 111 #define TX39_UARTCTRL2_BAUDRATE_MASK TX3922_UARTCTRL2_BAUDRATE_MASK 112 #endif 113 114 #define TX39_UARTCTRL2_BAUDRATE_SET(cr, val) \ 115 ((cr) | (((val) << TX39_UARTCTRL2_BAUDRATE_SHIFT) & \ 116 (TX39_UARTCTRL2_BAUDRATE_MASK << TX39_UARTCTRL2_BAUDRATE_SHIFT))) 117 118 /* 119 * UART DMA Control 1 Register 120 */ 121 /* W */ 122 #define TX39_UARTDMACTRL1_DMASTARTVAL_MASK 0xfffffffc 123 #define TX39_UARTDMACTRL1_DMASTARTVAL_SET(cr, val) \ 124 ((cr) | ((val) & TX39_UARTDMACTRL1_DMASTARTVAL_MASK)) 125 126 /* 127 * UART DMA Control 2 Register 128 */ 129 /* W */ 130 #define TX39_UARTDMACTRL2_DMALENGTH_MASK 0x0000ffff 131 #define TX39_UARTDMACTRL2_DMALENGTH_SET(cr, val) \ 132 ((cr) | ((val) & TX39_UARTDMACTRL1_DMALENGTH_MASK)) 133 134 /* 135 * UART DMA Count Register 136 */ 137 /* R */ 138 #define TX39_UARTDMACNT_DMACNT_SHIFT 0 139 #define TX39_UARTDMACNT_DMACNT_MASK 0xffff 140 #define TX39_UARTDMACNT_DMACNT(cr) \ 141 ((cr) & TX39_UARTDMACNT_DMACNT_MASK) 142 143 /* 144 * UART Transmit Holding Register 145 */ 146 /* W */ 147 #define TX39_UARTTXHOLD_BREAK 0x00000100 148 #define TX39_UARTTXHOLD_TXDATA_SHIFT 0 149 #define TX39_UARTTXHOLD_TXDATA_MASK 0x000000ff 150 #define TX39_UARTTXHOLD_TXDATA_SET(cr, val) \ 151 ((cr) | ((val) & TX39_UARTTXHOLD_TXDATA_MASK)) 152 153 /* 154 * UART Receiver Holding Register 155 */ 156 /* R */ 157 #define TX39_UARTRXHOLD_RXDATA_SHIFT 0 158 #define TX39_UARTRXHOLD_RXDATA_MASK 0x000000ff 159 #define TX39_UARTRXHOLD_RXDATA(cr) \ 160 ((cr) & TX39_UARTRXHOLD_RXDATA_MASK) 161
Indexes created Wed Oct 29 20:09:47 GMT 2025