tx39uartreg.h revision 1.2
1 /* $NetBSD: tx39uartreg.h,v 1.2 2001/06/14 11:09:56 uch Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 /* 39 * Toshiba TX3912/3922 UART module 40 */ 41 42 #define TX39_UARTACTRL1_REG 0x0b0 43 #define TX39_UARTACTRL2_REG 0x0b4 44 #define TX39_UARTADMACTRL1_REG 0x0b8 45 #define TX39_UARTADMACTRL2_REG 0x0bc 46 #define TX39_UARTADMACNT_REG 0x0c0 47 #define TX39_UARTATXHOLD_REG 0x0c4 48 #define TX39_UARTARXHOLD_REG 0x0c4 49 50 #define TX39_UARTBCTRL1_REG 0x0c8 51 #define TX39_UARTBCTRL2_REG 0x0cc 52 #define TX39_UARTBDMACTRL1_REG 0x0d0 53 #define TX39_UARTBDMACTRL2_REG 0x0d4 54 #define TX39_UARTBDMACNT_REG 0x0d8 55 #define TX39_UARTBTXHOLD_REG 0x0dc 56 #define TX39_UARTBRXHOLD_REG 0x0dc 57 58 #define TX39_UARTA_REG_START 0x0b0 59 #define TX39_UARTB_REG_START 0x0c8 60 #define TX39_UARTCTRL1_REG(x) \ 61 (((x) ? TX39_UARTB_REG_START : TX39_UARTA_REG_START)) 62 #define TX39_UARTCTRL2_REG(x) \ 63 (((x) ? TX39_UARTB_REG_START : TX39_UARTA_REG_START) + 4) 64 #define TX39_UARTDMACTRL1_REG(x) \ 65 (((x) ? TX39_UARTB_REG_START : TX39_UARTA_REG_START) + 8) 66 #define TX39_UARTDMACTRL2_REG(x) \ 67 (((x) ? TX39_UARTB_REG_START : TX39_UARTA_REG_START) + 12) 68 #define TX39_UARTDMACNT_REG(x) \ 69 (((x) ? TX39_UARTB_REG_START : TX39_UARTA_REG_START) + 16) 70 #define TX39_UARTTXHOLD_REG(x) \ 71 (((x) ? TX39_UARTB_REG_START : TX39_UARTA_REG_START) + 20) 72 #define TX39_UARTRXHOLD_REG(x) \ 73 (((x) ? TX39_UARTB_REG_START : TX39_UARTA_REG_START) + 20) 74 75 /* 76 * UART Control 1 Register 77 */ 78 /* R */ 79 #define TX39_UARTCTRL1_UARTON 0x80000000 80 #define TX39_UARTCTRL1_EMPTY 0x40000000 81 #define TX39_UARTCTRL1_PRXHOLDFULL 0x20000000 82 #define TX39_UARTCTRL1_RXHOLDFULL 0x10000000 83 /* R/W */ 84 #define TX39_UARTCTRL1_ENDMARX 0x00008000 85 #define TX39_UARTCTRL1_ENDMATX 0x00004000 86 #define TX39_UARTCTRL1_TESTMODE 0x00002000 87 #define TX39_UARTCTRL1_ENBREAHALT 0x00001000 88 #define TX39_UARTCTRL1_ENDMATEST 0x00000800 89 #define TX39_UARTCTRL1_ENDMALOOP 0x00000400 90 #define TX39_UARTCTRL1_PULSEOPT2 0x00000200 91 #define TX39_UARTCTRL1_PULSEOPT1 0x00000100 92 #define TX39_UARTCTRL1_DTINVERT 0x00000080 93 #define TX39_UARTCTRL1_DISTXD 0x00000040 94 #define TX39_UARTCTRL1_TWOSTOP 0x00000020 95 #define TX39_UARTCTRL1_LOOPBACK 0x00000010 96 #define TX39_UARTCTRL1_BIT7 0x00000008 97 #define TX39_UARTCTRL1_EVENPARITY 0x00000004 98 #define TX39_UARTCTRL1_ENPARITY 0x00000002 99 #define TX39_UARTCTRL1_ENUART 0x00000001 100 101 /* 102 * UART Control 2 Register 103 */ 104 /* W */ 105 /* 106 * BaudRate = UART Clock Hz / ((BAUDRATE + 1) * 16) 107 */ 108 #define TX3922_UARTCLOCKHZ 9216000 109 #define TX3912_UARTCLOCKHZ 3686400 110 111 #define TX39_UARTCTRL2_BAUDRATE_SHIFT 0 112 113 #define TX3912_UARTCTRL2_BAUDRATE_MASK 0x3ff 114 #define TX3922_UARTCTRL2_BAUDRATE_MASK 0x7ff 115 116 #ifdef TX391X 117 #define TX39_UARTCLOCKHZ TX3912_UARTCLOCKHZ 118 #define TX39_UARTCTRL2_BAUDRATE_MASK TX3912_UARTCTRL2_BAUDRATE_MASK 119 #elif defined TX392X 120 #define TX39_UARTCLOCKHZ TX3922_UARTCLOCKHZ 121 #define TX39_UARTCTRL2_BAUDRATE_MASK TX3922_UARTCTRL2_BAUDRATE_MASK 122 #endif 123 124 #define TX39_UARTCTRL2_BAUDRATE_SET(cr, val) \ 125 ((cr) | (((val) << TX39_UARTCTRL2_BAUDRATE_SHIFT) & \ 126 (TX39_UARTCTRL2_BAUDRATE_MASK << TX39_UARTCTRL2_BAUDRATE_SHIFT))) 127 128 /* 129 * UART DMA Control 1 Register 130 */ 131 /* W */ 132 #define TX39_UARTDMACTRL1_DMASTARTVAL_MASK 0xfffffffc 133 #define TX39_UARTDMACTRL1_DMASTARTVAL_SET(cr, val) \ 134 ((cr) | ((val) & TX39_UARTDMACTRL1_DMASTARTVAL_MASK)) 135 136 /* 137 * UART DMA Control 2 Register 138 */ 139 /* W */ 140 #define TX39_UARTDMACTRL2_DMALENGTH_MASK 0x0000ffff 141 #define TX39_UARTDMACTRL2_DMALENGTH_SET(cr, val) \ 142 ((cr) | ((val) & TX39_UARTDMACTRL1_DMALENGTH_MASK)) 143 144 /* 145 * UART DMA Count Register 146 */ 147 /* R */ 148 #define TX39_UARTDMACNT_DMACNT_SHIFT 0 149 #define TX39_UARTDMACNT_DMACNT_MASK 0xffff 150 #define TX39_UARTDMACNT_DMACNT(cr) \ 151 ((cr) & TX39_UARTDMACNT_DMACNT_MASK) 152 153 /* 154 * UART Transmit Holding Register 155 */ 156 /* W */ 157 #define TX39_UARTTXHOLD_BREAK 0x00000100 158 #define TX39_UARTTXHOLD_TXDATA_SHIFT 0 159 #define TX39_UARTTXHOLD_TXDATA_MASK 0x000000ff 160 #define TX39_UARTTXHOLD_TXDATA_SET(cr, val) \ 161 ((cr) | ((val) & TX39_UARTTXHOLD_TXDATA_MASK)) 162 163 /* 164 * UART Receiver Holding Register 165 */ 166 /* R */ 167 #define TX39_UARTRXHOLD_RXDATA_SHIFT 0 168 #define TX39_UARTRXHOLD_RXDATA_MASK 0x000000ff 169 #define TX39_UARTRXHOLD_RXDATA(cr) \ 170 ((cr) & TX39_UARTRXHOLD_RXDATA_MASK) 171
Indexes created Wed Oct 29 20:09:47 GMT 2025