txcom.c revision 1.14.8.5 1 1.14.8.5 nathanw /* $NetBSD: txcom.c,v 1.14.8.5 2002/10/18 02:37:14 nathanw Exp $ */
2 1.14.8.2 nathanw
3 1.14.8.2 nathanw /*-
4 1.14.8.2 nathanw * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc.
5 1.14.8.2 nathanw * All rights reserved.
6 1.14.8.2 nathanw *
7 1.14.8.2 nathanw * This code is derived from software contributed to The NetBSD Foundation
8 1.14.8.2 nathanw * by UCHIYAMA Yasushi.
9 1.14.8.2 nathanw *
10 1.14.8.2 nathanw * Redistribution and use in source and binary forms, with or without
11 1.14.8.2 nathanw * modification, are permitted provided that the following conditions
12 1.14.8.2 nathanw * are met:
13 1.14.8.2 nathanw * 1. Redistributions of source code must retain the above copyright
14 1.14.8.2 nathanw * notice, this list of conditions and the following disclaimer.
15 1.14.8.2 nathanw * 2. Redistributions in binary form must reproduce the above copyright
16 1.14.8.2 nathanw * notice, this list of conditions and the following disclaimer in the
17 1.14.8.2 nathanw * documentation and/or other materials provided with the distribution.
18 1.14.8.2 nathanw * 3. All advertising materials mentioning features or use of this software
19 1.14.8.2 nathanw * must display the following acknowledgement:
20 1.14.8.2 nathanw * This product includes software developed by the NetBSD
21 1.14.8.2 nathanw * Foundation, Inc. and its contributors.
22 1.14.8.2 nathanw * 4. Neither the name of The NetBSD Foundation nor the names of its
23 1.14.8.2 nathanw * contributors may be used to endorse or promote products derived
24 1.14.8.2 nathanw * from this software without specific prior written permission.
25 1.14.8.2 nathanw *
26 1.14.8.2 nathanw * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 1.14.8.2 nathanw * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 1.14.8.2 nathanw * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 1.14.8.2 nathanw * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 1.14.8.2 nathanw * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 1.14.8.2 nathanw * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 1.14.8.2 nathanw * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 1.14.8.2 nathanw * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 1.14.8.2 nathanw * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 1.14.8.2 nathanw * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 1.14.8.2 nathanw * POSSIBILITY OF SUCH DAMAGE.
37 1.14.8.2 nathanw */
38 1.14.8.2 nathanw
39 1.14.8.2 nathanw #include "opt_tx39uart_debug.h"
40 1.14.8.2 nathanw
41 1.14.8.2 nathanw #include <sys/param.h>
42 1.14.8.2 nathanw #include <sys/systm.h>
43 1.14.8.2 nathanw #include <sys/kernel.h>
44 1.14.8.2 nathanw #include <sys/device.h>
45 1.14.8.2 nathanw #include <sys/malloc.h>
46 1.14.8.2 nathanw
47 1.14.8.2 nathanw #include <sys/proc.h> /* tsleep/wakeup */
48 1.14.8.2 nathanw
49 1.14.8.2 nathanw #include <sys/ioctl.h>
50 1.14.8.2 nathanw #include <sys/select.h>
51 1.14.8.2 nathanw #include <sys/file.h>
52 1.14.8.2 nathanw
53 1.14.8.2 nathanw #include <sys/tty.h>
54 1.14.8.2 nathanw #include <sys/conf.h>
55 1.14.8.2 nathanw #include <dev/cons.h> /* consdev */
56 1.14.8.2 nathanw
57 1.14.8.2 nathanw #include <machine/bus.h>
58 1.14.8.2 nathanw #include <machine/config_hook.h>
59 1.14.8.2 nathanw
60 1.14.8.2 nathanw #include <hpcmips/tx/tx39var.h>
61 1.14.8.2 nathanw #include <hpcmips/tx/tx39icureg.h>
62 1.14.8.2 nathanw #include <hpcmips/tx/tx39uartvar.h>
63 1.14.8.2 nathanw #include <hpcmips/tx/tx39uartreg.h>
64 1.14.8.2 nathanw
65 1.14.8.2 nathanw #include <hpcmips/tx/tx39irvar.h>
66 1.14.8.2 nathanw
67 1.14.8.2 nathanw #include <hpcmips/tx/tx39clockreg.h> /* XXX */
68 1.14.8.2 nathanw
69 1.14.8.2 nathanw #define SET(t, f) (t) |= (f)
70 1.14.8.2 nathanw #define CLR(t, f) (t) &= ~(f)
71 1.14.8.2 nathanw #define ISSET(t, f) ((t) & (f))
72 1.14.8.2 nathanw /*
73 1.14.8.2 nathanw * UARTA channel has DTR, DSR, RTS, CTS lines. and they wired to MFIO/IO port.
74 1.14.8.2 nathanw */
75 1.14.8.2 nathanw #define IS_COM0(s) ((s) == 0)
76 1.14.8.2 nathanw #define IS_COM1(s) ((s) == 1)
77 1.14.8.2 nathanw #define ON ((void *)1)
78 1.14.8.2 nathanw #define OFF ((void *)0)
79 1.14.8.2 nathanw
80 1.14.8.2 nathanw #ifdef TX39UART_DEBUG
81 1.14.8.2 nathanw #define DPRINTF_ENABLE
82 1.14.8.2 nathanw #define DPRINTF_DEBUG tx39uart_debug
83 1.14.8.2 nathanw #endif
84 1.14.8.2 nathanw #include <machine/debug.h>
85 1.14.8.2 nathanw
86 1.14.8.2 nathanw #define TXCOM_HW_CONSOLE 0x40
87 1.14.8.2 nathanw #define TXCOM_RING_SIZE 256 /* must be a power of two! */
88 1.14.8.2 nathanw #define TXCOM_RING_MASK (TXCOM_RING_SIZE - 1)
89 1.14.8.2 nathanw
90 1.14.8.2 nathanw struct txcom_chip {
91 1.14.8.2 nathanw tx_chipset_tag_t sc_tc;
92 1.14.8.2 nathanw int sc_slot; /* UARTA or UARTB */
93 1.14.8.2 nathanw int sc_cflag;
94 1.14.8.2 nathanw int sc_speed;
95 1.14.8.2 nathanw int sc_swflags;
96 1.14.8.2 nathanw int sc_hwflags;
97 1.14.8.2 nathanw
98 1.14.8.2 nathanw int sc_dcd;
99 1.14.8.2 nathanw int sc_msr_cts;
100 1.14.8.2 nathanw int sc_tx_stopped;
101 1.14.8.2 nathanw };
102 1.14.8.2 nathanw
103 1.14.8.2 nathanw struct txcom_softc {
104 1.14.8.2 nathanw struct device sc_dev;
105 1.14.8.2 nathanw struct tty *sc_tty;
106 1.14.8.2 nathanw struct txcom_chip *sc_chip;
107 1.14.8.2 nathanw
108 1.14.8.2 nathanw struct callout sc_txsoft_ch;
109 1.14.8.2 nathanw struct callout sc_rxsoft_ch;
110 1.14.8.2 nathanw
111 1.14.8.2 nathanw u_int8_t *sc_tba; /* transmit buffer address */
112 1.14.8.2 nathanw int sc_tbc; /* transmit byte count */
113 1.14.8.2 nathanw int sc_heldtbc;
114 1.14.8.2 nathanw u_int8_t *sc_rbuf; /* receive buffer address */
115 1.14.8.2 nathanw int sc_rbput; /* receive byte count */
116 1.14.8.2 nathanw int sc_rbget;
117 1.14.8.2 nathanw };
118 1.14.8.2 nathanw
119 1.14.8.2 nathanw extern struct cfdriver txcom_cd;
120 1.14.8.2 nathanw
121 1.14.8.2 nathanw int txcom_match(struct device *, struct cfdata *, void *);
122 1.14.8.2 nathanw void txcom_attach(struct device *, struct device *, void *);
123 1.14.8.2 nathanw int txcom_print(void*, const char *);
124 1.14.8.2 nathanw
125 1.14.8.2 nathanw int txcom_txintr(void *);
126 1.14.8.2 nathanw int txcom_rxintr(void *);
127 1.14.8.2 nathanw int txcom_frameerr_intr(void *);
128 1.14.8.2 nathanw int txcom_parityerr_intr(void *);
129 1.14.8.2 nathanw int txcom_break_intr(void *);
130 1.14.8.2 nathanw
131 1.14.8.2 nathanw void txcom_rxsoft(void *);
132 1.14.8.2 nathanw void txcom_txsoft(void *);
133 1.14.8.2 nathanw
134 1.14.8.2 nathanw int txcom_stsoft(void *);
135 1.14.8.2 nathanw int txcom_stsoft2(void *);
136 1.14.8.2 nathanw int txcom_stsoft3(void *);
137 1.14.8.2 nathanw int txcom_stsoft4(void *);
138 1.14.8.2 nathanw
139 1.14.8.2 nathanw
140 1.14.8.2 nathanw void txcom_shutdown(struct txcom_softc *);
141 1.14.8.2 nathanw void txcom_break(struct txcom_softc *, int);
142 1.14.8.2 nathanw void txcom_modem(struct txcom_softc *, int);
143 1.14.8.2 nathanw void txcomstart(struct tty *);
144 1.14.8.2 nathanw int txcomparam(struct tty *, struct termios *);
145 1.14.8.2 nathanw
146 1.14.8.2 nathanw void txcom_reset (struct txcom_chip *);
147 1.14.8.2 nathanw int txcom_enable (struct txcom_chip *);
148 1.14.8.2 nathanw void txcom_disable (struct txcom_chip *);
149 1.14.8.2 nathanw void txcom_setmode (struct txcom_chip *);
150 1.14.8.2 nathanw void txcom_setbaudrate(struct txcom_chip *);
151 1.14.8.2 nathanw int txcom_cngetc (dev_t);
152 1.14.8.2 nathanw void txcom_cnputc (dev_t, int);
153 1.14.8.2 nathanw void txcom_cnpollc (dev_t, int);
154 1.14.8.2 nathanw
155 1.14.8.2 nathanw int txcom_dcd_hook(void *, int, long, void *);
156 1.14.8.2 nathanw int txcom_cts_hook(void *, int, long, void *);
157 1.14.8.2 nathanw
158 1.14.8.2 nathanw
159 1.14.8.2 nathanw __inline__ int __txcom_txbufready(struct txcom_chip *, int);
160 1.14.8.2 nathanw const char *__txcom_slotname(int);
161 1.14.8.2 nathanw
162 1.14.8.2 nathanw #ifdef TX39UARTDEBUG
163 1.14.8.2 nathanw void txcom_dump(struct txcom_chip *);
164 1.14.8.2 nathanw #endif
165 1.14.8.2 nathanw
166 1.14.8.2 nathanw struct consdev txcomcons = {
167 1.14.8.2 nathanw NULL, NULL, txcom_cngetc, txcom_cnputc, txcom_cnpollc,
168 1.14.8.2 nathanw NULL, NODEV, CN_NORMAL
169 1.14.8.2 nathanw };
170 1.14.8.2 nathanw
171 1.14.8.2 nathanw /* Serial console */
172 1.14.8.2 nathanw struct txcom_chip txcom_chip;
173 1.14.8.2 nathanw
174 1.14.8.5 nathanw CFATTACH_DECL(txcom, sizeof(struct txcom_softc),
175 1.14.8.5 nathanw txcom_match, txcom_attach, NULL, NULL);
176 1.14.8.2 nathanw
177 1.14.8.4 nathanw dev_type_open(txcomopen);
178 1.14.8.4 nathanw dev_type_close(txcomclose);
179 1.14.8.4 nathanw dev_type_read(txcomread);
180 1.14.8.4 nathanw dev_type_write(txcomwrite);
181 1.14.8.4 nathanw dev_type_ioctl(txcomioctl);
182 1.14.8.4 nathanw dev_type_stop(txcomstop);
183 1.14.8.4 nathanw dev_type_tty(txcomtty);
184 1.14.8.4 nathanw dev_type_poll(txcompoll);
185 1.14.8.4 nathanw
186 1.14.8.4 nathanw const struct cdevsw txcom_cdevsw = {
187 1.14.8.4 nathanw txcomopen, txcomclose, txcomread, txcomwrite, txcomioctl,
188 1.14.8.4 nathanw txcomstop, txcomtty, txcompoll, nommap, D_TTY
189 1.14.8.4 nathanw };
190 1.14.8.4 nathanw
191 1.14.8.2 nathanw int
192 1.14.8.2 nathanw txcom_match(parent, cf, aux)
193 1.14.8.2 nathanw struct device *parent;
194 1.14.8.2 nathanw struct cfdata *cf;
195 1.14.8.2 nathanw void *aux;
196 1.14.8.2 nathanw {
197 1.14.8.2 nathanw /* if the autoconfiguration got this far, there's a slot here */
198 1.14.8.2 nathanw return 1;
199 1.14.8.2 nathanw }
200 1.14.8.2 nathanw
201 1.14.8.2 nathanw void
202 1.14.8.2 nathanw txcom_attach(struct device *parent, struct device *self, void *aux)
203 1.14.8.2 nathanw {
204 1.14.8.2 nathanw struct tx39uart_attach_args *ua = aux;
205 1.14.8.2 nathanw struct txcom_softc *sc = (void*)self;
206 1.14.8.2 nathanw tx_chipset_tag_t tc;
207 1.14.8.2 nathanw struct tty *tp;
208 1.14.8.2 nathanw struct txcom_chip *chip;
209 1.14.8.2 nathanw int slot, console;
210 1.14.8.2 nathanw
211 1.14.8.2 nathanw /* Check this slot used as serial console */
212 1.14.8.2 nathanw console = (ua->ua_slot == txcom_chip.sc_slot) &&
213 1.14.8.2 nathanw (txcom_chip.sc_hwflags & TXCOM_HW_CONSOLE);
214 1.14.8.2 nathanw
215 1.14.8.2 nathanw if (console) {
216 1.14.8.2 nathanw sc->sc_chip = &txcom_chip;
217 1.14.8.2 nathanw } else {
218 1.14.8.2 nathanw if (!(sc->sc_chip = malloc(sizeof(struct txcom_chip),
219 1.14.8.2 nathanw M_DEVBUF, M_WAITOK))) {
220 1.14.8.2 nathanw printf(": can't allocate chip\n");
221 1.14.8.2 nathanw return;
222 1.14.8.2 nathanw }
223 1.14.8.2 nathanw memset(sc->sc_chip, 0, sizeof(struct txcom_chip));
224 1.14.8.2 nathanw }
225 1.14.8.2 nathanw
226 1.14.8.2 nathanw chip = sc->sc_chip;
227 1.14.8.2 nathanw tc = chip->sc_tc = ua->ua_tc;
228 1.14.8.2 nathanw slot = chip->sc_slot = ua->ua_slot;
229 1.14.8.2 nathanw
230 1.14.8.2 nathanw #ifdef TX39UARTDEBUG
231 1.14.8.2 nathanw txcom_dump(chip);
232 1.14.8.2 nathanw #endif
233 1.14.8.2 nathanw if (!console)
234 1.14.8.2 nathanw txcom_reset(chip);
235 1.14.8.2 nathanw
236 1.14.8.2 nathanw if (!(sc->sc_rbuf = malloc(TXCOM_RING_SIZE, M_DEVBUF, M_WAITOK))) {
237 1.14.8.2 nathanw printf(": can't allocate buffer.\n");
238 1.14.8.2 nathanw return;
239 1.14.8.2 nathanw }
240 1.14.8.2 nathanw memset(sc->sc_rbuf, 0, TXCOM_RING_SIZE);
241 1.14.8.2 nathanw
242 1.14.8.2 nathanw tp = ttymalloc();
243 1.14.8.2 nathanw tp->t_oproc = txcomstart;
244 1.14.8.2 nathanw tp->t_param = txcomparam;
245 1.14.8.2 nathanw tp->t_hwiflow = NULL;
246 1.14.8.2 nathanw sc->sc_tty = tp;
247 1.14.8.2 nathanw tty_attach(tp);
248 1.14.8.2 nathanw
249 1.14.8.2 nathanw if (ISSET(chip->sc_hwflags, TXCOM_HW_CONSOLE)) {
250 1.14.8.2 nathanw int maj;
251 1.14.8.2 nathanw /* locate the major number */
252 1.14.8.4 nathanw maj = cdevsw_lookup_major(&txcom_cdevsw);
253 1.14.8.2 nathanw
254 1.14.8.2 nathanw cn_tab->cn_dev = makedev(maj, sc->sc_dev.dv_unit);
255 1.14.8.2 nathanw
256 1.14.8.2 nathanw printf(": console");
257 1.14.8.2 nathanw }
258 1.14.8.2 nathanw
259 1.14.8.2 nathanw printf("\n");
260 1.14.8.2 nathanw
261 1.14.8.2 nathanw /*
262 1.14.8.2 nathanw * Enable interrupt
263 1.14.8.2 nathanw */
264 1.14.8.2 nathanw #define TXCOMINTR(i, s) MAKEINTR(2, TX39_INTRSTATUS2_UART##i##INT(s))
265 1.14.8.2 nathanw
266 1.14.8.2 nathanw tx_intr_establish(tc, TXCOMINTR(RX, slot), IST_EDGE, IPL_TTY,
267 1.14.8.2 nathanw txcom_rxintr, sc);
268 1.14.8.2 nathanw tx_intr_establish(tc, TXCOMINTR(TX, slot), IST_EDGE, IPL_TTY,
269 1.14.8.2 nathanw txcom_txintr, sc);
270 1.14.8.2 nathanw tx_intr_establish(tc, TXCOMINTR(RXOVERRUN, slot), IST_EDGE, IPL_TTY,
271 1.14.8.2 nathanw txcom_rxintr, sc);
272 1.14.8.2 nathanw tx_intr_establish(tc, TXCOMINTR(TXOVERRUN, slot), IST_EDGE, IPL_TTY,
273 1.14.8.2 nathanw txcom_txintr, sc);
274 1.14.8.2 nathanw tx_intr_establish(tc, TXCOMINTR(FRAMEERR, slot), IST_EDGE, IPL_TTY,
275 1.14.8.2 nathanw txcom_frameerr_intr, sc);
276 1.14.8.2 nathanw tx_intr_establish(tc, TXCOMINTR(PARITYERR, slot), IST_EDGE, IPL_TTY,
277 1.14.8.2 nathanw txcom_parityerr_intr, sc);
278 1.14.8.2 nathanw tx_intr_establish(tc, TXCOMINTR(BREAK, slot), IST_EDGE, IPL_TTY,
279 1.14.8.2 nathanw txcom_break_intr, sc);
280 1.14.8.2 nathanw
281 1.14.8.2 nathanw /*
282 1.14.8.2 nathanw * UARTA has external signal line. (its wiring is platform dependent)
283 1.14.8.2 nathanw */
284 1.14.8.2 nathanw if (IS_COM0(slot)) {
285 1.14.8.2 nathanw /* install DCD, CTS hooks. */
286 1.14.8.2 nathanw config_hook(CONFIG_HOOK_EVENT, CONFIG_HOOK_COM0_DCD,
287 1.14.8.2 nathanw CONFIG_HOOK_EXCLUSIVE, txcom_dcd_hook, sc);
288 1.14.8.2 nathanw config_hook(CONFIG_HOOK_EVENT, CONFIG_HOOK_COM0_CTS,
289 1.14.8.2 nathanw CONFIG_HOOK_EXCLUSIVE, txcom_cts_hook, sc);
290 1.14.8.2 nathanw }
291 1.14.8.2 nathanw
292 1.14.8.2 nathanw /*
293 1.14.8.2 nathanw * UARTB can connect IR module
294 1.14.8.2 nathanw */
295 1.14.8.2 nathanw if (IS_COM1(slot)) {
296 1.14.8.2 nathanw struct txcom_attach_args tca;
297 1.14.8.2 nathanw tca.tca_tc = tc;
298 1.14.8.2 nathanw tca.tca_parent = self;
299 1.14.8.2 nathanw config_found(self, &tca, txcom_print);
300 1.14.8.2 nathanw }
301 1.14.8.2 nathanw }
302 1.14.8.2 nathanw
303 1.14.8.2 nathanw int
304 1.14.8.2 nathanw txcom_print(void *aux, const char *pnp)
305 1.14.8.2 nathanw {
306 1.14.8.2 nathanw return pnp ? QUIET : UNCONF;
307 1.14.8.2 nathanw }
308 1.14.8.2 nathanw
309 1.14.8.2 nathanw void
310 1.14.8.2 nathanw txcom_reset(struct txcom_chip *chip)
311 1.14.8.2 nathanw {
312 1.14.8.2 nathanw tx_chipset_tag_t tc;
313 1.14.8.2 nathanw int slot, ofs;
314 1.14.8.2 nathanw txreg_t reg;
315 1.14.8.2 nathanw
316 1.14.8.2 nathanw tc = chip->sc_tc;
317 1.14.8.2 nathanw slot = chip->sc_slot;
318 1.14.8.2 nathanw ofs = TX39_UARTCTRL1_REG(slot);
319 1.14.8.2 nathanw
320 1.14.8.2 nathanw /* Supply clock */
321 1.14.8.2 nathanw reg = tx_conf_read(tc, TX39_CLOCKCTRL_REG);
322 1.14.8.2 nathanw reg |= (slot ? TX39_CLOCK_ENUARTBCLK : TX39_CLOCK_ENUARTACLK);
323 1.14.8.2 nathanw tx_conf_write(tc, TX39_CLOCKCTRL_REG, reg);
324 1.14.8.2 nathanw
325 1.14.8.2 nathanw /* reset UART module */
326 1.14.8.2 nathanw tx_conf_write(tc, ofs, 0);
327 1.14.8.2 nathanw }
328 1.14.8.2 nathanw
329 1.14.8.2 nathanw int
330 1.14.8.2 nathanw txcom_enable(struct txcom_chip *chip)
331 1.14.8.2 nathanw {
332 1.14.8.2 nathanw tx_chipset_tag_t tc;
333 1.14.8.2 nathanw txreg_t reg;
334 1.14.8.2 nathanw int slot, ofs, timeout;
335 1.14.8.2 nathanw
336 1.14.8.2 nathanw tc = chip->sc_tc;
337 1.14.8.2 nathanw slot = chip->sc_slot;
338 1.14.8.2 nathanw ofs = TX39_UARTCTRL1_REG(slot);
339 1.14.8.2 nathanw
340 1.14.8.2 nathanw /* External power supply (if any) */
341 1.14.8.2 nathanw config_hook_call(CONFIG_HOOK_POWERCONTROL,
342 1.14.8.2 nathanw CONFIG_HOOK_POWERCONTROL_COM0, PWCTL_ON);
343 1.14.8.2 nathanw delay(3);
344 1.14.8.2 nathanw
345 1.14.8.2 nathanw /* Supply clock */
346 1.14.8.2 nathanw reg = tx_conf_read(tc, TX39_CLOCKCTRL_REG);
347 1.14.8.2 nathanw reg |= (slot ? TX39_CLOCK_ENUARTBCLK : TX39_CLOCK_ENUARTACLK);
348 1.14.8.2 nathanw tx_conf_write(tc, TX39_CLOCKCTRL_REG, reg);
349 1.14.8.2 nathanw
350 1.14.8.2 nathanw /*
351 1.14.8.2 nathanw * XXX Disable DMA (DMA not coded yet)
352 1.14.8.2 nathanw */
353 1.14.8.2 nathanw reg = tx_conf_read(tc, ofs);
354 1.14.8.2 nathanw reg &= ~(TX39_UARTCTRL1_ENDMARX | TX39_UARTCTRL1_ENDMATX);
355 1.14.8.2 nathanw tx_conf_write(tc, ofs, reg);
356 1.14.8.2 nathanw
357 1.14.8.2 nathanw /* enable */
358 1.14.8.2 nathanw reg = tx_conf_read(tc, ofs);
359 1.14.8.2 nathanw reg |= TX39_UARTCTRL1_ENUART;
360 1.14.8.2 nathanw reg &= ~TX39_UARTCTRL1_ENBREAHALT;
361 1.14.8.2 nathanw tx_conf_write(tc, ofs, reg);
362 1.14.8.2 nathanw
363 1.14.8.2 nathanw timeout = 100000;
364 1.14.8.2 nathanw
365 1.14.8.2 nathanw while(!(tx_conf_read(tc, ofs) & TX39_UARTCTRL1_UARTON) &&
366 1.14.8.2 nathanw --timeout > 0)
367 1.14.8.2 nathanw ;
368 1.14.8.2 nathanw
369 1.14.8.2 nathanw if (timeout == 0 && !cold) {
370 1.14.8.2 nathanw printf("%s never power up\n", __txcom_slotname(slot));
371 1.14.8.2 nathanw return 1;
372 1.14.8.2 nathanw }
373 1.14.8.2 nathanw
374 1.14.8.2 nathanw return 0;
375 1.14.8.2 nathanw }
376 1.14.8.2 nathanw
377 1.14.8.2 nathanw void
378 1.14.8.2 nathanw txcom_disable(struct txcom_chip *chip)
379 1.14.8.2 nathanw {
380 1.14.8.2 nathanw tx_chipset_tag_t tc;
381 1.14.8.2 nathanw txreg_t reg;
382 1.14.8.2 nathanw int slot;
383 1.14.8.2 nathanw
384 1.14.8.2 nathanw tc = chip->sc_tc;
385 1.14.8.2 nathanw slot = chip->sc_slot;
386 1.14.8.2 nathanw
387 1.14.8.2 nathanw reg = tx_conf_read(tc, TX39_UARTCTRL1_REG(slot));
388 1.14.8.2 nathanw /* DMA */
389 1.14.8.2 nathanw reg &= ~(TX39_UARTCTRL1_ENDMARX | TX39_UARTCTRL1_ENDMATX);
390 1.14.8.2 nathanw
391 1.14.8.2 nathanw /* disable module */
392 1.14.8.2 nathanw reg &= ~TX39_UARTCTRL1_ENUART;
393 1.14.8.2 nathanw tx_conf_write(tc, TX39_UARTCTRL1_REG(slot), reg);
394 1.14.8.2 nathanw
395 1.14.8.2 nathanw /* Clock */
396 1.14.8.2 nathanw reg = tx_conf_read(tc, TX39_CLOCKCTRL_REG);
397 1.14.8.2 nathanw reg &= ~(slot ? TX39_CLOCK_ENUARTBCLK : TX39_CLOCK_ENUARTACLK);
398 1.14.8.2 nathanw tx_conf_write(tc, TX39_CLOCKCTRL_REG, reg);
399 1.14.8.2 nathanw
400 1.14.8.2 nathanw }
401 1.14.8.2 nathanw
402 1.14.8.2 nathanw __inline__ int
403 1.14.8.2 nathanw __txcom_txbufready(struct txcom_chip *chip, int retry)
404 1.14.8.2 nathanw {
405 1.14.8.2 nathanw tx_chipset_tag_t tc = chip->sc_tc;
406 1.14.8.2 nathanw int ofs = TX39_UARTCTRL1_REG(chip->sc_slot);
407 1.14.8.2 nathanw
408 1.14.8.2 nathanw do {
409 1.14.8.2 nathanw if (tx_conf_read(tc, ofs) & TX39_UARTCTRL1_EMPTY)
410 1.14.8.2 nathanw return 1;
411 1.14.8.2 nathanw } while(--retry != 0);
412 1.14.8.2 nathanw
413 1.14.8.2 nathanw return 0;
414 1.14.8.2 nathanw }
415 1.14.8.2 nathanw
416 1.14.8.2 nathanw void
417 1.14.8.2 nathanw txcom_pulse_mode(struct device *dev)
418 1.14.8.2 nathanw {
419 1.14.8.2 nathanw struct txcom_softc *sc = (void*)dev;
420 1.14.8.2 nathanw struct txcom_chip *chip = sc->sc_chip;
421 1.14.8.2 nathanw tx_chipset_tag_t tc = chip->sc_tc;
422 1.14.8.2 nathanw int ofs;
423 1.14.8.2 nathanw txreg_t reg;
424 1.14.8.2 nathanw
425 1.14.8.2 nathanw ofs = TX39_UARTCTRL1_REG(chip->sc_slot);
426 1.14.8.2 nathanw
427 1.14.8.2 nathanw reg = tx_conf_read(tc, ofs);
428 1.14.8.2 nathanw /* WindowsCE use this setting */
429 1.14.8.2 nathanw reg |= TX39_UARTCTRL1_PULSEOPT1;
430 1.14.8.2 nathanw reg &= ~TX39_UARTCTRL1_PULSEOPT2;
431 1.14.8.2 nathanw reg |= TX39_UARTCTRL1_DTINVERT;
432 1.14.8.2 nathanw
433 1.14.8.2 nathanw tx_conf_write(tc, ofs, reg);
434 1.14.8.2 nathanw }
435 1.14.8.2 nathanw
436 1.14.8.2 nathanw /*
437 1.14.8.2 nathanw * console
438 1.14.8.2 nathanw */
439 1.14.8.2 nathanw int
440 1.14.8.2 nathanw txcom_cngetc(dev_t dev)
441 1.14.8.2 nathanw {
442 1.14.8.2 nathanw tx_chipset_tag_t tc;
443 1.14.8.2 nathanw int ofs, c, s;
444 1.14.8.2 nathanw
445 1.14.8.2 nathanw s = spltty();
446 1.14.8.2 nathanw
447 1.14.8.2 nathanw tc = txcom_chip.sc_tc;
448 1.14.8.2 nathanw ofs = TX39_UARTCTRL1_REG(txcom_chip.sc_slot);
449 1.14.8.2 nathanw
450 1.14.8.2 nathanw while(!(TX39_UARTCTRL1_RXHOLDFULL & tx_conf_read(tc, ofs)))
451 1.14.8.2 nathanw ;
452 1.14.8.2 nathanw
453 1.14.8.2 nathanw c = TX39_UARTRXHOLD_RXDATA(
454 1.14.8.2 nathanw tx_conf_read(tc, TX39_UARTRXHOLD_REG(txcom_chip.sc_slot)));
455 1.14.8.2 nathanw
456 1.14.8.2 nathanw if (c == '\r')
457 1.14.8.2 nathanw c = '\n';
458 1.14.8.2 nathanw
459 1.14.8.2 nathanw splx(s);
460 1.14.8.2 nathanw
461 1.14.8.2 nathanw return c;
462 1.14.8.2 nathanw }
463 1.14.8.2 nathanw
464 1.14.8.2 nathanw void
465 1.14.8.2 nathanw txcom_cnputc(dev_t dev, int c)
466 1.14.8.2 nathanw {
467 1.14.8.2 nathanw struct txcom_chip *chip = &txcom_chip;
468 1.14.8.2 nathanw tx_chipset_tag_t tc = chip->sc_tc;
469 1.14.8.2 nathanw int s;
470 1.14.8.2 nathanw
471 1.14.8.2 nathanw s = spltty();
472 1.14.8.2 nathanw
473 1.14.8.2 nathanw /* Wait for transmitter to empty */
474 1.14.8.2 nathanw __txcom_txbufready(chip, -1);
475 1.14.8.2 nathanw
476 1.14.8.2 nathanw tx_conf_write(tc, TX39_UARTTXHOLD_REG(chip->sc_slot),
477 1.14.8.2 nathanw (c & TX39_UARTTXHOLD_TXDATA_MASK));
478 1.14.8.2 nathanw
479 1.14.8.2 nathanw __txcom_txbufready(chip, -1);
480 1.14.8.2 nathanw
481 1.14.8.2 nathanw splx(s);
482 1.14.8.2 nathanw }
483 1.14.8.2 nathanw
484 1.14.8.2 nathanw void
485 1.14.8.2 nathanw txcom_cnpollc(dev_t dev, int on)
486 1.14.8.2 nathanw {
487 1.14.8.2 nathanw }
488 1.14.8.2 nathanw
489 1.14.8.2 nathanw void
490 1.14.8.2 nathanw txcom_setmode(struct txcom_chip *chip)
491 1.14.8.2 nathanw {
492 1.14.8.2 nathanw tcflag_t cflag = chip->sc_cflag;
493 1.14.8.2 nathanw int ofs = TX39_UARTCTRL1_REG(chip->sc_slot);
494 1.14.8.2 nathanw txreg_t reg;
495 1.14.8.2 nathanw
496 1.14.8.2 nathanw reg = tx_conf_read(chip->sc_tc, ofs);
497 1.14.8.2 nathanw reg &= ~TX39_UARTCTRL1_ENUART;
498 1.14.8.2 nathanw tx_conf_write(chip->sc_tc, ofs, reg);
499 1.14.8.2 nathanw
500 1.14.8.2 nathanw switch (ISSET(cflag, CSIZE)) {
501 1.14.8.2 nathanw default:
502 1.14.8.2 nathanw printf("txcom_setmode: CS7, CS8 only. use CS7");
503 1.14.8.2 nathanw /* FALL THROUGH */
504 1.14.8.2 nathanw case CS7:
505 1.14.8.2 nathanw reg |= TX39_UARTCTRL1_BIT7;
506 1.14.8.2 nathanw break;
507 1.14.8.2 nathanw case CS8:
508 1.14.8.2 nathanw reg &= ~TX39_UARTCTRL1_BIT7;
509 1.14.8.2 nathanw break;
510 1.14.8.2 nathanw }
511 1.14.8.2 nathanw
512 1.14.8.2 nathanw if (ISSET(cflag, PARENB)) {
513 1.14.8.2 nathanw reg |= TX39_UARTCTRL1_ENPARITY;
514 1.14.8.2 nathanw if (ISSET(cflag, PARODD)) {
515 1.14.8.2 nathanw reg &= ~TX39_UARTCTRL1_EVENPARITY;
516 1.14.8.2 nathanw } else {
517 1.14.8.2 nathanw reg |= TX39_UARTCTRL1_EVENPARITY;
518 1.14.8.2 nathanw }
519 1.14.8.2 nathanw } else {
520 1.14.8.2 nathanw reg &= ~TX39_UARTCTRL1_ENPARITY;
521 1.14.8.2 nathanw }
522 1.14.8.2 nathanw
523 1.14.8.2 nathanw if (ISSET(cflag, CSTOPB))
524 1.14.8.2 nathanw reg |= TX39_UARTCTRL1_TWOSTOP;
525 1.14.8.2 nathanw else
526 1.14.8.2 nathanw reg &= ~TX39_UARTCTRL1_TWOSTOP;
527 1.14.8.2 nathanw
528 1.14.8.2 nathanw reg |= TX39_UARTCTRL1_ENUART;
529 1.14.8.2 nathanw tx_conf_write(chip->sc_tc, ofs, reg);
530 1.14.8.2 nathanw }
531 1.14.8.2 nathanw
532 1.14.8.2 nathanw void
533 1.14.8.2 nathanw txcom_setbaudrate(struct txcom_chip *chip)
534 1.14.8.2 nathanw {
535 1.14.8.2 nathanw int baudrate;
536 1.14.8.2 nathanw int ofs = TX39_UARTCTRL1_REG(chip->sc_slot);
537 1.14.8.2 nathanw txreg_t reg, reg1;
538 1.14.8.2 nathanw
539 1.14.8.2 nathanw if (chip->sc_speed == 0)
540 1.14.8.2 nathanw return;
541 1.14.8.2 nathanw
542 1.14.8.2 nathanw if (!cold)
543 1.14.8.2 nathanw DPRINTF("%d\n", chip->sc_speed);
544 1.14.8.2 nathanw
545 1.14.8.2 nathanw reg1 = tx_conf_read(chip->sc_tc, ofs);
546 1.14.8.2 nathanw reg1 &= ~TX39_UARTCTRL1_ENUART;
547 1.14.8.2 nathanw tx_conf_write(chip->sc_tc, ofs, reg1);
548 1.14.8.2 nathanw
549 1.14.8.2 nathanw baudrate = TX39_UARTCLOCKHZ / (chip->sc_speed * 16) - 1;
550 1.14.8.2 nathanw reg = TX39_UARTCTRL2_BAUDRATE_SET(0, baudrate);
551 1.14.8.2 nathanw
552 1.14.8.2 nathanw tx_conf_write(chip->sc_tc, TX39_UARTCTRL2_REG(chip->sc_slot), reg);
553 1.14.8.2 nathanw
554 1.14.8.2 nathanw reg1 |= TX39_UARTCTRL1_ENUART;
555 1.14.8.2 nathanw tx_conf_write(chip->sc_tc, ofs, reg1);
556 1.14.8.2 nathanw }
557 1.14.8.2 nathanw
558 1.14.8.2 nathanw int
559 1.14.8.2 nathanw txcom_cnattach(int slot, int speed, int cflag)
560 1.14.8.2 nathanw {
561 1.14.8.2 nathanw cn_tab = &txcomcons;
562 1.14.8.2 nathanw
563 1.14.8.2 nathanw txcom_chip.sc_tc = tx_conf_get_tag();
564 1.14.8.2 nathanw txcom_chip.sc_slot = slot;
565 1.14.8.2 nathanw txcom_chip.sc_cflag = cflag;
566 1.14.8.2 nathanw txcom_chip.sc_speed = speed;
567 1.14.8.2 nathanw txcom_chip.sc_hwflags |= TXCOM_HW_CONSOLE;
568 1.14.8.2 nathanw #if notyet
569 1.14.8.2 nathanw txcom_reset(&txcom_chip);
570 1.14.8.2 nathanw #endif
571 1.14.8.2 nathanw txcom_setmode(&txcom_chip);
572 1.14.8.2 nathanw txcom_setbaudrate(&txcom_chip);
573 1.14.8.2 nathanw
574 1.14.8.2 nathanw if (txcom_enable(&txcom_chip))
575 1.14.8.2 nathanw return 1;
576 1.14.8.2 nathanw
577 1.14.8.2 nathanw return 0;
578 1.14.8.2 nathanw }
579 1.14.8.2 nathanw
580 1.14.8.2 nathanw /*
581 1.14.8.2 nathanw * tty
582 1.14.8.2 nathanw */
583 1.14.8.2 nathanw void
584 1.14.8.2 nathanw txcom_break(struct txcom_softc *sc, int on)
585 1.14.8.2 nathanw {
586 1.14.8.2 nathanw struct txcom_chip *chip = sc->sc_chip;
587 1.14.8.2 nathanw
588 1.14.8.2 nathanw tx_conf_write(chip->sc_tc, TX39_UARTTXHOLD_REG(chip->sc_slot),
589 1.14.8.2 nathanw on ? TX39_UARTTXHOLD_BREAK : 0);
590 1.14.8.2 nathanw }
591 1.14.8.2 nathanw
592 1.14.8.2 nathanw void
593 1.14.8.2 nathanw txcom_modem(struct txcom_softc *sc, int on)
594 1.14.8.2 nathanw {
595 1.14.8.2 nathanw struct txcom_chip *chip = sc->sc_chip;
596 1.14.8.2 nathanw tx_chipset_tag_t tc = chip->sc_tc;
597 1.14.8.2 nathanw int slot = chip->sc_slot;
598 1.14.8.2 nathanw txreg_t reg;
599 1.14.8.2 nathanw
600 1.14.8.2 nathanw /* assert DTR */
601 1.14.8.2 nathanw if (IS_COM0(slot)) {
602 1.14.8.2 nathanw config_hook_call(CONFIG_HOOK_SET,
603 1.14.8.2 nathanw CONFIG_HOOK_COM0_DTR,
604 1.14.8.2 nathanw (void *)on);
605 1.14.8.2 nathanw }
606 1.14.8.2 nathanw
607 1.14.8.2 nathanw reg = tx_conf_read(tc, TX39_UARTCTRL1_REG(slot));
608 1.14.8.2 nathanw reg &= ~TX39_UARTCTRL1_ENUART;
609 1.14.8.2 nathanw tx_conf_write(tc, TX39_UARTCTRL1_REG(slot), reg);
610 1.14.8.2 nathanw
611 1.14.8.2 nathanw if (on) {
612 1.14.8.2 nathanw reg &= ~TX39_UARTCTRL1_DISTXD;
613 1.14.8.2 nathanw } else {
614 1.14.8.2 nathanw reg |= TX39_UARTCTRL1_DISTXD; /* low UARTTXD */
615 1.14.8.2 nathanw }
616 1.14.8.2 nathanw
617 1.14.8.2 nathanw reg |= TX39_UARTCTRL1_ENUART;
618 1.14.8.2 nathanw tx_conf_write(tc, TX39_UARTCTRL1_REG(slot), reg);
619 1.14.8.2 nathanw }
620 1.14.8.2 nathanw
621 1.14.8.2 nathanw void
622 1.14.8.2 nathanw txcom_shutdown(struct txcom_softc *sc)
623 1.14.8.2 nathanw {
624 1.14.8.2 nathanw struct tty *tp = sc->sc_tty;
625 1.14.8.2 nathanw int s = spltty();
626 1.14.8.2 nathanw
627 1.14.8.2 nathanw /* Clear any break condition set with TIOCSBRK. */
628 1.14.8.2 nathanw txcom_break(sc, 0);
629 1.14.8.2 nathanw
630 1.14.8.2 nathanw /*
631 1.14.8.2 nathanw * Hang up if necessary. Wait a bit, so the other side has time to
632 1.14.8.2 nathanw * notice even if we immediately open the port again.
633 1.14.8.2 nathanw */
634 1.14.8.2 nathanw if (ISSET(tp->t_cflag, HUPCL)) {
635 1.14.8.2 nathanw txcom_modem(sc, 0);
636 1.14.8.2 nathanw (void) tsleep(sc, TTIPRI, ttclos, hz);
637 1.14.8.2 nathanw }
638 1.14.8.2 nathanw
639 1.14.8.2 nathanw
640 1.14.8.2 nathanw /* Turn off interrupts if not the console. */
641 1.14.8.2 nathanw if (!ISSET(sc->sc_chip->sc_hwflags, TXCOM_HW_CONSOLE)) {
642 1.14.8.2 nathanw txcom_disable(sc->sc_chip);
643 1.14.8.2 nathanw }
644 1.14.8.2 nathanw
645 1.14.8.2 nathanw splx(s);
646 1.14.8.2 nathanw }
647 1.14.8.2 nathanw
648 1.14.8.2 nathanw const char *
649 1.14.8.2 nathanw __txcom_slotname(int slot)
650 1.14.8.2 nathanw {
651 1.14.8.2 nathanw static const char *slotname[] = {"UARTA", "UARTB", "unknown"};
652 1.14.8.2 nathanw
653 1.14.8.2 nathanw if (slot != 0 && slot != 1)
654 1.14.8.2 nathanw return slotname[2];
655 1.14.8.2 nathanw
656 1.14.8.2 nathanw return slotname[slot];
657 1.14.8.2 nathanw }
658 1.14.8.2 nathanw
659 1.14.8.2 nathanw int
660 1.14.8.2 nathanw txcom_frameerr_intr(void *arg)
661 1.14.8.2 nathanw {
662 1.14.8.2 nathanw struct txcom_softc *sc = arg;
663 1.14.8.2 nathanw
664 1.14.8.2 nathanw printf("%s frame error\n", __txcom_slotname(sc->sc_chip->sc_slot));
665 1.14.8.2 nathanw
666 1.14.8.2 nathanw return 0;
667 1.14.8.2 nathanw }
668 1.14.8.2 nathanw
669 1.14.8.2 nathanw int
670 1.14.8.2 nathanw txcom_parityerr_intr(void *arg)
671 1.14.8.2 nathanw {
672 1.14.8.2 nathanw struct txcom_softc *sc = arg;
673 1.14.8.2 nathanw
674 1.14.8.2 nathanw printf("%s parity error\n", __txcom_slotname(sc->sc_chip->sc_slot));
675 1.14.8.2 nathanw
676 1.14.8.2 nathanw return 0;
677 1.14.8.2 nathanw }
678 1.14.8.2 nathanw
679 1.14.8.2 nathanw int
680 1.14.8.2 nathanw txcom_break_intr(void *arg)
681 1.14.8.2 nathanw {
682 1.14.8.2 nathanw struct txcom_softc *sc = arg;
683 1.14.8.2 nathanw
684 1.14.8.2 nathanw printf("%s break\n", __txcom_slotname(sc->sc_chip->sc_slot));
685 1.14.8.2 nathanw
686 1.14.8.2 nathanw return 0;
687 1.14.8.2 nathanw }
688 1.14.8.2 nathanw
689 1.14.8.2 nathanw int
690 1.14.8.2 nathanw txcom_rxintr(void *arg)
691 1.14.8.2 nathanw {
692 1.14.8.2 nathanw struct txcom_softc *sc = arg;
693 1.14.8.2 nathanw struct txcom_chip *chip = sc->sc_chip;
694 1.14.8.2 nathanw u_int8_t c;
695 1.14.8.2 nathanw
696 1.14.8.2 nathanw c = TX39_UARTRXHOLD_RXDATA(
697 1.14.8.2 nathanw tx_conf_read(chip->sc_tc,
698 1.14.8.2 nathanw TX39_UARTRXHOLD_REG(chip->sc_slot)));
699 1.14.8.2 nathanw
700 1.14.8.2 nathanw sc->sc_rbuf[sc->sc_rbput] = c;
701 1.14.8.2 nathanw sc->sc_rbput = (sc->sc_rbput + 1) % TXCOM_RING_MASK;
702 1.14.8.2 nathanw
703 1.14.8.2 nathanw callout_reset(&sc->sc_rxsoft_ch, 1, txcom_rxsoft, sc);
704 1.14.8.2 nathanw
705 1.14.8.2 nathanw return 0;
706 1.14.8.2 nathanw }
707 1.14.8.2 nathanw
708 1.14.8.2 nathanw void
709 1.14.8.2 nathanw txcom_rxsoft(void *arg)
710 1.14.8.2 nathanw {
711 1.14.8.2 nathanw struct txcom_softc *sc = arg;
712 1.14.8.2 nathanw struct tty *tp = sc->sc_tty;
713 1.14.8.2 nathanw int (*rint)(int, struct tty *);
714 1.14.8.2 nathanw int code;
715 1.14.8.2 nathanw int s, end, get;
716 1.14.8.2 nathanw
717 1.14.8.2 nathanw rint = tp->t_linesw->l_rint;
718 1.14.8.2 nathanw
719 1.14.8.2 nathanw s = spltty();
720 1.14.8.2 nathanw end = sc->sc_rbput;
721 1.14.8.2 nathanw get = sc->sc_rbget;
722 1.14.8.2 nathanw
723 1.14.8.2 nathanw while (get != end) {
724 1.14.8.2 nathanw code = sc->sc_rbuf[get];
725 1.14.8.2 nathanw
726 1.14.8.2 nathanw if ((*rint)(code, tp) == -1) {
727 1.14.8.2 nathanw /*
728 1.14.8.2 nathanw * The line discipline's buffer is out of space.
729 1.14.8.2 nathanw */
730 1.14.8.2 nathanw }
731 1.14.8.2 nathanw get = (get + 1) % TXCOM_RING_MASK;
732 1.14.8.2 nathanw }
733 1.14.8.2 nathanw sc->sc_rbget = get;
734 1.14.8.2 nathanw
735 1.14.8.2 nathanw splx(s);
736 1.14.8.2 nathanw }
737 1.14.8.2 nathanw
738 1.14.8.2 nathanw int
739 1.14.8.2 nathanw txcom_txintr(void *arg)
740 1.14.8.2 nathanw {
741 1.14.8.2 nathanw struct txcom_softc *sc = arg;
742 1.14.8.2 nathanw struct txcom_chip *chip = sc->sc_chip;
743 1.14.8.2 nathanw tx_chipset_tag_t tc = chip->sc_tc;
744 1.14.8.2 nathanw
745 1.14.8.2 nathanw if (sc->sc_tbc > 0) {
746 1.14.8.2 nathanw tx_conf_write(tc, TX39_UARTTXHOLD_REG(chip->sc_slot),
747 1.14.8.2 nathanw (*sc->sc_tba &
748 1.14.8.2 nathanw TX39_UARTTXHOLD_TXDATA_MASK));
749 1.14.8.2 nathanw sc->sc_tbc--;
750 1.14.8.2 nathanw sc->sc_tba++;
751 1.14.8.2 nathanw } else {
752 1.14.8.2 nathanw callout_reset(&sc->sc_rxsoft_ch, 1, txcom_txsoft, sc);
753 1.14.8.2 nathanw }
754 1.14.8.2 nathanw
755 1.14.8.2 nathanw return 0;
756 1.14.8.2 nathanw }
757 1.14.8.2 nathanw
758 1.14.8.2 nathanw void
759 1.14.8.2 nathanw txcom_txsoft(void *arg)
760 1.14.8.2 nathanw {
761 1.14.8.2 nathanw struct txcom_softc *sc = arg;
762 1.14.8.2 nathanw struct tty *tp = sc->sc_tty;
763 1.14.8.2 nathanw int s = spltty();
764 1.14.8.2 nathanw
765 1.14.8.2 nathanw CLR(tp->t_state, TS_BUSY);
766 1.14.8.2 nathanw if (ISSET(tp->t_state, TS_FLUSH)) {
767 1.14.8.2 nathanw CLR(tp->t_state, TS_FLUSH);
768 1.14.8.2 nathanw } else {
769 1.14.8.2 nathanw ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf));
770 1.14.8.2 nathanw }
771 1.14.8.2 nathanw
772 1.14.8.2 nathanw (*tp->t_linesw->l_start)(tp);
773 1.14.8.2 nathanw
774 1.14.8.2 nathanw splx(s);
775 1.14.8.2 nathanw }
776 1.14.8.2 nathanw
777 1.14.8.2 nathanw int
778 1.14.8.2 nathanw txcomopen(dev_t dev, int flag, int mode, struct proc *p)
779 1.14.8.2 nathanw {
780 1.14.8.2 nathanw struct txcom_softc *sc = txcom_cd.cd_devs[minor(dev)];
781 1.14.8.2 nathanw struct txcom_chip *chip;
782 1.14.8.2 nathanw struct tty *tp;
783 1.14.8.2 nathanw int s, err;
784 1.14.8.2 nathanw
785 1.14.8.2 nathanw if (!sc)
786 1.14.8.2 nathanw return ENXIO;
787 1.14.8.2 nathanw
788 1.14.8.2 nathanw chip = sc->sc_chip;
789 1.14.8.2 nathanw tp = sc->sc_tty;
790 1.14.8.2 nathanw
791 1.14.8.2 nathanw if (ISSET(tp->t_state, TS_ISOPEN) &&
792 1.14.8.2 nathanw ISSET(tp->t_state, TS_XCLUDE) &&
793 1.14.8.2 nathanw p->p_ucred->cr_uid != 0)
794 1.14.8.2 nathanw return (EBUSY);
795 1.14.8.2 nathanw
796 1.14.8.2 nathanw s = spltty();
797 1.14.8.2 nathanw
798 1.14.8.2 nathanw if (txcom_enable(sc->sc_chip)) {
799 1.14.8.2 nathanw splx(s);
800 1.14.8.2 nathanw goto out;
801 1.14.8.2 nathanw }
802 1.14.8.2 nathanw /*
803 1.14.8.2 nathanw * Do the following iff this is a first open.
804 1.14.8.2 nathanw */
805 1.14.8.2 nathanw if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) {
806 1.14.8.2 nathanw struct termios t;
807 1.14.8.2 nathanw
808 1.14.8.2 nathanw tp->t_dev = dev;
809 1.14.8.2 nathanw
810 1.14.8.2 nathanw t.c_ispeed = 0;
811 1.14.8.2 nathanw if (ISSET(chip->sc_hwflags, TXCOM_HW_CONSOLE)) {
812 1.14.8.2 nathanw t.c_ospeed = chip->sc_speed;
813 1.14.8.2 nathanw t.c_cflag = chip->sc_cflag;
814 1.14.8.2 nathanw } else {
815 1.14.8.2 nathanw t.c_ospeed = TTYDEF_SPEED;
816 1.14.8.2 nathanw t.c_cflag = TTYDEF_CFLAG;
817 1.14.8.2 nathanw }
818 1.14.8.2 nathanw
819 1.14.8.2 nathanw if (ISSET(chip->sc_swflags, TIOCFLAG_CLOCAL))
820 1.14.8.2 nathanw SET(t.c_cflag, CLOCAL);
821 1.14.8.2 nathanw if (ISSET(chip->sc_swflags, TIOCFLAG_CRTSCTS))
822 1.14.8.2 nathanw SET(t.c_cflag, CRTSCTS);
823 1.14.8.2 nathanw if (ISSET(chip->sc_swflags, TIOCFLAG_MDMBUF))
824 1.14.8.2 nathanw SET(t.c_cflag, MDMBUF);
825 1.14.8.2 nathanw
826 1.14.8.2 nathanw /* Make sure txcomparam() will do something. */
827 1.14.8.2 nathanw tp->t_ospeed = 0;
828 1.14.8.2 nathanw txcomparam(tp, &t);
829 1.14.8.2 nathanw
830 1.14.8.2 nathanw tp->t_iflag = TTYDEF_IFLAG;
831 1.14.8.2 nathanw tp->t_oflag = TTYDEF_OFLAG;
832 1.14.8.2 nathanw tp->t_lflag = TTYDEF_LFLAG;
833 1.14.8.2 nathanw
834 1.14.8.2 nathanw ttychars(tp);
835 1.14.8.2 nathanw ttsetwater(tp);
836 1.14.8.2 nathanw
837 1.14.8.2 nathanw /*
838 1.14.8.2 nathanw * Turn on DTR. We must always do this, even if carrier is not
839 1.14.8.2 nathanw * present, because otherwise we'd have to use TIOCSDTR
840 1.14.8.2 nathanw * immediately after setting CLOCAL, which applications do not
841 1.14.8.2 nathanw * expect. We always assert DTR while the device is open
842 1.14.8.2 nathanw * unless explicitly requested to deassert it.
843 1.14.8.2 nathanw */
844 1.14.8.2 nathanw txcom_modem(sc, 1);
845 1.14.8.2 nathanw
846 1.14.8.2 nathanw /* Clear the input ring, and unblock. */
847 1.14.8.2 nathanw sc->sc_rbget = sc->sc_rbput = 0;
848 1.14.8.2 nathanw }
849 1.14.8.2 nathanw
850 1.14.8.2 nathanw splx(s);
851 1.14.8.2 nathanw #define TXCOMDIALOUT(x) (minor(x) & 0x80000)
852 1.14.8.2 nathanw if ((err = ttyopen(tp, TXCOMDIALOUT(dev), ISSET(flag, O_NONBLOCK)))) {
853 1.14.8.2 nathanw DPRINTF("ttyopen failed\n");
854 1.14.8.2 nathanw goto out;
855 1.14.8.2 nathanw }
856 1.14.8.2 nathanw if ((err = (*tp->t_linesw->l_open)(dev, tp))) {
857 1.14.8.2 nathanw DPRINTF("line dicipline open failed\n");
858 1.14.8.2 nathanw goto out;
859 1.14.8.2 nathanw }
860 1.14.8.2 nathanw
861 1.14.8.2 nathanw return err;
862 1.14.8.2 nathanw
863 1.14.8.2 nathanw out:
864 1.14.8.2 nathanw if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) {
865 1.14.8.2 nathanw /*
866 1.14.8.2 nathanw * We failed to open the device, and nobody else had it opened.
867 1.14.8.2 nathanw * Clean up the state as appropriate.
868 1.14.8.2 nathanw */
869 1.14.8.2 nathanw txcom_shutdown(sc);
870 1.14.8.2 nathanw }
871 1.14.8.2 nathanw
872 1.14.8.2 nathanw return err;
873 1.14.8.2 nathanw
874 1.14.8.2 nathanw }
875 1.14.8.2 nathanw
876 1.14.8.2 nathanw int
877 1.14.8.2 nathanw txcomclose(dev_t dev, int flag, int mode, struct proc *p)
878 1.14.8.2 nathanw {
879 1.14.8.2 nathanw struct txcom_softc *sc = txcom_cd.cd_devs[minor(dev)];
880 1.14.8.2 nathanw struct tty *tp = sc->sc_tty;
881 1.14.8.2 nathanw
882 1.14.8.2 nathanw /* XXX This is for cons.c. */
883 1.14.8.2 nathanw if (!ISSET(tp->t_state, TS_ISOPEN))
884 1.14.8.2 nathanw return 0;
885 1.14.8.2 nathanw
886 1.14.8.2 nathanw (*tp->t_linesw->l_close)(tp, flag);
887 1.14.8.2 nathanw ttyclose(tp);
888 1.14.8.2 nathanw
889 1.14.8.2 nathanw if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) {
890 1.14.8.2 nathanw /*
891 1.14.8.2 nathanw * Although we got a last close, the device may still be in
892 1.14.8.2 nathanw * use; e.g. if this was the dialout node, and there are still
893 1.14.8.2 nathanw * processes waiting for carrier on the non-dialout node.
894 1.14.8.2 nathanw */
895 1.14.8.2 nathanw txcom_shutdown(sc);
896 1.14.8.2 nathanw }
897 1.14.8.2 nathanw
898 1.14.8.2 nathanw return 0;
899 1.14.8.2 nathanw }
900 1.14.8.2 nathanw
901 1.14.8.2 nathanw int
902 1.14.8.2 nathanw txcomread(dev_t dev, struct uio *uio, int flag)
903 1.14.8.2 nathanw {
904 1.14.8.2 nathanw struct txcom_softc *sc = txcom_cd.cd_devs[minor(dev)];
905 1.14.8.2 nathanw struct tty *tp = sc->sc_tty;
906 1.14.8.2 nathanw
907 1.14.8.2 nathanw return ((*tp->t_linesw->l_read)(tp, uio, flag));
908 1.14.8.2 nathanw }
909 1.14.8.2 nathanw
910 1.14.8.2 nathanw int
911 1.14.8.2 nathanw txcomwrite(dev_t dev, struct uio *uio, int flag)
912 1.14.8.2 nathanw {
913 1.14.8.2 nathanw struct txcom_softc *sc = txcom_cd.cd_devs[minor(dev)];
914 1.14.8.2 nathanw struct tty *tp = sc->sc_tty;
915 1.14.8.2 nathanw
916 1.14.8.2 nathanw return ((*tp->t_linesw->l_write)(tp, uio, flag));
917 1.14.8.2 nathanw }
918 1.14.8.2 nathanw
919 1.14.8.2 nathanw int
920 1.14.8.2 nathanw txcompoll(dev_t dev, int events, struct proc *p)
921 1.14.8.2 nathanw {
922 1.14.8.2 nathanw struct txcom_softc *sc = txcom_cd.cd_devs[minor(dev)];
923 1.14.8.2 nathanw struct tty *tp = sc->sc_tty;
924 1.14.8.2 nathanw
925 1.14.8.2 nathanw return ((*tp->t_linesw->l_poll)(tp, events, p));
926 1.14.8.2 nathanw }
927 1.14.8.2 nathanw
928 1.14.8.2 nathanw struct tty *
929 1.14.8.2 nathanw txcomtty(dev_t dev)
930 1.14.8.2 nathanw {
931 1.14.8.2 nathanw struct txcom_softc *sc = txcom_cd.cd_devs[minor(dev)];
932 1.14.8.2 nathanw
933 1.14.8.2 nathanw return sc->sc_tty;
934 1.14.8.2 nathanw }
935 1.14.8.2 nathanw
936 1.14.8.2 nathanw int
937 1.14.8.2 nathanw txcomioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p)
938 1.14.8.2 nathanw {
939 1.14.8.2 nathanw struct txcom_softc *sc = txcom_cd.cd_devs[minor(dev)];
940 1.14.8.2 nathanw struct tty *tp = sc->sc_tty;
941 1.14.8.2 nathanw int s, err;
942 1.14.8.2 nathanw
943 1.14.8.2 nathanw err = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, p);
944 1.14.8.3 nathanw if (err != EPASSTHROUGH) {
945 1.14.8.2 nathanw return err;
946 1.14.8.2 nathanw }
947 1.14.8.2 nathanw
948 1.14.8.2 nathanw err = ttioctl(tp, cmd, data, flag, p);
949 1.14.8.3 nathanw if (err != EPASSTHROUGH) {
950 1.14.8.2 nathanw return err;
951 1.14.8.2 nathanw }
952 1.14.8.2 nathanw
953 1.14.8.2 nathanw err = 0;
954 1.14.8.2 nathanw
955 1.14.8.2 nathanw s = spltty();
956 1.14.8.2 nathanw
957 1.14.8.2 nathanw switch (cmd) {
958 1.14.8.2 nathanw default:
959 1.14.8.3 nathanw err = EPASSTHROUGH;
960 1.14.8.2 nathanw break;
961 1.14.8.2 nathanw
962 1.14.8.2 nathanw case TIOCSBRK:
963 1.14.8.2 nathanw txcom_break(sc, 1);
964 1.14.8.2 nathanw break;
965 1.14.8.2 nathanw
966 1.14.8.2 nathanw case TIOCCBRK:
967 1.14.8.2 nathanw txcom_break(sc, 0);
968 1.14.8.2 nathanw break;
969 1.14.8.2 nathanw
970 1.14.8.2 nathanw case TIOCSDTR:
971 1.14.8.2 nathanw txcom_modem(sc, 1);
972 1.14.8.2 nathanw break;
973 1.14.8.2 nathanw
974 1.14.8.2 nathanw case TIOCCDTR:
975 1.14.8.2 nathanw txcom_modem(sc, 0);
976 1.14.8.2 nathanw break;
977 1.14.8.2 nathanw
978 1.14.8.2 nathanw case TIOCGFLAGS:
979 1.14.8.2 nathanw *(int *)data = sc->sc_chip->sc_swflags;
980 1.14.8.2 nathanw break;
981 1.14.8.2 nathanw
982 1.14.8.2 nathanw case TIOCSFLAGS:
983 1.14.8.2 nathanw err = suser(p->p_ucred, &p->p_acflag);
984 1.14.8.2 nathanw if (err) {
985 1.14.8.2 nathanw break;
986 1.14.8.2 nathanw }
987 1.14.8.2 nathanw sc->sc_chip->sc_swflags = *(int *)data;
988 1.14.8.2 nathanw break;
989 1.14.8.2 nathanw
990 1.14.8.2 nathanw }
991 1.14.8.2 nathanw
992 1.14.8.2 nathanw splx(s);
993 1.14.8.2 nathanw
994 1.14.8.2 nathanw return err;
995 1.14.8.2 nathanw }
996 1.14.8.2 nathanw
997 1.14.8.2 nathanw void
998 1.14.8.2 nathanw txcomstop(struct tty *tp, int flag)
999 1.14.8.2 nathanw {
1000 1.14.8.2 nathanw struct txcom_softc *sc = txcom_cd.cd_devs[minor(tp->t_dev)];
1001 1.14.8.2 nathanw int s;
1002 1.14.8.2 nathanw
1003 1.14.8.2 nathanw s = spltty();
1004 1.14.8.2 nathanw
1005 1.14.8.2 nathanw if (ISSET(tp->t_state, TS_BUSY)) {
1006 1.14.8.2 nathanw /* Stop transmitting at the next chunk. */
1007 1.14.8.2 nathanw sc->sc_tbc = 0;
1008 1.14.8.2 nathanw sc->sc_heldtbc = 0;
1009 1.14.8.2 nathanw if (!ISSET(tp->t_state, TS_TTSTOP))
1010 1.14.8.2 nathanw SET(tp->t_state, TS_FLUSH);
1011 1.14.8.2 nathanw }
1012 1.14.8.2 nathanw
1013 1.14.8.2 nathanw splx(s);
1014 1.14.8.2 nathanw }
1015 1.14.8.2 nathanw
1016 1.14.8.2 nathanw void
1017 1.14.8.2 nathanw txcomstart(struct tty *tp)
1018 1.14.8.2 nathanw {
1019 1.14.8.2 nathanw struct txcom_softc *sc = txcom_cd.cd_devs[minor(tp->t_dev)];
1020 1.14.8.2 nathanw struct txcom_chip *chip = sc->sc_chip;
1021 1.14.8.2 nathanw tx_chipset_tag_t tc = chip->sc_tc;
1022 1.14.8.2 nathanw int slot = chip->sc_slot;
1023 1.14.8.2 nathanw int s;
1024 1.14.8.2 nathanw
1025 1.14.8.2 nathanw s = spltty();
1026 1.14.8.2 nathanw
1027 1.14.8.2 nathanw if (!__txcom_txbufready(chip, 0) ||
1028 1.14.8.2 nathanw ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP))
1029 1.14.8.2 nathanw goto out;
1030 1.14.8.2 nathanw
1031 1.14.8.2 nathanw if (tp->t_outq.c_cc <= tp->t_lowat) {
1032 1.14.8.2 nathanw if (ISSET(tp->t_state, TS_ASLEEP)) {
1033 1.14.8.2 nathanw CLR(tp->t_state, TS_ASLEEP);
1034 1.14.8.2 nathanw wakeup(&tp->t_outq);
1035 1.14.8.2 nathanw }
1036 1.14.8.2 nathanw selwakeup(&tp->t_wsel);
1037 1.14.8.2 nathanw if (tp->t_outq.c_cc == 0)
1038 1.14.8.2 nathanw goto out;
1039 1.14.8.2 nathanw }
1040 1.14.8.2 nathanw
1041 1.14.8.2 nathanw sc->sc_tba = tp->t_outq.c_cf;
1042 1.14.8.2 nathanw sc->sc_tbc = ndqb(&tp->t_outq, 0);
1043 1.14.8.2 nathanw SET(tp->t_state, TS_BUSY);
1044 1.14.8.2 nathanw
1045 1.14.8.2 nathanw /* Output the first character of the contiguous buffer. */
1046 1.14.8.2 nathanw tx_conf_write(tc, TX39_UARTTXHOLD_REG(slot),
1047 1.14.8.2 nathanw (*sc->sc_tba & TX39_UARTTXHOLD_TXDATA_MASK));
1048 1.14.8.2 nathanw
1049 1.14.8.2 nathanw sc->sc_tbc--;
1050 1.14.8.2 nathanw sc->sc_tba++;
1051 1.14.8.2 nathanw
1052 1.14.8.2 nathanw out:
1053 1.14.8.2 nathanw splx(s);
1054 1.14.8.2 nathanw }
1055 1.14.8.2 nathanw
1056 1.14.8.2 nathanw /*
1057 1.14.8.2 nathanw * Set TXcom tty parameters from termios.
1058 1.14.8.2 nathanw */
1059 1.14.8.2 nathanw int
1060 1.14.8.2 nathanw txcomparam(struct tty *tp, struct termios *t)
1061 1.14.8.2 nathanw {
1062 1.14.8.2 nathanw struct txcom_softc *sc = txcom_cd.cd_devs[minor(tp->t_dev)];
1063 1.14.8.2 nathanw struct txcom_chip *chip;
1064 1.14.8.2 nathanw int ospeed;
1065 1.14.8.2 nathanw int s;
1066 1.14.8.2 nathanw
1067 1.14.8.2 nathanw if (!sc)
1068 1.14.8.2 nathanw return ENXIO;
1069 1.14.8.2 nathanw
1070 1.14.8.2 nathanw ospeed = t->c_ospeed;
1071 1.14.8.2 nathanw
1072 1.14.8.2 nathanw /* Check requested parameters. */
1073 1.14.8.2 nathanw if (ospeed < 0) {
1074 1.14.8.2 nathanw return EINVAL;
1075 1.14.8.2 nathanw }
1076 1.14.8.2 nathanw if (t->c_ispeed && t->c_ispeed != ospeed) {
1077 1.14.8.2 nathanw return EINVAL;
1078 1.14.8.2 nathanw }
1079 1.14.8.2 nathanw
1080 1.14.8.2 nathanw s = spltty();
1081 1.14.8.2 nathanw chip = sc->sc_chip;
1082 1.14.8.2 nathanw /*
1083 1.14.8.2 nathanw * For the console, always force CLOCAL and !HUPCL, so that the port
1084 1.14.8.2 nathanw * is always active.
1085 1.14.8.2 nathanw */
1086 1.14.8.2 nathanw if (ISSET(chip->sc_swflags, TIOCFLAG_SOFTCAR) ||
1087 1.14.8.2 nathanw ISSET(chip->sc_hwflags, TXCOM_HW_CONSOLE)) {
1088 1.14.8.2 nathanw SET(t->c_cflag, CLOCAL);
1089 1.14.8.2 nathanw CLR(t->c_cflag, HUPCL);
1090 1.14.8.2 nathanw }
1091 1.14.8.2 nathanw splx(s);
1092 1.14.8.2 nathanw
1093 1.14.8.2 nathanw /*
1094 1.14.8.2 nathanw * If we're not in a mode that assumes a connection is present, then
1095 1.14.8.2 nathanw * ignore carrier changes.
1096 1.14.8.2 nathanw */
1097 1.14.8.2 nathanw if (ISSET(t->c_cflag, CLOCAL | MDMBUF))
1098 1.14.8.2 nathanw chip->sc_dcd = 0;
1099 1.14.8.2 nathanw else
1100 1.14.8.2 nathanw chip->sc_dcd = 1;
1101 1.14.8.2 nathanw
1102 1.14.8.2 nathanw /*
1103 1.14.8.2 nathanw * Only whack the UART when params change.
1104 1.14.8.2 nathanw * Some callers need to clear tp->t_ospeed
1105 1.14.8.2 nathanw * to make sure initialization gets done.
1106 1.14.8.2 nathanw */
1107 1.14.8.2 nathanw if (tp->t_ospeed == ospeed && tp->t_cflag == t->c_cflag) {
1108 1.14.8.2 nathanw return 0;
1109 1.14.8.2 nathanw }
1110 1.14.8.2 nathanw
1111 1.14.8.2 nathanw s = spltty();
1112 1.14.8.2 nathanw chip = sc->sc_chip;
1113 1.14.8.2 nathanw chip->sc_speed = ospeed;
1114 1.14.8.2 nathanw chip->sc_cflag = t->c_cflag;
1115 1.14.8.2 nathanw
1116 1.14.8.2 nathanw txcom_setmode(chip);
1117 1.14.8.2 nathanw txcom_setbaudrate(chip);
1118 1.14.8.2 nathanw
1119 1.14.8.2 nathanw /* And copy to tty. */
1120 1.14.8.2 nathanw tp->t_ispeed = 0;
1121 1.14.8.2 nathanw tp->t_ospeed = chip->sc_speed;
1122 1.14.8.2 nathanw tp->t_cflag = chip->sc_cflag;
1123 1.14.8.2 nathanw
1124 1.14.8.2 nathanw /*
1125 1.14.8.2 nathanw * Update the tty layer's idea of the carrier bit, in case we changed
1126 1.14.8.2 nathanw * CLOCAL or MDMBUF. We don't hang up here; we only do that by
1127 1.14.8.2 nathanw * explicit request.
1128 1.14.8.2 nathanw */
1129 1.14.8.2 nathanw (void) (*tp->t_linesw->l_modem)(tp, chip->sc_dcd);
1130 1.14.8.2 nathanw
1131 1.14.8.2 nathanw /*
1132 1.14.8.2 nathanw * If hardware flow control is disabled, unblock any hard flow
1133 1.14.8.2 nathanw * control state.
1134 1.14.8.2 nathanw */
1135 1.14.8.2 nathanw if (!ISSET(chip->sc_cflag, CHWFLOW)) {
1136 1.14.8.2 nathanw txcomstart(tp);
1137 1.14.8.2 nathanw }
1138 1.14.8.2 nathanw
1139 1.14.8.2 nathanw splx(s);
1140 1.14.8.2 nathanw
1141 1.14.8.2 nathanw return 0;
1142 1.14.8.2 nathanw }
1143 1.14.8.2 nathanw
1144 1.14.8.2 nathanw int
1145 1.14.8.2 nathanw txcom_dcd_hook(void *arg, int type, long id, void *msg)
1146 1.14.8.2 nathanw {
1147 1.14.8.2 nathanw struct txcom_softc *sc = arg;
1148 1.14.8.2 nathanw struct tty *tp = sc->sc_tty;
1149 1.14.8.2 nathanw struct txcom_chip *chip = sc->sc_chip;
1150 1.14.8.2 nathanw int modem = !(int)msg; /* p-edge 1, n-edge 0 */
1151 1.14.8.2 nathanw
1152 1.14.8.2 nathanw DPRINTF("DCD %s\n", modem ? "ON" : "OFF");
1153 1.14.8.2 nathanw
1154 1.14.8.2 nathanw if (modem && chip->sc_dcd)
1155 1.14.8.2 nathanw (void) (*tp->t_linesw->l_modem)(tp, chip->sc_dcd);
1156 1.14.8.2 nathanw
1157 1.14.8.2 nathanw return 0;
1158 1.14.8.2 nathanw }
1159 1.14.8.2 nathanw
1160 1.14.8.2 nathanw int
1161 1.14.8.2 nathanw txcom_cts_hook(void *arg, int type, long id, void *msg)
1162 1.14.8.2 nathanw {
1163 1.14.8.2 nathanw struct txcom_softc *sc = arg;
1164 1.14.8.2 nathanw struct tty *tp = sc->sc_tty;
1165 1.14.8.2 nathanw struct txcom_chip *chip = sc->sc_chip;
1166 1.14.8.2 nathanw int clear = !(int)msg; /* p-edge 1, n-edge 0 */
1167 1.14.8.2 nathanw
1168 1.14.8.2 nathanw DPRINTF("CTS %s\n", clear ? "ON" : "OFF");
1169 1.14.8.2 nathanw
1170 1.14.8.2 nathanw if (chip->sc_msr_cts) {
1171 1.14.8.2 nathanw if (!clear) {
1172 1.14.8.2 nathanw chip->sc_tx_stopped = 1;
1173 1.14.8.2 nathanw } else {
1174 1.14.8.2 nathanw chip->sc_tx_stopped = 0;
1175 1.14.8.2 nathanw (*tp->t_linesw->l_start)(tp);
1176 1.14.8.2 nathanw }
1177 1.14.8.2 nathanw }
1178 1.14.8.2 nathanw
1179 1.14.8.2 nathanw return 0;
1180 1.14.8.2 nathanw }
1181 1.14.8.2 nathanw
1182 1.14.8.2 nathanw #ifdef TX39UARTDEBUG
1183 1.14.8.2 nathanw void
1184 1.14.8.2 nathanw txcom_dump(struct txcom_chip *chip)
1185 1.14.8.2 nathanw {
1186 1.14.8.2 nathanw tx_chipset_tag_t tc = chip->sc_tc;
1187 1.14.8.2 nathanw int slot = chip->sc_slot;
1188 1.14.8.2 nathanw txreg_t reg;
1189 1.14.8.2 nathanw
1190 1.14.8.2 nathanw reg = tx_conf_read(tc, TX39_UARTCTRL1_REG(slot));
1191 1.14.8.2 nathanw #define ISSETPRINT(r, m) \
1192 1.14.8.2 nathanw dbg_bitmask_print(r, TX39_UARTCTRL1_##m, #m)
1193 1.14.8.2 nathanw ISSETPRINT(reg, UARTON);
1194 1.14.8.2 nathanw ISSETPRINT(reg, EMPTY);
1195 1.14.8.2 nathanw ISSETPRINT(reg, PRXHOLDFULL);
1196 1.14.8.2 nathanw ISSETPRINT(reg, RXHOLDFULL);
1197 1.14.8.2 nathanw ISSETPRINT(reg, ENDMARX);
1198 1.14.8.2 nathanw ISSETPRINT(reg, ENDMATX);
1199 1.14.8.2 nathanw ISSETPRINT(reg, TESTMODE);
1200 1.14.8.2 nathanw ISSETPRINT(reg, ENBREAHALT);
1201 1.14.8.2 nathanw ISSETPRINT(reg, ENDMATEST);
1202 1.14.8.2 nathanw ISSETPRINT(reg, ENDMALOOP);
1203 1.14.8.2 nathanw ISSETPRINT(reg, PULSEOPT2);
1204 1.14.8.2 nathanw ISSETPRINT(reg, PULSEOPT1);
1205 1.14.8.2 nathanw ISSETPRINT(reg, DTINVERT);
1206 1.14.8.2 nathanw ISSETPRINT(reg, DISTXD);
1207 1.14.8.2 nathanw ISSETPRINT(reg, TWOSTOP);
1208 1.14.8.2 nathanw ISSETPRINT(reg, LOOPBACK);
1209 1.14.8.2 nathanw ISSETPRINT(reg, BIT7);
1210 1.14.8.2 nathanw ISSETPRINT(reg, EVENPARITY);
1211 1.14.8.2 nathanw ISSETPRINT(reg, ENPARITY);
1212 1.14.8.2 nathanw ISSETPRINT(reg, ENUART);
1213 1.14.8.2 nathanw }
1214 1.14.8.2 nathanw #endif /* TX39UARTDEBUG */
1215