txcsbus.c revision 1.1
1 /* $NetBSD: txcsbus.c,v 1.1 1999/11/20 19:56:39 uch Exp $ */ 2 3 /* 4 * Copyright (c) 1999, by UCHIYAMA Yasushi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. The name of the developer may NOT be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 #include "opt_tx39_debug.h" 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/device.h> 33 34 #include <machine/bus.h> 35 #include <machine/intr.h> 36 37 #include <machine/platid.h> 38 #include <machine/platid_mask.h> 39 40 #include <hpcmips/tx/tx39var.h> 41 #include <hpcmips/tx/txcsbusvar.h> 42 #include <hpcmips/tx/tx39biuvar.h> 43 #include <hpcmips/tx/tx39biureg.h> 44 45 #include "locators.h" 46 47 int txcsbus_match __P((struct device*, struct cfdata*, void*)); 48 void txcsbus_attach __P((struct device*, struct device*, void*)); 49 int txcsbus_print __P((void*, const char*)); 50 int txcsbus_search __P((struct device*, struct cfdata*, void*)); 51 52 struct txcsbus_softc { 53 struct device sc_dev; 54 tx_chipset_tag_t sc_tc; 55 /* chip select space tag */ 56 bus_space_tag_t sc_cst[TX39_MAXCS]; 57 }; 58 59 struct cfattach txcsbus_ca = { 60 sizeof(struct txcsbus_softc), txcsbus_match, txcsbus_attach 61 }; 62 63 bus_space_tag_t __txcsbus_alloc_cstag __P((struct txcsbus_softc*, struct cs_handle*)); 64 65 int 66 txcsbus_match(parent, cf, aux) 67 struct device *parent; 68 struct cfdata *cf; 69 void *aux; 70 { 71 struct csbus_attach_args *cba = aux; 72 platid_mask_t mask; 73 74 if (strcmp(cba->cba_busname, cf->cf_driver->cd_name)) 75 return 0; 76 77 if (cf->cf_loc[TXCSBUSIFCF_PLATFORM] == TXCSBUSIFCF_PLATFORM_DEFAULT) 78 return 1; 79 80 mask = PLATID_DEREF(cf->cf_loc[TXCSBUSIFCF_PLATFORM]); 81 if (platid_match(&platid, &mask)) 82 return 2; 83 84 return 0; 85 } 86 87 void 88 txcsbus_attach(parent, self, aux) 89 struct device *parent; 90 struct device *self; 91 void *aux; 92 { 93 struct csbus_attach_args *cba = aux; 94 struct txcsbus_softc *sc = (void*)self; 95 96 sc->sc_tc = cba->cba_tc; 97 printf("\n"); 98 99 /* 100 * Attach external chip. 101 */ 102 config_search(txcsbus_search, self, txcsbus_print); 103 } 104 105 int 106 txcsbus_print(aux, pnp) 107 void *aux; 108 const char *pnp; 109 { 110 return pnp ? QUIET : UNCONF; 111 } 112 113 int 114 txcsbus_search(parent, cf, aux) 115 struct device *parent; 116 struct cfdata *cf; 117 void *aux; 118 { 119 struct txcsbus_softc *sc = (void*)parent; 120 struct cs_attach_args ca; 121 122 ca.ca_tc = sc->sc_tc; 123 124 ca.ca_csreg.cs = cf->cf_loc[TXCSBUSCF_REGCS]; 125 ca.ca_csreg.csbase = cf->cf_loc[TXCSBUSCF_REGCSBASE]; 126 ca.ca_csreg.cssize = cf->cf_loc[TXCSBUSCF_REGCSSIZE]; 127 ca.ca_csreg.cswidth = cf->cf_loc[TXCSBUSCF_REGCSWIDTH]; 128 if (ca.ca_csreg.cs != TXCSBUSCF_REGCS_DEFAULT) { 129 ca.ca_csreg.cstag = __txcsbus_alloc_cstag(sc, &ca.ca_csreg); 130 } 131 132 ca.ca_csio.cs = cf->cf_loc[TXCSBUSCF_IOCS]; 133 ca.ca_csio.csbase = cf->cf_loc[TXCSBUSCF_IOCSBASE]; 134 ca.ca_csio.cssize = cf->cf_loc[TXCSBUSCF_IOCSSIZE]; 135 ca.ca_csio.cswidth = cf->cf_loc[TXCSBUSCF_IOCSWIDTH]; 136 if (ca.ca_csio.cs != TXCSBUSCF_IOCS_DEFAULT) { 137 ca.ca_csio.cstag = __txcsbus_alloc_cstag(sc, &ca.ca_csio); 138 } 139 ca.ca_csmem.cs = cf->cf_loc[TXCSBUSCF_MEMCS]; 140 ca.ca_csmem.csbase = cf->cf_loc[TXCSBUSCF_MEMCSBASE]; 141 ca.ca_csmem.cssize = cf->cf_loc[TXCSBUSCF_MEMCSSIZE]; 142 ca.ca_csmem.cswidth = cf->cf_loc[TXCSBUSCF_MEMCSWIDTH]; 143 if (ca.ca_csmem.cs != TXCSBUSCF_MEMCS_DEFAULT) { 144 ca.ca_csmem.cstag = __txcsbus_alloc_cstag(sc, &ca.ca_csmem); 145 } 146 147 ca.ca_irq1 = cf->cf_loc[TXCSBUSCF_IRQ1]; 148 ca.ca_irq2 = cf->cf_loc[TXCSBUSCF_IRQ2]; 149 ca.ca_irq3 = cf->cf_loc[TXCSBUSCF_IRQ3]; 150 151 if ((*cf->cf_attach->ca_match)(parent, cf, &ca)) { 152 config_attach(parent, cf, &ca, txcsbus_print); 153 } 154 155 return 0; 156 } 157 158 bus_space_tag_t 159 __txcsbus_alloc_cstag(sc, csh) 160 struct txcsbus_softc *sc; 161 struct cs_handle *csh; 162 { 163 /* TX39 CS mapping. (nonconfigurationable) */ 164 struct csmap { 165 char *cs_name; 166 paddr_t cs_addr; 167 psize_t cs_size; 168 } __csmap[] = { 169 [TX39_CS0] = {"CS0(ROM)" , TX39_SYSADDR_CS0 ,TX39_SYSADDR_CS_SIZE}, 170 [TX39_CS1] = {"CS1" , TX39_SYSADDR_CS1 ,TX39_SYSADDR_CS_SIZE}, 171 [TX39_CS2] = {"CS2" , TX39_SYSADDR_CS2 ,TX39_SYSADDR_CS_SIZE}, 172 [TX39_CS3] = {"CS3" , TX39_SYSADDR_CS3 ,TX39_SYSADDR_CS_SIZE}, 173 [TX39_MCS0] = {"MCS0" , TX39_SYSADDR_MCS0 ,TX39_SYSADDR_MCS_SIZE}, 174 [TX39_MCS1] = {"MCS1" , TX39_SYSADDR_MCS1 ,TX39_SYSADDR_MCS_SIZE}, 175 #ifdef TX391X 176 [TX39_MCS2] = {"MCS2" , TX39_SYSADDR_MCS2 ,TX39_SYSADDR_MCS_SIZE}, 177 [TX39_MCS3] = {"MCS3" , TX39_SYSADDR_MCS3 ,TX39_SYSADDR_MCS_SIZE}, 178 #endif /* TX391X */ 179 [TX39_CARD1] = {"CARD1(io)" , TX39_SYSADDR_CARD1 ,TX39_SYSADDR_CARD_SIZE}, 180 [TX39_CARD2] = {"CARD2(io)" , TX39_SYSADDR_CARD2 ,TX39_SYSADDR_CARD_SIZE}, 181 [TX39_CARD1MEM] = {"CARD1(mem)" , TX39_SYSADDR_CARD1MEM ,TX39_SYSADDR_CARD_SIZE}, 182 [TX39_CARD2MEM] = {"CARD2(mem)" , TX39_SYSADDR_CARD2MEM ,TX39_SYSADDR_CARD_SIZE}, 183 }; 184 185 tx_chipset_tag_t tc = sc->sc_tc; 186 int cs = csh->cs; 187 int width = csh->cswidth; 188 bus_space_tag_t iot; 189 txreg_t reg; 190 191 if (!TX39_ISCS(cs) && !TX39_ISMCS(cs) && !TX39_ISCARD(cs)) { 192 panic("txcsbus_alloc_tag: bogus chip select %d\n", cs); 193 } 194 195 printf("(%s)", __csmap[cs].cs_name); 196 /* Already setuped chip select */ 197 if (sc->sc_cst[cs]) { 198 return sc->sc_cst[cs]; 199 } 200 201 iot = hpcmips_alloc_bus_space_tag(); 202 sc->sc_cst[cs] = iot; 203 204 iot->t_base = __csmap[cs].cs_addr; 205 iot->t_size = __csmap[cs].cs_size; 206 strcpy(iot->t_name , __csmap[cs].cs_name); 207 208 /* CS bus-width (configurationable) */ 209 switch (width) { 210 default: 211 panic("txcsbus_alloc_tag: bogus bus width %d\n", width); 212 case 32: 213 if (TX39_ISCS(cs)) { 214 reg = tx_conf_read(tc, TX39_MEMCONFIG0_REG); 215 reg |= (1 << cs); 216 tx_conf_write(tc, TX39_MEMCONFIG0_REG, reg); 217 } else { 218 #ifdef TX391X 219 panic("txcsbus_alloc_tag: MCS is 16bit only"); 220 #elif defined TX392X 221 reg = tx_conf_read(tc, TX39_MEMCONFIG1_REG); 222 reg |= ((cs == TX39_MCS0) ? TX39_MEMCONFIG1_MCS0_32 : 223 TX39_MEMCONFIG1_MCS1_32); 224 tx_conf_write(tc, TX39_MEMCONFIG1_REG, reg); 225 #endif 226 } 227 break; 228 case 16: 229 if (TX39_ISCS(cs)) { 230 reg = tx_conf_read(tc, TX39_MEMCONFIG0_REG); 231 reg &= ~(1 << cs); 232 tx_conf_write(tc, TX39_MEMCONFIG0_REG, reg); 233 } else { /* TX391X always 16bit port */ 234 #ifdef TX392X 235 reg = tx_conf_read(tc, TX39_MEMCONFIG1_REG); 236 reg &= ~((cs == TX39_MCS0) ? TX39_MEMCONFIG1_MCS0_32 : 237 TX39_MEMCONFIG1_MCS1_32); 238 tx_conf_write(tc, TX39_MEMCONFIG1_REG, reg); 239 #endif 240 } 241 break; 242 } 243 244 hpcmips_init_bus_space_extent(iot); 245 printf("\n"); 246 247 return iot; 248 } 249
Indexes created Fri Oct 31 09:09:54 GMT 2025