txcsbus.c revision 1.12
1 /* $NetBSD: txcsbus.c,v 1.12 2002/09/27 20:32:28 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/device.h> 42 43 #include <machine/intr.h> 44 #include <machine/bus.h> 45 #include <machine/bus_space_hpcmips.h> 46 47 #include <machine/platid.h> 48 #include <machine/platid_mask.h> 49 50 #include <hpcmips/tx/tx39var.h> 51 #include <hpcmips/tx/txcsbusvar.h> 52 #include <hpcmips/tx/tx39biuvar.h> 53 #include <hpcmips/tx/tx39biureg.h> 54 55 #include "locators.h" 56 57 /* TX39 CS mapping. (nonconfigurationable) */ 58 const struct csmap { 59 char *cs_name; 60 paddr_t cs_addr; 61 psize_t cs_size; 62 } __csmap[] = { 63 [TX39_CS0] = {"CS0(ROM)" , TX39_SYSADDR_CS0 , 64 TX39_SYSADDR_CS_SIZE}, 65 [TX39_CS1] = {"CS1" , TX39_SYSADDR_CS1 , 66 TX39_SYSADDR_CS_SIZE}, 67 [TX39_CS2] = {"CS2" , TX39_SYSADDR_CS2 , 68 TX39_SYSADDR_CS_SIZE}, 69 [TX39_CS3] = {"CS3" , TX39_SYSADDR_CS3 , 70 TX39_SYSADDR_CS_SIZE}, 71 [TX39_MCS0] = {"MCS0" , TX39_SYSADDR_MCS0 , 72 TX39_SYSADDR_MCS_SIZE}, 73 [TX39_MCS1] = {"MCS1" , TX39_SYSADDR_MCS1 , 74 TX39_SYSADDR_MCS_SIZE}, 75 #ifdef TX391X 76 [TX39_MCS2] = {"MCS2" , TX39_SYSADDR_MCS2 , 77 TX39_SYSADDR_MCS_SIZE}, 78 [TX39_MCS3] = {"MCS3" , TX39_SYSADDR_MCS3 , 79 TX39_SYSADDR_MCS_SIZE}, 80 #endif /* TX391X */ 81 [TX39_CARD1] = {"CARD1(io/attr)", TX39_SYSADDR_CARD1 , 82 TX39_SYSADDR_CARD_SIZE}, 83 [TX39_CARD2] = {"CARD2(io/attr)", TX39_SYSADDR_CARD2 , 84 TX39_SYSADDR_CARD_SIZE}, 85 [TX39_CARD1MEM] = {"CARD1(mem)" , TX39_SYSADDR_CARD1MEM , 86 TX39_SYSADDR_CARD_SIZE}, 87 [TX39_CARD2MEM] = {"CARD2(mem)" , TX39_SYSADDR_CARD2MEM , 88 TX39_SYSADDR_CARD_SIZE}, 89 }; 90 91 int txcsbus_match(struct device *, struct cfdata *, void *); 92 void txcsbus_attach(struct device *, struct device *, void *); 93 int txcsbus_print(void *, const char *); 94 int txcsbus_search(struct device *, struct cfdata *, void *); 95 96 struct txcsbus_softc { 97 struct device sc_dev; 98 tx_chipset_tag_t sc_tc; 99 /* chip select space tag */ 100 struct bus_space_tag_hpcmips *sc_cst[TX39_MAXCS]; 101 }; 102 103 const struct cfattach txcsbus_ca = { 104 sizeof(struct txcsbus_softc), txcsbus_match, txcsbus_attach 105 }; 106 107 static bus_space_tag_t __txcsbus_alloc_cstag(struct txcsbus_softc *, 108 struct cs_handle *); 109 110 int 111 txcsbus_match(struct device *parent, struct cfdata *cf, void *aux) 112 { 113 struct csbus_attach_args *cba = aux; 114 platid_mask_t mask; 115 116 if (strcmp(cba->cba_busname, cf->cf_name)) 117 return (0); 118 119 if (cf->cf_loc[TXCSBUSIFCF_PLATFORM] == TXCSBUSIFCF_PLATFORM_DEFAULT) 120 return (1); 121 122 mask = PLATID_DEREF(cf->cf_loc[TXCSBUSIFCF_PLATFORM]); 123 if (platid_match(&platid, &mask)) 124 return (2); 125 126 return (0); 127 } 128 129 void 130 txcsbus_attach(struct device *parent, struct device *self, void *aux) 131 { 132 struct csbus_attach_args *cba = aux; 133 struct txcsbus_softc *sc = (void*)self; 134 135 sc->sc_tc = cba->cba_tc; 136 printf("\n"); 137 138 /* 139 * Attach external chip. 140 */ 141 config_search(txcsbus_search, self, txcsbus_print); 142 } 143 144 int 145 txcsbus_print(void *aux, const char *pnp) 146 { 147 #define PRINTIRQ(i) i, (i) / 32, (i) % 32 148 struct cs_attach_args *ca = aux; 149 150 if (ca->ca_csreg.cs != TXCSBUSCF_REGCS_DEFAULT) { 151 printf(" regcs %s %dbit %#x+%#x", 152 __csmap[ca->ca_csreg.cs].cs_name, 153 ca->ca_csreg.cswidth, 154 ca->ca_csreg.csbase, 155 ca->ca_csreg.cssize); 156 } 157 158 if (ca->ca_csio.cs != TXCSBUSCF_IOCS_DEFAULT) { 159 printf(" iocs %s %dbit %#x+%#x", 160 __csmap[ca->ca_csio.cs].cs_name, 161 ca->ca_csio.cswidth, 162 ca->ca_csio.csbase, 163 ca->ca_csio.cssize); 164 } 165 166 if (ca->ca_csmem.cs != TXCSBUSCF_MEMCS_DEFAULT) { 167 printf(" memcs %s %dbit %#x+%#x", 168 __csmap[ca->ca_csmem.cs].cs_name, 169 ca->ca_csmem.cswidth, 170 ca->ca_csmem.csbase, 171 ca->ca_csmem.cssize); 172 } 173 174 if (ca->ca_irq1 != TXCSBUSCF_IRQ1_DEFAULT) { 175 printf(" irq1 %d(%d:%d)", PRINTIRQ(ca->ca_irq1)); 176 } 177 178 if (ca->ca_irq2 != TXCSBUSCF_IRQ2_DEFAULT) { 179 printf(" irq2 %d(%d:%d)", PRINTIRQ(ca->ca_irq2)); 180 } 181 182 if (ca->ca_irq3 != TXCSBUSCF_IRQ3_DEFAULT) { 183 printf(" irq3 %d(%d:%d)", PRINTIRQ(ca->ca_irq3)); 184 } 185 186 return (UNCONF); 187 } 188 189 int 190 txcsbus_search(struct device *parent, struct cfdata *cf, void *aux) 191 { 192 struct txcsbus_softc *sc = (void*)parent; 193 struct cs_attach_args ca; 194 195 ca.ca_tc = sc->sc_tc; 196 197 ca.ca_csreg.cs = cf->cf_loc[TXCSBUSCF_REGCS]; 198 ca.ca_csreg.csbase = cf->cf_loc[TXCSBUSCF_REGCSBASE]; 199 ca.ca_csreg.cssize = cf->cf_loc[TXCSBUSCF_REGCSSIZE]; 200 ca.ca_csreg.cswidth = cf->cf_loc[TXCSBUSCF_REGCSWIDTH]; 201 202 if (ca.ca_csreg.cs != TXCSBUSCF_REGCS_DEFAULT) { 203 ca.ca_csreg.cstag = __txcsbus_alloc_cstag(sc, &ca.ca_csreg); 204 } 205 206 ca.ca_csio.cs = cf->cf_loc[TXCSBUSCF_IOCS]; 207 ca.ca_csio.csbase = cf->cf_loc[TXCSBUSCF_IOCSBASE]; 208 ca.ca_csio.cssize = cf->cf_loc[TXCSBUSCF_IOCSSIZE]; 209 ca.ca_csio.cswidth = cf->cf_loc[TXCSBUSCF_IOCSWIDTH]; 210 211 if (ca.ca_csio.cs != TXCSBUSCF_IOCS_DEFAULT) { 212 ca.ca_csio.cstag = __txcsbus_alloc_cstag(sc, &ca.ca_csio); 213 } 214 215 ca.ca_csmem.cs = cf->cf_loc[TXCSBUSCF_MEMCS]; 216 ca.ca_csmem.csbase = cf->cf_loc[TXCSBUSCF_MEMCSBASE]; 217 ca.ca_csmem.cssize = cf->cf_loc[TXCSBUSCF_MEMCSSIZE]; 218 ca.ca_csmem.cswidth = cf->cf_loc[TXCSBUSCF_MEMCSWIDTH]; 219 220 if (ca.ca_csmem.cs != TXCSBUSCF_MEMCS_DEFAULT) { 221 ca.ca_csmem.cstag = __txcsbus_alloc_cstag(sc, &ca.ca_csmem); 222 } 223 224 ca.ca_irq1 = cf->cf_loc[TXCSBUSCF_IRQ1]; 225 ca.ca_irq2 = cf->cf_loc[TXCSBUSCF_IRQ2]; 226 ca.ca_irq3 = cf->cf_loc[TXCSBUSCF_IRQ3]; 227 228 if (config_match(parent, cf, &ca)) { 229 config_attach(parent, cf, &ca, txcsbus_print); 230 } 231 232 return (0); 233 } 234 235 bus_space_tag_t 236 __txcsbus_alloc_cstag(struct txcsbus_softc *sc, struct cs_handle *csh) 237 { 238 239 tx_chipset_tag_t tc = sc->sc_tc; 240 int cs = csh->cs; 241 int width = csh->cswidth; 242 struct bus_space_tag_hpcmips *iot; 243 txreg_t reg; 244 245 if (!TX39_ISCS(cs) && !TX39_ISMCS(cs) && !TX39_ISCARD(cs)) { 246 panic("txcsbus_alloc_tag: bogus chip select %d", cs); 247 } 248 249 /* Already setuped chip select */ 250 if (sc->sc_cst[cs]) { 251 return (&sc->sc_cst[cs]->bst); 252 } 253 254 iot = hpcmips_alloc_bus_space_tag(); 255 hpcmips_init_bus_space(iot, hpcmips_system_bus_space_hpcmips(), 256 __csmap[cs].cs_name, __csmap[cs].cs_addr, __csmap[cs].cs_size); 257 sc->sc_cst[cs] = iot; 258 259 /* CS bus-width (configurationable) */ 260 switch (width) { 261 default: 262 panic("txcsbus_alloc_tag: bogus bus width %d", width); 263 264 case 32: 265 if (TX39_ISCS(cs)) { 266 reg = tx_conf_read(tc, TX39_MEMCONFIG0_REG); 267 reg |= (1 << cs); 268 tx_conf_write(tc, TX39_MEMCONFIG0_REG, reg); 269 } else if(TX39_ISMCS(cs)) { 270 #ifdef TX391X 271 panic("txcsbus_alloc_tag: MCS is 16bit only"); 272 #endif /* TX391X */ 273 #ifdef TX392X 274 reg = tx_conf_read(tc, TX39_MEMCONFIG1_REG); 275 reg |= ((cs == TX39_MCS0) ? 276 TX39_MEMCONFIG1_MCS0_32 : 277 TX39_MEMCONFIG1_MCS1_32); 278 tx_conf_write(tc, TX39_MEMCONFIG1_REG, reg); 279 #endif /* TX392X */ 280 } 281 break; 282 283 case 16: 284 if (TX39_ISCS(cs)) { 285 reg = tx_conf_read(tc, TX39_MEMCONFIG0_REG); 286 reg &= ~(1 << cs); 287 tx_conf_write(tc, TX39_MEMCONFIG0_REG, reg); 288 } else if(TX39_ISMCS(cs)) { 289 /* TX391X always 16bit port */ 290 #ifdef TX392X 291 reg = tx_conf_read(tc, TX39_MEMCONFIG1_REG); 292 reg &= ~((cs == TX39_MCS0) ? 293 TX39_MEMCONFIG1_MCS0_32 : 294 TX39_MEMCONFIG1_MCS1_32); 295 tx_conf_write(tc, TX39_MEMCONFIG1_REG, reg); 296 #endif /* TX392X */ 297 } else { 298 /* CARD io/attr or mem */ 299 reg = tx_conf_read(tc, TX39_MEMCONFIG3_REG); 300 301 /* enable I/O access */ 302 reg |= (cs == TX39_CARD1) ? 303 TX39_MEMCONFIG3_CARD1IOEN : 304 TX39_MEMCONFIG3_CARD2IOEN; 305 /* disable 8bit access */ 306 #ifdef TX392X 307 reg &= ~((cs == TX39_CARD1) ? 308 TX39_MEMCONFIG3_CARD1_8SEL : 309 TX39_MEMCONFIG3_CARD2_8SEL); 310 #endif /* TX392X */ 311 #ifdef TX391X 312 reg &= ~TX39_MEMCONFIG3_PORT8SEL; 313 #endif /* TX391X */ 314 tx_conf_write(tc, TX39_MEMCONFIG3_REG, reg); 315 } 316 break; 317 318 case 8: 319 if (TX39_ISCARD(cs)) { 320 reg = tx_conf_read(tc, TX39_MEMCONFIG3_REG); 321 322 /* enable I/O access */ 323 reg |= (cs == TX39_CARD1) ? 324 TX39_MEMCONFIG3_CARD1IOEN : 325 TX39_MEMCONFIG3_CARD2IOEN; 326 /* disable 8bit access */ 327 #ifdef TX392X 328 reg |= (cs == TX39_CARD1) ? 329 TX39_MEMCONFIG3_CARD1_8SEL : 330 TX39_MEMCONFIG3_CARD2_8SEL; 331 #endif /* TX392X */ 332 #ifdef TX391X 333 reg |= TX39_MEMCONFIG3_PORT8SEL; 334 #endif /* TX391X */ 335 tx_conf_write(tc, TX39_MEMCONFIG3_REG, reg); 336 337 } else { 338 panic("__txcsbus_alloc_cstag: CS%d 8bit mode is" 339 "not allowed", cs); 340 } 341 } 342 343 return (&iot->bst); 344 } 345
Indexes created Thu Oct 30 03:10:01 GMT 2025