txcsbus.c revision 1.15.14.1
1 /* $NetBSD: txcsbus.c,v 1.15.14.1 2005/08/04 18:30:06 tron Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: txcsbus.c,v 1.15.14.1 2005/08/04 18:30:06 tron Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/device.h> 45 46 #include <machine/intr.h> 47 #include <machine/bus.h> 48 #include <machine/bus_space_hpcmips.h> 49 50 #include <machine/platid.h> 51 #include <machine/platid_mask.h> 52 53 #include <hpcmips/tx/tx39var.h> 54 #include <hpcmips/tx/txcsbusvar.h> 55 #include <hpcmips/tx/tx39biuvar.h> 56 #include <hpcmips/tx/tx39biureg.h> 57 58 #include "locators.h" 59 60 /* TX39 CS mapping. (nonconfigurationable) */ 61 const struct csmap { 62 char *cs_name; 63 paddr_t cs_addr; 64 psize_t cs_size; 65 } __csmap[] = { 66 [TX39_CS0] = {"CS0(ROM)" , TX39_SYSADDR_CS0 , 67 TX39_SYSADDR_CS_SIZE}, 68 [TX39_CS1] = {"CS1" , TX39_SYSADDR_CS1 , 69 TX39_SYSADDR_CS_SIZE}, 70 [TX39_CS2] = {"CS2" , TX39_SYSADDR_CS2 , 71 TX39_SYSADDR_CS_SIZE}, 72 [TX39_CS3] = {"CS3" , TX39_SYSADDR_CS3 , 73 TX39_SYSADDR_CS_SIZE}, 74 [TX39_MCS0] = {"MCS0" , TX39_SYSADDR_MCS0 , 75 TX39_SYSADDR_MCS_SIZE}, 76 [TX39_MCS1] = {"MCS1" , TX39_SYSADDR_MCS1 , 77 TX39_SYSADDR_MCS_SIZE}, 78 #ifdef TX391X 79 [TX39_MCS2] = {"MCS2" , TX39_SYSADDR_MCS2 , 80 TX39_SYSADDR_MCS_SIZE}, 81 [TX39_MCS3] = {"MCS3" , TX39_SYSADDR_MCS3 , 82 TX39_SYSADDR_MCS_SIZE}, 83 #endif /* TX391X */ 84 [TX39_CARD1] = {"CARD1(io/attr)", TX39_SYSADDR_CARD1 , 85 TX39_SYSADDR_CARD_SIZE}, 86 [TX39_CARD2] = {"CARD2(io/attr)", TX39_SYSADDR_CARD2 , 87 TX39_SYSADDR_CARD_SIZE}, 88 [TX39_CARD1MEM] = {"CARD1(mem)" , TX39_SYSADDR_CARD1MEM , 89 TX39_SYSADDR_CARD_SIZE}, 90 [TX39_CARD2MEM] = {"CARD2(mem)" , TX39_SYSADDR_CARD2MEM , 91 TX39_SYSADDR_CARD_SIZE}, 92 [TX39_KUCS0] = {"KUCS0" , TX39_SYSADDR_KUSEG_CS0, 93 TX39_SYSADDR_KUCS_SIZE}, 94 [TX39_KUCS1] = {"KUCS1" , TX39_SYSADDR_KUSEG_CS1, 95 TX39_SYSADDR_KUCS_SIZE}, 96 [TX39_KUCS2] = {"KUCS2" , TX39_SYSADDR_KUSEG_CS2, 97 TX39_SYSADDR_KUCS_SIZE}, 98 [TX39_KUCS3] = {"KUCS3" , TX39_SYSADDR_KUSEG_CS3, 99 TX39_SYSADDR_KUCS_SIZE}, 100 }; 101 102 int txcsbus_match(struct device *, struct cfdata *, void *); 103 void txcsbus_attach(struct device *, struct device *, void *); 104 int txcsbus_print(void *, const char *); 105 int txcsbus_search(struct device *, struct cfdata *, void *); 106 107 struct txcsbus_softc { 108 struct device sc_dev; 109 tx_chipset_tag_t sc_tc; 110 /* chip select space tag */ 111 struct bus_space_tag_hpcmips *sc_cst[TX39_MAXCS]; 112 int sc_pri; 113 }; 114 115 CFATTACH_DECL(txcsbus, sizeof(struct txcsbus_softc), 116 txcsbus_match, txcsbus_attach, NULL, NULL); 117 118 static bus_space_tag_t __txcsbus_alloc_cstag(struct txcsbus_softc *, 119 struct cs_handle *); 120 121 int 122 txcsbus_match(struct device *parent, struct cfdata *cf, void *aux) 123 { 124 struct csbus_attach_args *cba = aux; 125 platid_mask_t mask; 126 127 if (strcmp(cba->cba_busname, cf->cf_name)) 128 return (0); 129 130 if (cf->cf_loc[TXCSBUSIFCF_PLATFORM] == TXCSBUSIFCF_PLATFORM_DEFAULT) 131 return (1); 132 133 mask = PLATID_DEREF(cf->cf_loc[TXCSBUSIFCF_PLATFORM]); 134 if (platid_match(&platid, &mask)) 135 return (2); 136 137 return (0); 138 } 139 140 void 141 txcsbus_attach(struct device *parent, struct device *self, void *aux) 142 { 143 struct csbus_attach_args *cba = aux; 144 struct txcsbus_softc *sc = (void*)self; 145 146 sc->sc_tc = cba->cba_tc; 147 printf("\n"); 148 149 /* 150 * Attach external chip. 151 */ 152 /* higher priority devices attach first */ 153 sc->sc_pri = 2; 154 config_search(txcsbus_search, self, txcsbus_print); 155 /* then, normal priority devices */ 156 sc->sc_pri = 1; 157 config_search(txcsbus_search, self, txcsbus_print); 158 } 159 160 int 161 txcsbus_print(void *aux, const char *pnp) 162 { 163 #define PRINTIRQ(i) i, (i) / 32, (i) % 32 164 struct cs_attach_args *ca = aux; 165 166 if (ca->ca_csreg.cs != TXCSBUSCF_REGCS_DEFAULT) { 167 aprint_normal(" regcs %s %dbit %#x+%#x", 168 __csmap[ca->ca_csreg.cs].cs_name, 169 ca->ca_csreg.cswidth, 170 ca->ca_csreg.csbase, 171 ca->ca_csreg.cssize); 172 } 173 174 if (ca->ca_csio.cs != TXCSBUSCF_IOCS_DEFAULT) { 175 aprint_normal(" iocs %s %dbit %#x+%#x", 176 __csmap[ca->ca_csio.cs].cs_name, 177 ca->ca_csio.cswidth, 178 ca->ca_csio.csbase, 179 ca->ca_csio.cssize); 180 } 181 182 if (ca->ca_csmem.cs != TXCSBUSCF_MEMCS_DEFAULT) { 183 aprint_normal(" memcs %s %dbit %#x+%#x", 184 __csmap[ca->ca_csmem.cs].cs_name, 185 ca->ca_csmem.cswidth, 186 ca->ca_csmem.csbase, 187 ca->ca_csmem.cssize); 188 } 189 190 if (ca->ca_irq1 != TXCSBUSCF_IRQ1_DEFAULT) { 191 aprint_normal(" irq1 %d(%d:%d)", PRINTIRQ(ca->ca_irq1)); 192 } 193 194 if (ca->ca_irq2 != TXCSBUSCF_IRQ2_DEFAULT) { 195 aprint_normal(" irq2 %d(%d:%d)", PRINTIRQ(ca->ca_irq2)); 196 } 197 198 if (ca->ca_irq3 != TXCSBUSCF_IRQ3_DEFAULT) { 199 aprint_normal(" irq3 %d(%d:%d)", PRINTIRQ(ca->ca_irq3)); 200 } 201 202 return (UNCONF); 203 } 204 205 int 206 txcsbus_search(struct device *parent, struct cfdata *cf, void *aux) 207 { 208 struct txcsbus_softc *sc = (void*)parent; 209 struct cs_attach_args ca; 210 211 ca.ca_tc = sc->sc_tc; 212 213 ca.ca_csreg.cs = cf->cf_loc[TXCSBUSCF_REGCS]; 214 ca.ca_csreg.csbase = cf->cf_loc[TXCSBUSCF_REGCSBASE]; 215 ca.ca_csreg.cssize = cf->cf_loc[TXCSBUSCF_REGCSSIZE]; 216 ca.ca_csreg.cswidth = cf->cf_loc[TXCSBUSCF_REGCSWIDTH]; 217 218 if (ca.ca_csreg.cs != TXCSBUSCF_REGCS_DEFAULT) { 219 ca.ca_csreg.cstag = __txcsbus_alloc_cstag(sc, &ca.ca_csreg); 220 } 221 222 ca.ca_csio.cs = cf->cf_loc[TXCSBUSCF_IOCS]; 223 ca.ca_csio.csbase = cf->cf_loc[TXCSBUSCF_IOCSBASE]; 224 ca.ca_csio.cssize = cf->cf_loc[TXCSBUSCF_IOCSSIZE]; 225 ca.ca_csio.cswidth = cf->cf_loc[TXCSBUSCF_IOCSWIDTH]; 226 227 if (ca.ca_csio.cs != TXCSBUSCF_IOCS_DEFAULT) { 228 ca.ca_csio.cstag = __txcsbus_alloc_cstag(sc, &ca.ca_csio); 229 } 230 231 ca.ca_csmem.cs = cf->cf_loc[TXCSBUSCF_MEMCS]; 232 ca.ca_csmem.csbase = cf->cf_loc[TXCSBUSCF_MEMCSBASE]; 233 ca.ca_csmem.cssize = cf->cf_loc[TXCSBUSCF_MEMCSSIZE]; 234 ca.ca_csmem.cswidth = cf->cf_loc[TXCSBUSCF_MEMCSWIDTH]; 235 236 if (ca.ca_csmem.cs != TXCSBUSCF_MEMCS_DEFAULT) { 237 ca.ca_csmem.cstag = __txcsbus_alloc_cstag(sc, &ca.ca_csmem); 238 } 239 240 ca.ca_irq1 = cf->cf_loc[TXCSBUSCF_IRQ1]; 241 ca.ca_irq2 = cf->cf_loc[TXCSBUSCF_IRQ2]; 242 ca.ca_irq3 = cf->cf_loc[TXCSBUSCF_IRQ3]; 243 244 if (config_match(parent, cf, &ca) == sc->sc_pri) { 245 config_attach(parent, cf, &ca, txcsbus_print); 246 } 247 248 return (0); 249 } 250 251 bus_space_tag_t 252 __txcsbus_alloc_cstag(struct txcsbus_softc *sc, struct cs_handle *csh) 253 { 254 255 tx_chipset_tag_t tc = sc->sc_tc; 256 int cs = csh->cs; 257 int width = csh->cswidth; 258 struct bus_space_tag_hpcmips *iot; 259 txreg_t reg; 260 261 if (!TX39_ISCS(cs) && !TX39_ISMCS(cs) && !TX39_ISCARD(cs) && 262 !TX39_ISKUCS(cs)) { 263 panic("txcsbus_alloc_tag: bogus chip select %d", cs); 264 } 265 266 /* Already setuped chip select */ 267 if (sc->sc_cst[cs]) { 268 return (&sc->sc_cst[cs]->bst); 269 } 270 271 iot = hpcmips_alloc_bus_space_tag(); 272 hpcmips_init_bus_space(iot, hpcmips_system_bus_space_hpcmips(), 273 __csmap[cs].cs_name, __csmap[cs].cs_addr, __csmap[cs].cs_size); 274 sc->sc_cst[cs] = iot; 275 276 /* CS bus-width (configurationable) */ 277 switch (width) { 278 default: 279 panic("txcsbus_alloc_tag: bogus bus width %d", width); 280 281 case 32: 282 if (TX39_ISCS(cs)) { 283 reg = tx_conf_read(tc, TX39_MEMCONFIG0_REG); 284 reg |= (1 << cs); 285 tx_conf_write(tc, TX39_MEMCONFIG0_REG, reg); 286 } else if(TX39_ISMCS(cs)) { 287 #ifdef TX391X 288 panic("txcsbus_alloc_tag: MCS is 16bit only"); 289 #endif /* TX391X */ 290 #ifdef TX392X 291 reg = tx_conf_read(tc, TX39_MEMCONFIG1_REG); 292 reg |= ((cs == TX39_MCS0) ? 293 TX39_MEMCONFIG1_MCS0_32 : 294 TX39_MEMCONFIG1_MCS1_32); 295 tx_conf_write(tc, TX39_MEMCONFIG1_REG, reg); 296 #endif /* TX392X */ 297 } 298 break; 299 300 case 16: 301 if (TX39_ISCS(cs)) { 302 reg = tx_conf_read(tc, TX39_MEMCONFIG0_REG); 303 reg &= ~(1 << cs); 304 tx_conf_write(tc, TX39_MEMCONFIG0_REG, reg); 305 } else if(TX39_ISMCS(cs)) { 306 /* TX391X always 16bit port */ 307 #ifdef TX392X 308 reg = tx_conf_read(tc, TX39_MEMCONFIG1_REG); 309 reg &= ~((cs == TX39_MCS0) ? 310 TX39_MEMCONFIG1_MCS0_32 : 311 TX39_MEMCONFIG1_MCS1_32); 312 tx_conf_write(tc, TX39_MEMCONFIG1_REG, reg); 313 #endif /* TX392X */ 314 } else if (TX39_ISCARD(cs)) { 315 /* CARD io/attr or mem */ 316 reg = tx_conf_read(tc, TX39_MEMCONFIG3_REG); 317 318 /* enable I/O access */ 319 reg |= (cs == TX39_CARD1) ? 320 TX39_MEMCONFIG3_CARD1IOEN : 321 TX39_MEMCONFIG3_CARD2IOEN; 322 /* disable 8bit access */ 323 #ifdef TX392X 324 reg &= ~((cs == TX39_CARD1) ? 325 TX39_MEMCONFIG3_CARD1_8SEL : 326 TX39_MEMCONFIG3_CARD2_8SEL); 327 #endif /* TX392X */ 328 #ifdef TX391X 329 reg &= ~TX39_MEMCONFIG3_PORT8SEL; 330 #endif /* TX391X */ 331 tx_conf_write(tc, TX39_MEMCONFIG3_REG, reg); 332 } 333 break; 334 335 case 8: 336 if (TX39_ISCARD(cs)) { 337 reg = tx_conf_read(tc, TX39_MEMCONFIG3_REG); 338 339 /* enable I/O access */ 340 reg |= (cs == TX39_CARD1) ? 341 TX39_MEMCONFIG3_CARD1IOEN : 342 TX39_MEMCONFIG3_CARD2IOEN; 343 /* disable 8bit access */ 344 #ifdef TX392X 345 reg |= (cs == TX39_CARD1) ? 346 TX39_MEMCONFIG3_CARD1_8SEL : 347 TX39_MEMCONFIG3_CARD2_8SEL; 348 #endif /* TX392X */ 349 #ifdef TX391X 350 reg |= TX39_MEMCONFIG3_PORT8SEL; 351 #endif /* TX391X */ 352 tx_conf_write(tc, TX39_MEMCONFIG3_REG, reg); 353 354 } else { 355 panic("__txcsbus_alloc_cstag: CS%d 8bit mode is" 356 "not allowed", cs); 357 } 358 } 359 360 return (&iot->bst); 361 } 362
Indexes created Wed Oct 29 20:09:47 GMT 2025