txcsbus.c revision 1.16
1 /* $NetBSD: txcsbus.c,v 1.16 2005/06/07 12:19:46 he Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: txcsbus.c,v 1.16 2005/06/07 12:19:46 he Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/device.h> 45 46 #include <machine/intr.h> 47 #include <machine/bus.h> 48 #include <machine/bus_space_hpcmips.h> 49 50 #include <machine/platid.h> 51 #include <machine/platid_mask.h> 52 53 #include <hpcmips/tx/tx39var.h> 54 #include <hpcmips/tx/txcsbusvar.h> 55 #include <hpcmips/tx/tx39biuvar.h> 56 #include <hpcmips/tx/tx39biureg.h> 57 58 #include "locators.h" 59 60 /* TX39 CS mapping. (nonconfigurationable) */ 61 const struct csmap { 62 const char *cs_name; 63 paddr_t cs_addr; 64 psize_t cs_size; 65 } __csmap[] = { 66 [TX39_CS0] = {"CS0(ROM)" , TX39_SYSADDR_CS0 , 67 TX39_SYSADDR_CS_SIZE}, 68 [TX39_CS1] = {"CS1" , TX39_SYSADDR_CS1 , 69 TX39_SYSADDR_CS_SIZE}, 70 [TX39_CS2] = {"CS2" , TX39_SYSADDR_CS2 , 71 TX39_SYSADDR_CS_SIZE}, 72 [TX39_CS3] = {"CS3" , TX39_SYSADDR_CS3 , 73 TX39_SYSADDR_CS_SIZE}, 74 [TX39_MCS0] = {"MCS0" , TX39_SYSADDR_MCS0 , 75 TX39_SYSADDR_MCS_SIZE}, 76 [TX39_MCS1] = {"MCS1" , TX39_SYSADDR_MCS1 , 77 TX39_SYSADDR_MCS_SIZE}, 78 #ifdef TX391X 79 [TX39_MCS2] = {"MCS2" , TX39_SYSADDR_MCS2 , 80 TX39_SYSADDR_MCS_SIZE}, 81 [TX39_MCS3] = {"MCS3" , TX39_SYSADDR_MCS3 , 82 TX39_SYSADDR_MCS_SIZE}, 83 #endif /* TX391X */ 84 [TX39_CARD1] = {"CARD1(io/attr)", TX39_SYSADDR_CARD1 , 85 TX39_SYSADDR_CARD_SIZE}, 86 [TX39_CARD2] = {"CARD2(io/attr)", TX39_SYSADDR_CARD2 , 87 TX39_SYSADDR_CARD_SIZE}, 88 [TX39_CARD1MEM] = {"CARD1(mem)" , TX39_SYSADDR_CARD1MEM , 89 TX39_SYSADDR_CARD_SIZE}, 90 [TX39_CARD2MEM] = {"CARD2(mem)" , TX39_SYSADDR_CARD2MEM , 91 TX39_SYSADDR_CARD_SIZE}, 92 }; 93 94 int txcsbus_match(struct device *, struct cfdata *, void *); 95 void txcsbus_attach(struct device *, struct device *, void *); 96 int txcsbus_print(void *, const char *); 97 int txcsbus_search(struct device *, struct cfdata *, void *); 98 99 struct txcsbus_softc { 100 struct device sc_dev; 101 tx_chipset_tag_t sc_tc; 102 /* chip select space tag */ 103 struct bus_space_tag_hpcmips *sc_cst[TX39_MAXCS]; 104 }; 105 106 CFATTACH_DECL(txcsbus, sizeof(struct txcsbus_softc), 107 txcsbus_match, txcsbus_attach, NULL, NULL); 108 109 static bus_space_tag_t __txcsbus_alloc_cstag(struct txcsbus_softc *, 110 struct cs_handle *); 111 112 int 113 txcsbus_match(struct device *parent, struct cfdata *cf, void *aux) 114 { 115 struct csbus_attach_args *cba = aux; 116 platid_mask_t mask; 117 118 if (strcmp(cba->cba_busname, cf->cf_name)) 119 return (0); 120 121 if (cf->cf_loc[TXCSBUSIFCF_PLATFORM] == TXCSBUSIFCF_PLATFORM_DEFAULT) 122 return (1); 123 124 mask = PLATID_DEREF(cf->cf_loc[TXCSBUSIFCF_PLATFORM]); 125 if (platid_match(&platid, &mask)) 126 return (2); 127 128 return (0); 129 } 130 131 void 132 txcsbus_attach(struct device *parent, struct device *self, void *aux) 133 { 134 struct csbus_attach_args *cba = aux; 135 struct txcsbus_softc *sc = (void*)self; 136 137 sc->sc_tc = cba->cba_tc; 138 printf("\n"); 139 140 /* 141 * Attach external chip. 142 */ 143 config_search(txcsbus_search, self, txcsbus_print); 144 } 145 146 int 147 txcsbus_print(void *aux, const char *pnp) 148 { 149 #define PRINTIRQ(i) i, (i) / 32, (i) % 32 150 struct cs_attach_args *ca = aux; 151 152 if (ca->ca_csreg.cs != TXCSBUSCF_REGCS_DEFAULT) { 153 aprint_normal(" regcs %s %dbit %#x+%#x", 154 __csmap[ca->ca_csreg.cs].cs_name, 155 ca->ca_csreg.cswidth, 156 ca->ca_csreg.csbase, 157 ca->ca_csreg.cssize); 158 } 159 160 if (ca->ca_csio.cs != TXCSBUSCF_IOCS_DEFAULT) { 161 aprint_normal(" iocs %s %dbit %#x+%#x", 162 __csmap[ca->ca_csio.cs].cs_name, 163 ca->ca_csio.cswidth, 164 ca->ca_csio.csbase, 165 ca->ca_csio.cssize); 166 } 167 168 if (ca->ca_csmem.cs != TXCSBUSCF_MEMCS_DEFAULT) { 169 aprint_normal(" memcs %s %dbit %#x+%#x", 170 __csmap[ca->ca_csmem.cs].cs_name, 171 ca->ca_csmem.cswidth, 172 ca->ca_csmem.csbase, 173 ca->ca_csmem.cssize); 174 } 175 176 if (ca->ca_irq1 != TXCSBUSCF_IRQ1_DEFAULT) { 177 aprint_normal(" irq1 %d(%d:%d)", PRINTIRQ(ca->ca_irq1)); 178 } 179 180 if (ca->ca_irq2 != TXCSBUSCF_IRQ2_DEFAULT) { 181 aprint_normal(" irq2 %d(%d:%d)", PRINTIRQ(ca->ca_irq2)); 182 } 183 184 if (ca->ca_irq3 != TXCSBUSCF_IRQ3_DEFAULT) { 185 aprint_normal(" irq3 %d(%d:%d)", PRINTIRQ(ca->ca_irq3)); 186 } 187 188 return (UNCONF); 189 } 190 191 int 192 txcsbus_search(struct device *parent, struct cfdata *cf, void *aux) 193 { 194 struct txcsbus_softc *sc = (void*)parent; 195 struct cs_attach_args ca; 196 197 ca.ca_tc = sc->sc_tc; 198 199 ca.ca_csreg.cs = cf->cf_loc[TXCSBUSCF_REGCS]; 200 ca.ca_csreg.csbase = cf->cf_loc[TXCSBUSCF_REGCSBASE]; 201 ca.ca_csreg.cssize = cf->cf_loc[TXCSBUSCF_REGCSSIZE]; 202 ca.ca_csreg.cswidth = cf->cf_loc[TXCSBUSCF_REGCSWIDTH]; 203 204 if (ca.ca_csreg.cs != TXCSBUSCF_REGCS_DEFAULT) { 205 ca.ca_csreg.cstag = __txcsbus_alloc_cstag(sc, &ca.ca_csreg); 206 } 207 208 ca.ca_csio.cs = cf->cf_loc[TXCSBUSCF_IOCS]; 209 ca.ca_csio.csbase = cf->cf_loc[TXCSBUSCF_IOCSBASE]; 210 ca.ca_csio.cssize = cf->cf_loc[TXCSBUSCF_IOCSSIZE]; 211 ca.ca_csio.cswidth = cf->cf_loc[TXCSBUSCF_IOCSWIDTH]; 212 213 if (ca.ca_csio.cs != TXCSBUSCF_IOCS_DEFAULT) { 214 ca.ca_csio.cstag = __txcsbus_alloc_cstag(sc, &ca.ca_csio); 215 } 216 217 ca.ca_csmem.cs = cf->cf_loc[TXCSBUSCF_MEMCS]; 218 ca.ca_csmem.csbase = cf->cf_loc[TXCSBUSCF_MEMCSBASE]; 219 ca.ca_csmem.cssize = cf->cf_loc[TXCSBUSCF_MEMCSSIZE]; 220 ca.ca_csmem.cswidth = cf->cf_loc[TXCSBUSCF_MEMCSWIDTH]; 221 222 if (ca.ca_csmem.cs != TXCSBUSCF_MEMCS_DEFAULT) { 223 ca.ca_csmem.cstag = __txcsbus_alloc_cstag(sc, &ca.ca_csmem); 224 } 225 226 ca.ca_irq1 = cf->cf_loc[TXCSBUSCF_IRQ1]; 227 ca.ca_irq2 = cf->cf_loc[TXCSBUSCF_IRQ2]; 228 ca.ca_irq3 = cf->cf_loc[TXCSBUSCF_IRQ3]; 229 230 if (config_match(parent, cf, &ca)) { 231 config_attach(parent, cf, &ca, txcsbus_print); 232 } 233 234 return (0); 235 } 236 237 bus_space_tag_t 238 __txcsbus_alloc_cstag(struct txcsbus_softc *sc, struct cs_handle *csh) 239 { 240 241 tx_chipset_tag_t tc = sc->sc_tc; 242 int cs = csh->cs; 243 int width = csh->cswidth; 244 struct bus_space_tag_hpcmips *iot; 245 txreg_t reg; 246 247 if (!TX39_ISCS(cs) && !TX39_ISMCS(cs) && !TX39_ISCARD(cs)) { 248 panic("txcsbus_alloc_tag: bogus chip select %d", cs); 249 } 250 251 /* Already setuped chip select */ 252 if (sc->sc_cst[cs]) { 253 return (&sc->sc_cst[cs]->bst); 254 } 255 256 iot = hpcmips_alloc_bus_space_tag(); 257 hpcmips_init_bus_space(iot, hpcmips_system_bus_space_hpcmips(), 258 __csmap[cs].cs_name, __csmap[cs].cs_addr, __csmap[cs].cs_size); 259 sc->sc_cst[cs] = iot; 260 261 /* CS bus-width (configurationable) */ 262 switch (width) { 263 default: 264 panic("txcsbus_alloc_tag: bogus bus width %d", width); 265 266 case 32: 267 if (TX39_ISCS(cs)) { 268 reg = tx_conf_read(tc, TX39_MEMCONFIG0_REG); 269 reg |= (1 << cs); 270 tx_conf_write(tc, TX39_MEMCONFIG0_REG, reg); 271 } else if(TX39_ISMCS(cs)) { 272 #ifdef TX391X 273 panic("txcsbus_alloc_tag: MCS is 16bit only"); 274 #endif /* TX391X */ 275 #ifdef TX392X 276 reg = tx_conf_read(tc, TX39_MEMCONFIG1_REG); 277 reg |= ((cs == TX39_MCS0) ? 278 TX39_MEMCONFIG1_MCS0_32 : 279 TX39_MEMCONFIG1_MCS1_32); 280 tx_conf_write(tc, TX39_MEMCONFIG1_REG, reg); 281 #endif /* TX392X */ 282 } 283 break; 284 285 case 16: 286 if (TX39_ISCS(cs)) { 287 reg = tx_conf_read(tc, TX39_MEMCONFIG0_REG); 288 reg &= ~(1 << cs); 289 tx_conf_write(tc, TX39_MEMCONFIG0_REG, reg); 290 } else if(TX39_ISMCS(cs)) { 291 /* TX391X always 16bit port */ 292 #ifdef TX392X 293 reg = tx_conf_read(tc, TX39_MEMCONFIG1_REG); 294 reg &= ~((cs == TX39_MCS0) ? 295 TX39_MEMCONFIG1_MCS0_32 : 296 TX39_MEMCONFIG1_MCS1_32); 297 tx_conf_write(tc, TX39_MEMCONFIG1_REG, reg); 298 #endif /* TX392X */ 299 } else { 300 /* CARD io/attr or mem */ 301 reg = tx_conf_read(tc, TX39_MEMCONFIG3_REG); 302 303 /* enable I/O access */ 304 reg |= (cs == TX39_CARD1) ? 305 TX39_MEMCONFIG3_CARD1IOEN : 306 TX39_MEMCONFIG3_CARD2IOEN; 307 /* disable 8bit access */ 308 #ifdef TX392X 309 reg &= ~((cs == TX39_CARD1) ? 310 TX39_MEMCONFIG3_CARD1_8SEL : 311 TX39_MEMCONFIG3_CARD2_8SEL); 312 #endif /* TX392X */ 313 #ifdef TX391X 314 reg &= ~TX39_MEMCONFIG3_PORT8SEL; 315 #endif /* TX391X */ 316 tx_conf_write(tc, TX39_MEMCONFIG3_REG, reg); 317 } 318 break; 319 320 case 8: 321 if (TX39_ISCARD(cs)) { 322 reg = tx_conf_read(tc, TX39_MEMCONFIG3_REG); 323 324 /* enable I/O access */ 325 reg |= (cs == TX39_CARD1) ? 326 TX39_MEMCONFIG3_CARD1IOEN : 327 TX39_MEMCONFIG3_CARD2IOEN; 328 /* disable 8bit access */ 329 #ifdef TX392X 330 reg |= (cs == TX39_CARD1) ? 331 TX39_MEMCONFIG3_CARD1_8SEL : 332 TX39_MEMCONFIG3_CARD2_8SEL; 333 #endif /* TX392X */ 334 #ifdef TX391X 335 reg |= TX39_MEMCONFIG3_PORT8SEL; 336 #endif /* TX391X */ 337 tx_conf_write(tc, TX39_MEMCONFIG3_REG, reg); 338 339 } else { 340 panic("__txcsbus_alloc_cstag: CS%d 8bit mode is" 341 "not allowed", cs); 342 } 343 } 344 345 return (&iot->bst); 346 } 347
Indexes created Thu Oct 30 16:09:53 GMT 2025