txcsbus.c revision 1.17
1 /* $NetBSD: txcsbus.c,v 1.17 2005/06/30 17:03:53 drochner Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: txcsbus.c,v 1.17 2005/06/30 17:03:53 drochner Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/device.h> 45 46 #include <machine/intr.h> 47 #include <machine/bus.h> 48 #include <machine/bus_space_hpcmips.h> 49 50 #include <machine/platid.h> 51 #include <machine/platid_mask.h> 52 53 #include <hpcmips/tx/tx39var.h> 54 #include <hpcmips/tx/txcsbusvar.h> 55 #include <hpcmips/tx/tx39biuvar.h> 56 #include <hpcmips/tx/tx39biureg.h> 57 58 #include "locators.h" 59 60 /* TX39 CS mapping. (nonconfigurationable) */ 61 const struct csmap { 62 const char *cs_name; 63 paddr_t cs_addr; 64 psize_t cs_size; 65 } __csmap[] = { 66 [TX39_CS0] = {"CS0(ROM)" , TX39_SYSADDR_CS0 , 67 TX39_SYSADDR_CS_SIZE}, 68 [TX39_CS1] = {"CS1" , TX39_SYSADDR_CS1 , 69 TX39_SYSADDR_CS_SIZE}, 70 [TX39_CS2] = {"CS2" , TX39_SYSADDR_CS2 , 71 TX39_SYSADDR_CS_SIZE}, 72 [TX39_CS3] = {"CS3" , TX39_SYSADDR_CS3 , 73 TX39_SYSADDR_CS_SIZE}, 74 [TX39_MCS0] = {"MCS0" , TX39_SYSADDR_MCS0 , 75 TX39_SYSADDR_MCS_SIZE}, 76 [TX39_MCS1] = {"MCS1" , TX39_SYSADDR_MCS1 , 77 TX39_SYSADDR_MCS_SIZE}, 78 #ifdef TX391X 79 [TX39_MCS2] = {"MCS2" , TX39_SYSADDR_MCS2 , 80 TX39_SYSADDR_MCS_SIZE}, 81 [TX39_MCS3] = {"MCS3" , TX39_SYSADDR_MCS3 , 82 TX39_SYSADDR_MCS_SIZE}, 83 #endif /* TX391X */ 84 [TX39_CARD1] = {"CARD1(io/attr)", TX39_SYSADDR_CARD1 , 85 TX39_SYSADDR_CARD_SIZE}, 86 [TX39_CARD2] = {"CARD2(io/attr)", TX39_SYSADDR_CARD2 , 87 TX39_SYSADDR_CARD_SIZE}, 88 [TX39_CARD1MEM] = {"CARD1(mem)" , TX39_SYSADDR_CARD1MEM , 89 TX39_SYSADDR_CARD_SIZE}, 90 [TX39_CARD2MEM] = {"CARD2(mem)" , TX39_SYSADDR_CARD2MEM , 91 TX39_SYSADDR_CARD_SIZE}, 92 }; 93 94 int txcsbus_match(struct device *, struct cfdata *, void *); 95 void txcsbus_attach(struct device *, struct device *, void *); 96 int txcsbus_print(void *, const char *); 97 int txcsbus_search(struct device *, struct cfdata *, 98 const locdesc_t *, void *); 99 100 struct txcsbus_softc { 101 struct device sc_dev; 102 tx_chipset_tag_t sc_tc; 103 /* chip select space tag */ 104 struct bus_space_tag_hpcmips *sc_cst[TX39_MAXCS]; 105 }; 106 107 CFATTACH_DECL(txcsbus, sizeof(struct txcsbus_softc), 108 txcsbus_match, txcsbus_attach, NULL, NULL); 109 110 static bus_space_tag_t __txcsbus_alloc_cstag(struct txcsbus_softc *, 111 struct cs_handle *); 112 113 int 114 txcsbus_match(struct device *parent, struct cfdata *cf, void *aux) 115 { 116 struct csbus_attach_args *cba = aux; 117 platid_mask_t mask; 118 119 if (strcmp(cba->cba_busname, cf->cf_name)) 120 return (0); 121 122 if (cf->cf_loc[TXCSBUSIFCF_PLATFORM] == TXCSBUSIFCF_PLATFORM_DEFAULT) 123 return (1); 124 125 mask = PLATID_DEREF(cf->cf_loc[TXCSBUSIFCF_PLATFORM]); 126 if (platid_match(&platid, &mask)) 127 return (2); 128 129 return (0); 130 } 131 132 void 133 txcsbus_attach(struct device *parent, struct device *self, void *aux) 134 { 135 struct csbus_attach_args *cba = aux; 136 struct txcsbus_softc *sc = (void*)self; 137 138 sc->sc_tc = cba->cba_tc; 139 printf("\n"); 140 141 /* 142 * Attach external chip. 143 */ 144 config_search_ia(txcsbus_search, self, "txcsbus", txcsbus_print); 145 } 146 147 int 148 txcsbus_print(void *aux, const char *pnp) 149 { 150 #define PRINTIRQ(i) i, (i) / 32, (i) % 32 151 struct cs_attach_args *ca = aux; 152 153 if (ca->ca_csreg.cs != TXCSBUSCF_REGCS_DEFAULT) { 154 aprint_normal(" regcs %s %dbit %#x+%#x", 155 __csmap[ca->ca_csreg.cs].cs_name, 156 ca->ca_csreg.cswidth, 157 ca->ca_csreg.csbase, 158 ca->ca_csreg.cssize); 159 } 160 161 if (ca->ca_csio.cs != TXCSBUSCF_IOCS_DEFAULT) { 162 aprint_normal(" iocs %s %dbit %#x+%#x", 163 __csmap[ca->ca_csio.cs].cs_name, 164 ca->ca_csio.cswidth, 165 ca->ca_csio.csbase, 166 ca->ca_csio.cssize); 167 } 168 169 if (ca->ca_csmem.cs != TXCSBUSCF_MEMCS_DEFAULT) { 170 aprint_normal(" memcs %s %dbit %#x+%#x", 171 __csmap[ca->ca_csmem.cs].cs_name, 172 ca->ca_csmem.cswidth, 173 ca->ca_csmem.csbase, 174 ca->ca_csmem.cssize); 175 } 176 177 if (ca->ca_irq1 != TXCSBUSCF_IRQ1_DEFAULT) { 178 aprint_normal(" irq1 %d(%d:%d)", PRINTIRQ(ca->ca_irq1)); 179 } 180 181 if (ca->ca_irq2 != TXCSBUSCF_IRQ2_DEFAULT) { 182 aprint_normal(" irq2 %d(%d:%d)", PRINTIRQ(ca->ca_irq2)); 183 } 184 185 if (ca->ca_irq3 != TXCSBUSCF_IRQ3_DEFAULT) { 186 aprint_normal(" irq3 %d(%d:%d)", PRINTIRQ(ca->ca_irq3)); 187 } 188 189 return (UNCONF); 190 } 191 192 int 193 txcsbus_search(struct device *parent, struct cfdata *cf, 194 const locdesc_t *ldesc, void *aux) 195 { 196 struct txcsbus_softc *sc = (void*)parent; 197 struct cs_attach_args ca; 198 199 ca.ca_tc = sc->sc_tc; 200 201 ca.ca_csreg.cs = cf->cf_loc[TXCSBUSCF_REGCS]; 202 ca.ca_csreg.csbase = cf->cf_loc[TXCSBUSCF_REGCSBASE]; 203 ca.ca_csreg.cssize = cf->cf_loc[TXCSBUSCF_REGCSSIZE]; 204 ca.ca_csreg.cswidth = cf->cf_loc[TXCSBUSCF_REGCSWIDTH]; 205 206 if (ca.ca_csreg.cs != TXCSBUSCF_REGCS_DEFAULT) { 207 ca.ca_csreg.cstag = __txcsbus_alloc_cstag(sc, &ca.ca_csreg); 208 } 209 210 ca.ca_csio.cs = cf->cf_loc[TXCSBUSCF_IOCS]; 211 ca.ca_csio.csbase = cf->cf_loc[TXCSBUSCF_IOCSBASE]; 212 ca.ca_csio.cssize = cf->cf_loc[TXCSBUSCF_IOCSSIZE]; 213 ca.ca_csio.cswidth = cf->cf_loc[TXCSBUSCF_IOCSWIDTH]; 214 215 if (ca.ca_csio.cs != TXCSBUSCF_IOCS_DEFAULT) { 216 ca.ca_csio.cstag = __txcsbus_alloc_cstag(sc, &ca.ca_csio); 217 } 218 219 ca.ca_csmem.cs = cf->cf_loc[TXCSBUSCF_MEMCS]; 220 ca.ca_csmem.csbase = cf->cf_loc[TXCSBUSCF_MEMCSBASE]; 221 ca.ca_csmem.cssize = cf->cf_loc[TXCSBUSCF_MEMCSSIZE]; 222 ca.ca_csmem.cswidth = cf->cf_loc[TXCSBUSCF_MEMCSWIDTH]; 223 224 if (ca.ca_csmem.cs != TXCSBUSCF_MEMCS_DEFAULT) { 225 ca.ca_csmem.cstag = __txcsbus_alloc_cstag(sc, &ca.ca_csmem); 226 } 227 228 ca.ca_irq1 = cf->cf_loc[TXCSBUSCF_IRQ1]; 229 ca.ca_irq2 = cf->cf_loc[TXCSBUSCF_IRQ2]; 230 ca.ca_irq3 = cf->cf_loc[TXCSBUSCF_IRQ3]; 231 232 if (config_match(parent, cf, &ca)) { 233 config_attach(parent, cf, &ca, txcsbus_print); 234 } 235 236 return (0); 237 } 238 239 bus_space_tag_t 240 __txcsbus_alloc_cstag(struct txcsbus_softc *sc, struct cs_handle *csh) 241 { 242 243 tx_chipset_tag_t tc = sc->sc_tc; 244 int cs = csh->cs; 245 int width = csh->cswidth; 246 struct bus_space_tag_hpcmips *iot; 247 txreg_t reg; 248 249 if (!TX39_ISCS(cs) && !TX39_ISMCS(cs) && !TX39_ISCARD(cs)) { 250 panic("txcsbus_alloc_tag: bogus chip select %d", cs); 251 } 252 253 /* Already setuped chip select */ 254 if (sc->sc_cst[cs]) { 255 return (&sc->sc_cst[cs]->bst); 256 } 257 258 iot = hpcmips_alloc_bus_space_tag(); 259 hpcmips_init_bus_space(iot, hpcmips_system_bus_space_hpcmips(), 260 __csmap[cs].cs_name, __csmap[cs].cs_addr, __csmap[cs].cs_size); 261 sc->sc_cst[cs] = iot; 262 263 /* CS bus-width (configurationable) */ 264 switch (width) { 265 default: 266 panic("txcsbus_alloc_tag: bogus bus width %d", width); 267 268 case 32: 269 if (TX39_ISCS(cs)) { 270 reg = tx_conf_read(tc, TX39_MEMCONFIG0_REG); 271 reg |= (1 << cs); 272 tx_conf_write(tc, TX39_MEMCONFIG0_REG, reg); 273 } else if(TX39_ISMCS(cs)) { 274 #ifdef TX391X 275 panic("txcsbus_alloc_tag: MCS is 16bit only"); 276 #endif /* TX391X */ 277 #ifdef TX392X 278 reg = tx_conf_read(tc, TX39_MEMCONFIG1_REG); 279 reg |= ((cs == TX39_MCS0) ? 280 TX39_MEMCONFIG1_MCS0_32 : 281 TX39_MEMCONFIG1_MCS1_32); 282 tx_conf_write(tc, TX39_MEMCONFIG1_REG, reg); 283 #endif /* TX392X */ 284 } 285 break; 286 287 case 16: 288 if (TX39_ISCS(cs)) { 289 reg = tx_conf_read(tc, TX39_MEMCONFIG0_REG); 290 reg &= ~(1 << cs); 291 tx_conf_write(tc, TX39_MEMCONFIG0_REG, reg); 292 } else if(TX39_ISMCS(cs)) { 293 /* TX391X always 16bit port */ 294 #ifdef TX392X 295 reg = tx_conf_read(tc, TX39_MEMCONFIG1_REG); 296 reg &= ~((cs == TX39_MCS0) ? 297 TX39_MEMCONFIG1_MCS0_32 : 298 TX39_MEMCONFIG1_MCS1_32); 299 tx_conf_write(tc, TX39_MEMCONFIG1_REG, reg); 300 #endif /* TX392X */ 301 } else { 302 /* CARD io/attr or mem */ 303 reg = tx_conf_read(tc, TX39_MEMCONFIG3_REG); 304 305 /* enable I/O access */ 306 reg |= (cs == TX39_CARD1) ? 307 TX39_MEMCONFIG3_CARD1IOEN : 308 TX39_MEMCONFIG3_CARD2IOEN; 309 /* disable 8bit access */ 310 #ifdef TX392X 311 reg &= ~((cs == TX39_CARD1) ? 312 TX39_MEMCONFIG3_CARD1_8SEL : 313 TX39_MEMCONFIG3_CARD2_8SEL); 314 #endif /* TX392X */ 315 #ifdef TX391X 316 reg &= ~TX39_MEMCONFIG3_PORT8SEL; 317 #endif /* TX391X */ 318 tx_conf_write(tc, TX39_MEMCONFIG3_REG, reg); 319 } 320 break; 321 322 case 8: 323 if (TX39_ISCARD(cs)) { 324 reg = tx_conf_read(tc, TX39_MEMCONFIG3_REG); 325 326 /* enable I/O access */ 327 reg |= (cs == TX39_CARD1) ? 328 TX39_MEMCONFIG3_CARD1IOEN : 329 TX39_MEMCONFIG3_CARD2IOEN; 330 /* disable 8bit access */ 331 #ifdef TX392X 332 reg |= (cs == TX39_CARD1) ? 333 TX39_MEMCONFIG3_CARD1_8SEL : 334 TX39_MEMCONFIG3_CARD2_8SEL; 335 #endif /* TX392X */ 336 #ifdef TX391X 337 reg |= TX39_MEMCONFIG3_PORT8SEL; 338 #endif /* TX391X */ 339 tx_conf_write(tc, TX39_MEMCONFIG3_REG, reg); 340 341 } else { 342 panic("__txcsbus_alloc_cstag: CS%d 8bit mode is" 343 "not allowed", cs); 344 } 345 } 346 347 return (&iot->bst); 348 } 349
Indexes created Fri Oct 31 11:10:07 GMT 2025