txcsbus.c revision 1.5.8.4
1 /* $NetBSD: txcsbus.c,v 1.5.8.4 2002/10/18 02:37:14 nathanw Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/device.h> 42 43 #include <machine/intr.h> 44 #include <machine/bus.h> 45 #include <machine/bus_space_hpcmips.h> 46 47 #include <machine/platid.h> 48 #include <machine/platid_mask.h> 49 50 #include <hpcmips/tx/tx39var.h> 51 #include <hpcmips/tx/txcsbusvar.h> 52 #include <hpcmips/tx/tx39biuvar.h> 53 #include <hpcmips/tx/tx39biureg.h> 54 55 #include "locators.h" 56 57 /* TX39 CS mapping. (nonconfigurationable) */ 58 const struct csmap { 59 char *cs_name; 60 paddr_t cs_addr; 61 psize_t cs_size; 62 } __csmap[] = { 63 [TX39_CS0] = {"CS0(ROM)" , TX39_SYSADDR_CS0 , 64 TX39_SYSADDR_CS_SIZE}, 65 [TX39_CS1] = {"CS1" , TX39_SYSADDR_CS1 , 66 TX39_SYSADDR_CS_SIZE}, 67 [TX39_CS2] = {"CS2" , TX39_SYSADDR_CS2 , 68 TX39_SYSADDR_CS_SIZE}, 69 [TX39_CS3] = {"CS3" , TX39_SYSADDR_CS3 , 70 TX39_SYSADDR_CS_SIZE}, 71 [TX39_MCS0] = {"MCS0" , TX39_SYSADDR_MCS0 , 72 TX39_SYSADDR_MCS_SIZE}, 73 [TX39_MCS1] = {"MCS1" , TX39_SYSADDR_MCS1 , 74 TX39_SYSADDR_MCS_SIZE}, 75 #ifdef TX391X 76 [TX39_MCS2] = {"MCS2" , TX39_SYSADDR_MCS2 , 77 TX39_SYSADDR_MCS_SIZE}, 78 [TX39_MCS3] = {"MCS3" , TX39_SYSADDR_MCS3 , 79 TX39_SYSADDR_MCS_SIZE}, 80 #endif /* TX391X */ 81 [TX39_CARD1] = {"CARD1(io/attr)", TX39_SYSADDR_CARD1 , 82 TX39_SYSADDR_CARD_SIZE}, 83 [TX39_CARD2] = {"CARD2(io/attr)", TX39_SYSADDR_CARD2 , 84 TX39_SYSADDR_CARD_SIZE}, 85 [TX39_CARD1MEM] = {"CARD1(mem)" , TX39_SYSADDR_CARD1MEM , 86 TX39_SYSADDR_CARD_SIZE}, 87 [TX39_CARD2MEM] = {"CARD2(mem)" , TX39_SYSADDR_CARD2MEM , 88 TX39_SYSADDR_CARD_SIZE}, 89 }; 90 91 int txcsbus_match(struct device *, struct cfdata *, void *); 92 void txcsbus_attach(struct device *, struct device *, void *); 93 int txcsbus_print(void *, const char *); 94 int txcsbus_search(struct device *, struct cfdata *, void *); 95 96 struct txcsbus_softc { 97 struct device sc_dev; 98 tx_chipset_tag_t sc_tc; 99 /* chip select space tag */ 100 struct bus_space_tag_hpcmips *sc_cst[TX39_MAXCS]; 101 }; 102 103 CFATTACH_DECL(txcsbus, sizeof(struct txcsbus_softc), 104 txcsbus_match, txcsbus_attach, NULL, NULL); 105 106 static bus_space_tag_t __txcsbus_alloc_cstag(struct txcsbus_softc *, 107 struct cs_handle *); 108 109 int 110 txcsbus_match(struct device *parent, struct cfdata *cf, void *aux) 111 { 112 struct csbus_attach_args *cba = aux; 113 platid_mask_t mask; 114 115 if (strcmp(cba->cba_busname, cf->cf_name)) 116 return (0); 117 118 if (cf->cf_loc[TXCSBUSIFCF_PLATFORM] == TXCSBUSIFCF_PLATFORM_DEFAULT) 119 return (1); 120 121 mask = PLATID_DEREF(cf->cf_loc[TXCSBUSIFCF_PLATFORM]); 122 if (platid_match(&platid, &mask)) 123 return (2); 124 125 return (0); 126 } 127 128 void 129 txcsbus_attach(struct device *parent, struct device *self, void *aux) 130 { 131 struct csbus_attach_args *cba = aux; 132 struct txcsbus_softc *sc = (void*)self; 133 134 sc->sc_tc = cba->cba_tc; 135 printf("\n"); 136 137 /* 138 * Attach external chip. 139 */ 140 config_search(txcsbus_search, self, txcsbus_print); 141 } 142 143 int 144 txcsbus_print(void *aux, const char *pnp) 145 { 146 #define PRINTIRQ(i) i, (i) / 32, (i) % 32 147 struct cs_attach_args *ca = aux; 148 149 if (ca->ca_csreg.cs != TXCSBUSCF_REGCS_DEFAULT) { 150 printf(" regcs %s %dbit %#x+%#x", 151 __csmap[ca->ca_csreg.cs].cs_name, 152 ca->ca_csreg.cswidth, 153 ca->ca_csreg.csbase, 154 ca->ca_csreg.cssize); 155 } 156 157 if (ca->ca_csio.cs != TXCSBUSCF_IOCS_DEFAULT) { 158 printf(" iocs %s %dbit %#x+%#x", 159 __csmap[ca->ca_csio.cs].cs_name, 160 ca->ca_csio.cswidth, 161 ca->ca_csio.csbase, 162 ca->ca_csio.cssize); 163 } 164 165 if (ca->ca_csmem.cs != TXCSBUSCF_MEMCS_DEFAULT) { 166 printf(" memcs %s %dbit %#x+%#x", 167 __csmap[ca->ca_csmem.cs].cs_name, 168 ca->ca_csmem.cswidth, 169 ca->ca_csmem.csbase, 170 ca->ca_csmem.cssize); 171 } 172 173 if (ca->ca_irq1 != TXCSBUSCF_IRQ1_DEFAULT) { 174 printf(" irq1 %d(%d:%d)", PRINTIRQ(ca->ca_irq1)); 175 } 176 177 if (ca->ca_irq2 != TXCSBUSCF_IRQ2_DEFAULT) { 178 printf(" irq2 %d(%d:%d)", PRINTIRQ(ca->ca_irq2)); 179 } 180 181 if (ca->ca_irq3 != TXCSBUSCF_IRQ3_DEFAULT) { 182 printf(" irq3 %d(%d:%d)", PRINTIRQ(ca->ca_irq3)); 183 } 184 185 return (UNCONF); 186 } 187 188 int 189 txcsbus_search(struct device *parent, struct cfdata *cf, void *aux) 190 { 191 struct txcsbus_softc *sc = (void*)parent; 192 struct cs_attach_args ca; 193 194 ca.ca_tc = sc->sc_tc; 195 196 ca.ca_csreg.cs = cf->cf_loc[TXCSBUSCF_REGCS]; 197 ca.ca_csreg.csbase = cf->cf_loc[TXCSBUSCF_REGCSBASE]; 198 ca.ca_csreg.cssize = cf->cf_loc[TXCSBUSCF_REGCSSIZE]; 199 ca.ca_csreg.cswidth = cf->cf_loc[TXCSBUSCF_REGCSWIDTH]; 200 201 if (ca.ca_csreg.cs != TXCSBUSCF_REGCS_DEFAULT) { 202 ca.ca_csreg.cstag = __txcsbus_alloc_cstag(sc, &ca.ca_csreg); 203 } 204 205 ca.ca_csio.cs = cf->cf_loc[TXCSBUSCF_IOCS]; 206 ca.ca_csio.csbase = cf->cf_loc[TXCSBUSCF_IOCSBASE]; 207 ca.ca_csio.cssize = cf->cf_loc[TXCSBUSCF_IOCSSIZE]; 208 ca.ca_csio.cswidth = cf->cf_loc[TXCSBUSCF_IOCSWIDTH]; 209 210 if (ca.ca_csio.cs != TXCSBUSCF_IOCS_DEFAULT) { 211 ca.ca_csio.cstag = __txcsbus_alloc_cstag(sc, &ca.ca_csio); 212 } 213 214 ca.ca_csmem.cs = cf->cf_loc[TXCSBUSCF_MEMCS]; 215 ca.ca_csmem.csbase = cf->cf_loc[TXCSBUSCF_MEMCSBASE]; 216 ca.ca_csmem.cssize = cf->cf_loc[TXCSBUSCF_MEMCSSIZE]; 217 ca.ca_csmem.cswidth = cf->cf_loc[TXCSBUSCF_MEMCSWIDTH]; 218 219 if (ca.ca_csmem.cs != TXCSBUSCF_MEMCS_DEFAULT) { 220 ca.ca_csmem.cstag = __txcsbus_alloc_cstag(sc, &ca.ca_csmem); 221 } 222 223 ca.ca_irq1 = cf->cf_loc[TXCSBUSCF_IRQ1]; 224 ca.ca_irq2 = cf->cf_loc[TXCSBUSCF_IRQ2]; 225 ca.ca_irq3 = cf->cf_loc[TXCSBUSCF_IRQ3]; 226 227 if (config_match(parent, cf, &ca)) { 228 config_attach(parent, cf, &ca, txcsbus_print); 229 } 230 231 return (0); 232 } 233 234 bus_space_tag_t 235 __txcsbus_alloc_cstag(struct txcsbus_softc *sc, struct cs_handle *csh) 236 { 237 238 tx_chipset_tag_t tc = sc->sc_tc; 239 int cs = csh->cs; 240 int width = csh->cswidth; 241 struct bus_space_tag_hpcmips *iot; 242 txreg_t reg; 243 244 if (!TX39_ISCS(cs) && !TX39_ISMCS(cs) && !TX39_ISCARD(cs)) { 245 panic("txcsbus_alloc_tag: bogus chip select %d", cs); 246 } 247 248 /* Already setuped chip select */ 249 if (sc->sc_cst[cs]) { 250 return (&sc->sc_cst[cs]->bst); 251 } 252 253 iot = hpcmips_alloc_bus_space_tag(); 254 hpcmips_init_bus_space(iot, hpcmips_system_bus_space_hpcmips(), 255 __csmap[cs].cs_name, __csmap[cs].cs_addr, __csmap[cs].cs_size); 256 sc->sc_cst[cs] = iot; 257 258 /* CS bus-width (configurationable) */ 259 switch (width) { 260 default: 261 panic("txcsbus_alloc_tag: bogus bus width %d", width); 262 263 case 32: 264 if (TX39_ISCS(cs)) { 265 reg = tx_conf_read(tc, TX39_MEMCONFIG0_REG); 266 reg |= (1 << cs); 267 tx_conf_write(tc, TX39_MEMCONFIG0_REG, reg); 268 } else if(TX39_ISMCS(cs)) { 269 #ifdef TX391X 270 panic("txcsbus_alloc_tag: MCS is 16bit only"); 271 #endif /* TX391X */ 272 #ifdef TX392X 273 reg = tx_conf_read(tc, TX39_MEMCONFIG1_REG); 274 reg |= ((cs == TX39_MCS0) ? 275 TX39_MEMCONFIG1_MCS0_32 : 276 TX39_MEMCONFIG1_MCS1_32); 277 tx_conf_write(tc, TX39_MEMCONFIG1_REG, reg); 278 #endif /* TX392X */ 279 } 280 break; 281 282 case 16: 283 if (TX39_ISCS(cs)) { 284 reg = tx_conf_read(tc, TX39_MEMCONFIG0_REG); 285 reg &= ~(1 << cs); 286 tx_conf_write(tc, TX39_MEMCONFIG0_REG, reg); 287 } else if(TX39_ISMCS(cs)) { 288 /* TX391X always 16bit port */ 289 #ifdef TX392X 290 reg = tx_conf_read(tc, TX39_MEMCONFIG1_REG); 291 reg &= ~((cs == TX39_MCS0) ? 292 TX39_MEMCONFIG1_MCS0_32 : 293 TX39_MEMCONFIG1_MCS1_32); 294 tx_conf_write(tc, TX39_MEMCONFIG1_REG, reg); 295 #endif /* TX392X */ 296 } else { 297 /* CARD io/attr or mem */ 298 reg = tx_conf_read(tc, TX39_MEMCONFIG3_REG); 299 300 /* enable I/O access */ 301 reg |= (cs == TX39_CARD1) ? 302 TX39_MEMCONFIG3_CARD1IOEN : 303 TX39_MEMCONFIG3_CARD2IOEN; 304 /* disable 8bit access */ 305 #ifdef TX392X 306 reg &= ~((cs == TX39_CARD1) ? 307 TX39_MEMCONFIG3_CARD1_8SEL : 308 TX39_MEMCONFIG3_CARD2_8SEL); 309 #endif /* TX392X */ 310 #ifdef TX391X 311 reg &= ~TX39_MEMCONFIG3_PORT8SEL; 312 #endif /* TX391X */ 313 tx_conf_write(tc, TX39_MEMCONFIG3_REG, reg); 314 } 315 break; 316 317 case 8: 318 if (TX39_ISCARD(cs)) { 319 reg = tx_conf_read(tc, TX39_MEMCONFIG3_REG); 320 321 /* enable I/O access */ 322 reg |= (cs == TX39_CARD1) ? 323 TX39_MEMCONFIG3_CARD1IOEN : 324 TX39_MEMCONFIG3_CARD2IOEN; 325 /* disable 8bit access */ 326 #ifdef TX392X 327 reg |= (cs == TX39_CARD1) ? 328 TX39_MEMCONFIG3_CARD1_8SEL : 329 TX39_MEMCONFIG3_CARD2_8SEL; 330 #endif /* TX392X */ 331 #ifdef TX391X 332 reg |= TX39_MEMCONFIG3_PORT8SEL; 333 #endif /* TX391X */ 334 tx_conf_write(tc, TX39_MEMCONFIG3_REG, reg); 335 336 } else { 337 panic("__txcsbus_alloc_cstag: CS%d 8bit mode is" 338 "not allowed", cs); 339 } 340 } 341 342 return (&iot->bst); 343 } 344
Indexes created Wed Oct 29 20:09:47 GMT 2025