txcsbus.c revision 1.7
1 /* $NetBSD: txcsbus.c,v 1.7 2001/12/02 10:37:54 uch Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 #include "opt_tx39_debug.h" 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/device.h> 43 44 #include <machine/intr.h> 45 #include <machine/bus.h> 46 #include <machine/bus_space_hpcmips.h> 47 48 #include <machine/platid.h> 49 #include <machine/platid_mask.h> 50 51 #include <hpcmips/tx/tx39var.h> 52 #include <hpcmips/tx/txcsbusvar.h> 53 #include <hpcmips/tx/tx39biuvar.h> 54 #include <hpcmips/tx/tx39biureg.h> 55 56 #include "locators.h" 57 58 /* TX39 CS mapping. (nonconfigurationable) */ 59 const struct csmap { 60 char *cs_name; 61 paddr_t cs_addr; 62 psize_t cs_size; 63 } __csmap[] = { 64 [TX39_CS0] = {"CS0(ROM)" , TX39_SYSADDR_CS0 , 65 TX39_SYSADDR_CS_SIZE}, 66 [TX39_CS1] = {"CS1" , TX39_SYSADDR_CS1 , 67 TX39_SYSADDR_CS_SIZE}, 68 [TX39_CS2] = {"CS2" , TX39_SYSADDR_CS2 , 69 TX39_SYSADDR_CS_SIZE}, 70 [TX39_CS3] = {"CS3" , TX39_SYSADDR_CS3 , 71 TX39_SYSADDR_CS_SIZE}, 72 [TX39_MCS0] = {"MCS0" , TX39_SYSADDR_MCS0 , 73 TX39_SYSADDR_MCS_SIZE}, 74 [TX39_MCS1] = {"MCS1" , TX39_SYSADDR_MCS1 , 75 TX39_SYSADDR_MCS_SIZE}, 76 #ifdef TX391X 77 [TX39_MCS2] = {"MCS2" , TX39_SYSADDR_MCS2 , 78 TX39_SYSADDR_MCS_SIZE}, 79 [TX39_MCS3] = {"MCS3" , TX39_SYSADDR_MCS3 , 80 TX39_SYSADDR_MCS_SIZE}, 81 #endif /* TX391X */ 82 [TX39_CARD1] = {"CARD1(io/attr)", TX39_SYSADDR_CARD1 , 83 TX39_SYSADDR_CARD_SIZE}, 84 [TX39_CARD2] = {"CARD2(io/attr)", TX39_SYSADDR_CARD2 , 85 TX39_SYSADDR_CARD_SIZE}, 86 [TX39_CARD1MEM] = {"CARD1(mem)" , TX39_SYSADDR_CARD1MEM , 87 TX39_SYSADDR_CARD_SIZE}, 88 [TX39_CARD2MEM] = {"CARD2(mem)" , TX39_SYSADDR_CARD2MEM , 89 TX39_SYSADDR_CARD_SIZE}, 90 }; 91 92 int txcsbus_match(struct device *, struct cfdata *, void *); 93 void txcsbus_attach(struct device *, struct device *, void *); 94 int txcsbus_print(void *, const char *); 95 int txcsbus_search(struct device *, struct cfdata *, void *); 96 97 struct txcsbus_softc { 98 struct device sc_dev; 99 tx_chipset_tag_t sc_tc; 100 /* chip select space tag */ 101 struct bus_space_tag_hpcmips *sc_cst[TX39_MAXCS]; 102 }; 103 104 struct cfattach txcsbus_ca = { 105 sizeof(struct txcsbus_softc), txcsbus_match, txcsbus_attach 106 }; 107 108 static bus_space_tag_t __txcsbus_alloc_cstag(struct txcsbus_softc *, 109 struct cs_handle *); 110 111 int 112 txcsbus_match(struct device *parent, struct cfdata *cf, void *aux) 113 { 114 struct csbus_attach_args *cba = aux; 115 platid_mask_t mask; 116 117 if (strcmp(cba->cba_busname, cf->cf_driver->cd_name)) 118 return (0); 119 120 if (cf->cf_loc[TXCSBUSIFCF_PLATFORM] == TXCSBUSIFCF_PLATFORM_DEFAULT) 121 return (1); 122 123 mask = PLATID_DEREF(cf->cf_loc[TXCSBUSIFCF_PLATFORM]); 124 if (platid_match(&platid, &mask)) 125 return (2); 126 127 return (0); 128 } 129 130 void 131 txcsbus_attach(struct device *parent, struct device *self, void *aux) 132 { 133 struct csbus_attach_args *cba = aux; 134 struct txcsbus_softc *sc = (void*)self; 135 136 sc->sc_tc = cba->cba_tc; 137 printf("\n"); 138 139 /* 140 * Attach external chip. 141 */ 142 config_search(txcsbus_search, self, txcsbus_print); 143 } 144 145 int 146 txcsbus_print(void *aux, const char *pnp) 147 { 148 #define PRINTIRQ(i) i, (i) / 32, (i) % 32 149 struct cs_attach_args *ca = aux; 150 151 if (ca->ca_csreg.cs != TXCSBUSCF_REGCS_DEFAULT) { 152 printf(" regcs %s %dbit %#x+%#x", 153 __csmap[ca->ca_csreg.cs].cs_name, 154 ca->ca_csreg.cswidth, 155 ca->ca_csreg.csbase, 156 ca->ca_csreg.cssize); 157 } 158 159 if (ca->ca_csio.cs != TXCSBUSCF_IOCS_DEFAULT) { 160 printf(" iocs %s %dbit %#x+%#x", 161 __csmap[ca->ca_csio.cs].cs_name, 162 ca->ca_csio.cswidth, 163 ca->ca_csio.csbase, 164 ca->ca_csio.cssize); 165 } 166 167 if (ca->ca_csmem.cs != TXCSBUSCF_MEMCS_DEFAULT) { 168 printf(" memcs %s %dbit %#x+%#x", 169 __csmap[ca->ca_csmem.cs].cs_name, 170 ca->ca_csmem.cswidth, 171 ca->ca_csmem.csbase, 172 ca->ca_csmem.cssize); 173 } 174 175 if (ca->ca_irq1 != TXCSBUSCF_IRQ1_DEFAULT) { 176 printf(" irq1 %d(%d:%d)", PRINTIRQ(ca->ca_irq1)); 177 } 178 179 if (ca->ca_irq2 != TXCSBUSCF_IRQ2_DEFAULT) { 180 printf(" irq2 %d(%d:%d)", PRINTIRQ(ca->ca_irq2)); 181 } 182 183 if (ca->ca_irq3 != TXCSBUSCF_IRQ3_DEFAULT) { 184 printf(" irq3 %d(%d:%d)", PRINTIRQ(ca->ca_irq3)); 185 } 186 187 return (UNCONF); 188 } 189 190 int 191 txcsbus_search(struct device *parent, struct cfdata *cf, void *aux) 192 { 193 struct txcsbus_softc *sc = (void*)parent; 194 struct cs_attach_args ca; 195 196 ca.ca_tc = sc->sc_tc; 197 198 ca.ca_csreg.cs = cf->cf_loc[TXCSBUSCF_REGCS]; 199 ca.ca_csreg.csbase = cf->cf_loc[TXCSBUSCF_REGCSBASE]; 200 ca.ca_csreg.cssize = cf->cf_loc[TXCSBUSCF_REGCSSIZE]; 201 ca.ca_csreg.cswidth = cf->cf_loc[TXCSBUSCF_REGCSWIDTH]; 202 203 if (ca.ca_csreg.cs != TXCSBUSCF_REGCS_DEFAULT) { 204 ca.ca_csreg.cstag = __txcsbus_alloc_cstag(sc, &ca.ca_csreg); 205 } 206 207 ca.ca_csio.cs = cf->cf_loc[TXCSBUSCF_IOCS]; 208 ca.ca_csio.csbase = cf->cf_loc[TXCSBUSCF_IOCSBASE]; 209 ca.ca_csio.cssize = cf->cf_loc[TXCSBUSCF_IOCSSIZE]; 210 ca.ca_csio.cswidth = cf->cf_loc[TXCSBUSCF_IOCSWIDTH]; 211 212 if (ca.ca_csio.cs != TXCSBUSCF_IOCS_DEFAULT) { 213 ca.ca_csio.cstag = __txcsbus_alloc_cstag(sc, &ca.ca_csio); 214 } 215 216 ca.ca_csmem.cs = cf->cf_loc[TXCSBUSCF_MEMCS]; 217 ca.ca_csmem.csbase = cf->cf_loc[TXCSBUSCF_MEMCSBASE]; 218 ca.ca_csmem.cssize = cf->cf_loc[TXCSBUSCF_MEMCSSIZE]; 219 ca.ca_csmem.cswidth = cf->cf_loc[TXCSBUSCF_MEMCSWIDTH]; 220 221 if (ca.ca_csmem.cs != TXCSBUSCF_MEMCS_DEFAULT) { 222 ca.ca_csmem.cstag = __txcsbus_alloc_cstag(sc, &ca.ca_csmem); 223 } 224 225 ca.ca_irq1 = cf->cf_loc[TXCSBUSCF_IRQ1]; 226 ca.ca_irq2 = cf->cf_loc[TXCSBUSCF_IRQ2]; 227 ca.ca_irq3 = cf->cf_loc[TXCSBUSCF_IRQ3]; 228 229 if ((*cf->cf_attach->ca_match)(parent, cf, &ca)) { 230 config_attach(parent, cf, &ca, txcsbus_print); 231 } 232 233 return (0); 234 } 235 236 bus_space_tag_t 237 __txcsbus_alloc_cstag(struct txcsbus_softc *sc, struct cs_handle *csh) 238 { 239 240 tx_chipset_tag_t tc = sc->sc_tc; 241 int cs = csh->cs; 242 int width = csh->cswidth; 243 struct bus_space_tag_hpcmips *iot; 244 txreg_t reg; 245 246 if (!TX39_ISCS(cs) && !TX39_ISMCS(cs) && !TX39_ISCARD(cs)) { 247 panic("txcsbus_alloc_tag: bogus chip select %d\n", cs); 248 } 249 250 /* Already setuped chip select */ 251 if (sc->sc_cst[cs]) { 252 return (&sc->sc_cst[cs]->bst); 253 } 254 255 iot = hpcmips_alloc_bus_space_tag(); 256 hpcmips_init_bus_space(iot, hpcmips_system_bus_space_hpcmips(), 257 __csmap[cs].cs_name, __csmap[cs].cs_addr, __csmap[cs].cs_size); 258 sc->sc_cst[cs] = iot; 259 260 /* CS bus-width (configurationable) */ 261 switch (width) { 262 default: 263 panic("txcsbus_alloc_tag: bogus bus width %d\n", width); 264 265 case 32: 266 if (TX39_ISCS(cs)) { 267 reg = tx_conf_read(tc, TX39_MEMCONFIG0_REG); 268 reg |= (1 << cs); 269 tx_conf_write(tc, TX39_MEMCONFIG0_REG, reg); 270 } else if(TX39_ISMCS(cs)) { 271 #ifdef TX391X 272 panic("txcsbus_alloc_tag: MCS is 16bit only"); 273 #endif /* TX391X */ 274 #ifdef TX392X 275 reg = tx_conf_read(tc, TX39_MEMCONFIG1_REG); 276 reg |= ((cs == TX39_MCS0) ? 277 TX39_MEMCONFIG1_MCS0_32 : 278 TX39_MEMCONFIG1_MCS1_32); 279 tx_conf_write(tc, TX39_MEMCONFIG1_REG, reg); 280 #endif /* TX392X */ 281 } 282 break; 283 284 case 16: 285 if (TX39_ISCS(cs)) { 286 reg = tx_conf_read(tc, TX39_MEMCONFIG0_REG); 287 reg &= ~(1 << cs); 288 tx_conf_write(tc, TX39_MEMCONFIG0_REG, reg); 289 } else if(TX39_ISMCS(cs)) { 290 /* TX391X always 16bit port */ 291 #ifdef TX392X 292 reg = tx_conf_read(tc, TX39_MEMCONFIG1_REG); 293 reg &= ~((cs == TX39_MCS0) ? 294 TX39_MEMCONFIG1_MCS0_32 : 295 TX39_MEMCONFIG1_MCS1_32); 296 tx_conf_write(tc, TX39_MEMCONFIG1_REG, reg); 297 #endif /* TX392X */ 298 } else { 299 /* CARD io/attr or mem */ 300 reg = tx_conf_read(tc, TX39_MEMCONFIG3_REG); 301 302 /* enable I/O access */ 303 reg |= (cs == TX39_CARD1) ? 304 TX39_MEMCONFIG3_CARD1IOEN : 305 TX39_MEMCONFIG3_CARD2IOEN; 306 /* disable 8bit access */ 307 #ifdef TX392X 308 reg &= ~((cs == TX39_CARD1) ? 309 TX39_MEMCONFIG3_CARD1_8SEL : 310 TX39_MEMCONFIG3_CARD2_8SEL); 311 #endif /* TX392X */ 312 #ifdef TX391X 313 reg &= ~TX39_MEMCONFIG3_PORT8SEL; 314 #endif /* TX391X */ 315 tx_conf_write(tc, TX39_MEMCONFIG3_REG, reg); 316 } 317 break; 318 319 case 8: 320 if (TX39_ISCARD(cs)) { 321 reg = tx_conf_read(tc, TX39_MEMCONFIG3_REG); 322 323 /* enable I/O access */ 324 reg |= (cs == TX39_CARD1) ? 325 TX39_MEMCONFIG3_CARD1IOEN : 326 TX39_MEMCONFIG3_CARD2IOEN; 327 /* disable 8bit access */ 328 #ifdef TX392X 329 reg |= (cs == TX39_CARD1) ? 330 TX39_MEMCONFIG3_CARD1_8SEL : 331 TX39_MEMCONFIG3_CARD2_8SEL; 332 #endif /* TX392X */ 333 #ifdef TX391X 334 reg |= TX39_MEMCONFIG3_PORT8SEL; 335 #endif /* TX391X */ 336 tx_conf_write(tc, TX39_MEMCONFIG3_REG, reg); 337 338 } else { 339 panic("__txcsbus_alloc_cstag: CS%d 8bit mode is" 340 "not allowed", cs); 341 } 342 } 343 344 return (&iot->bst); 345 } 346
Indexes created Wed Oct 29 20:09:47 GMT 2025