bcu_vrip.c revision 1.13
1 /* $NetBSD: bcu_vrip.c,v 1.13 2002/01/26 10:50:44 takemura Exp $ */ 2 3 /*- 4 * Copyright (c) 1999-2001 SATO Kazumi. All rights reserved. 5 * Copyright (c) 1999 PocketBSD Project. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the PocketBSD project 18 * and its contributors. 19 * 4. Neither the name of the project nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 */ 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/device.h> 40 #include <sys/reboot.h> 41 42 #include <machine/bus.h> 43 #include <machine/bitdisp.h> 44 45 #include <mips/cpuregs.h> 46 47 #include "opt_vr41xx.h" 48 #include <hpcmips/vr/vr.h> 49 #include <hpcmips/vr/vrcpudef.h> 50 #include <hpcmips/vr/vripvar.h> 51 #include <hpcmips/vr/vripreg.h> 52 #include <hpcmips/vr/bcureg.h> 53 #include <hpcmips/vr/bcuvar.h> 54 55 static int vrbcu_match(struct device *, struct cfdata *, void *); 56 static void vrbcu_attach(struct device *, struct device *, void *); 57 58 static void vrbcu_write(struct vrbcu_softc *, int, unsigned short); 59 static unsigned short vrbcu_read(struct vrbcu_softc *, int); 60 61 static void vrbcu_dump_regs(void); 62 63 char *vr_cpuname=NULL; 64 int vr_major=-1; 65 int vr_minor=-1; 66 int vr_cpuid=-1; 67 68 struct cfattach vrbcu_ca = { 69 sizeof(struct vrbcu_softc), vrbcu_match, vrbcu_attach 70 }; 71 72 struct vrbcu_softc *the_bcu_sc = NULL; 73 74 static inline void 75 vrbcu_write(struct vrbcu_softc *sc, int port, unsigned short val) 76 { 77 78 bus_space_write_2(sc->sc_iot, sc->sc_ioh, port, val); 79 } 80 81 static inline unsigned short 82 vrbcu_read(struct vrbcu_softc *sc, int port) 83 { 84 85 return (bus_space_read_2(sc->sc_iot, sc->sc_ioh, port)); 86 } 87 88 static int 89 vrbcu_match(struct device *parent, struct cfdata *cf, void *aux) 90 { 91 92 return (2); 93 } 94 95 static void 96 vrbcu_attach(struct device *parent, struct device *self, void *aux) 97 { 98 struct vrip_attach_args *va = aux; 99 struct vrbcu_softc *sc = (struct vrbcu_softc *)self; 100 101 sc->sc_iot = va->va_iot; 102 bus_space_map(sc->sc_iot, va->va_addr, va->va_size, 103 0, /* no flags */ 104 &sc->sc_ioh); 105 106 printf("\n"); 107 the_bcu_sc = sc; 108 vrbcu_dump_regs(); 109 } 110 111 static void 112 vrbcu_dump_regs() 113 { 114 struct vrbcu_softc *sc = the_bcu_sc; 115 int cpuclock = 0, tclock = 0, vtclock = 0, cpuid; 116 #if !defined(ONLY_VR4102) 117 int spdreg; 118 #endif 119 #ifdef VRBCUDEBUG 120 int reg; 121 #endif /* VRBCUDEBUG */ 122 123 cpuid = vrbcu_vrip_getcpuid(); 124 #if !defined(ONLY_VR4181) && !defined(ONLY_VR4102) 125 if (cpuid != BCUREVID_FIXRID_4181 126 && cpuid <= BCUREVID_RID_4131 127 && cpuid >= BCUREVID_RID_4111) { 128 spdreg = vrbcu_read(sc, BCUCLKSPEED_REG_W); 129 #ifdef VRBCUDEBUG 130 printf("vrbcu: CLKSPEED %x: \n", spdreg); 131 #endif /* VRBCUDEBUG */ 132 } 133 #endif 134 #if defined VR4181 135 if (cpuid == BCUREVID_FIXRID_4181){ 136 spdreg = vrbcu_read(sc, BCU81CLKSPEED_REG_W); 137 #ifdef VRBCUDEBUG 138 printf("vrbcu: CLKSPEED %x: \n", spdreg); 139 #endif /* VRBCUDEBUG */ 140 } 141 #endif 142 143 cpuclock = vrbcu_vrip_getcpuclock(); 144 145 switch (cpuid) { 146 #if defined VR4181 147 case BCUREVID_FIXRID_4181: 148 switch ((spdreg & BCU81CLKSPEED_DIVTMASK) >> 149 BCU81CLKSPEED_DIVTSHFT){ 150 case BCU81CLKSPEED_DIVT1: 151 vtclock = tclock = cpuclock; 152 break; 153 case BCU81CLKSPEED_DIVT2: 154 vtclock = tclock = cpuclock/2; 155 break; 156 case BCU81CLKSPEED_DIVT3: 157 vtclock = tclock = cpuclock/3; 158 break; 159 case BCU81CLKSPEED_DIVT4: 160 vtclock = tclock = cpuclock/4; 161 break; 162 default: 163 vtclock = tclock = 0; 164 } 165 break; 166 #endif /* VR4181 */ 167 case BCUREVID_RID_4101: 168 case BCUREVID_RID_4102: 169 vtclock = tclock = cpuclock/2; 170 break; 171 #if defined VR4111 172 case BCUREVID_RID_4111: 173 if ((spdreg&BCUCLKSPEED_DIVT2B) == 0) 174 vtclock = tclock = cpuclock/2; 175 else if ((spdreg&BCUCLKSPEED_DIVT3B) == 0) 176 vtclock = tclock = cpuclock/3; 177 else if ((spdreg&BCUCLKSPEED_DIVT4B) == 0) 178 vtclock = tclock = cpuclock/4; 179 else 180 vtclock = tclock = 0; /* XXX */ 181 break; 182 #endif /* VR4111 */ 183 #if defined VR4121 184 case BCUREVID_RID_4121: 185 { 186 int vt; 187 tclock = cpuclock / ((spdreg & BCUCLKSPEED_DIVTMASK) >> 188 BCUCLKSPEED_DIVTSHFT); 189 vt = ((spdreg & BCUCLKSPEED_DIVVTMASK) >> 190 BCUCLKSPEED_DIVVTSHFT); 191 if (vt == 0) 192 vtclock = 0; /* XXX */ 193 else if (vt < 0x9) 194 vtclock = cpuclock / vt; 195 else 196 vtclock = cpuclock / ((vt - 8)*2+1) * 2; 197 } 198 break; 199 #endif /* VR4121 */ 200 #if defined VR4122 || defined VR4131 201 case BCUREVID_RID_4122: 202 case BCUREVID_RID_4131: 203 { 204 int vtdiv; 205 206 vtdiv = ((spdreg & BCUCLKSPEED_VTDIVMODE) >> 207 BCUCLKSPEED_VTDIVSHFT); 208 if (vtdiv == 0 || vtdiv > BCUCLKSPEED_VTDIV6) 209 vtclock = 0; /* XXX */ 210 else 211 vtclock = cpuclock / vtdiv; 212 tclock = vtclock / 213 (((spdreg & BCUCLKSPEED_TDIVMODE) >> 214 BCUCLKSPEED_TDIVSHFT) ? 4 : 2); 215 } 216 break; 217 #endif /* VR4122 || VR4131 */ 218 default: 219 break; 220 } 221 if (tclock) 222 printf("%s: cpu %d.%03dMHz, bus %d.%03dMHz, ram %d.%03dMHz\n", 223 sc->sc_dev.dv_xname, 224 cpuclock/1000000, (cpuclock%1000000)/1000, 225 tclock/1000000, (tclock%1000000)/1000, 226 vtclock/1000000, (vtclock%1000000)/1000); 227 else { 228 printf("%s: cpu %d.%03dMHz\n", 229 sc->sc_dev.dv_xname, 230 cpuclock/1000000, (cpuclock%1000000)/1000); 231 printf("%s: UNKNOWN BUS CLOCK SPEED:" 232 " CPU is UNKNOWN or NOT CONFIGURED\n", 233 sc->sc_dev.dv_xname); 234 } 235 #ifdef VRBCUDEBUG 236 reg = vrbcu_read(sc, BCUCNT1_REG_W); 237 printf("vrbcu: CNT1 %x: ", reg); 238 bitdisp16(reg); 239 #if !defined(ONLY_VR4181) 240 if (cpuid != BCUREVID_FIXRID_4181 241 && cpuid <= BCUREVID_RID_4121 242 && cpuid >= BCUREVID_RID_4102) { 243 reg = vrbcu_read(sc, BCUCNT2_REG_W); 244 printf("vrbcu: CNT2 %x: ", reg); 245 bitdisp16(reg); 246 } 247 #endif /* !defined ONLY_VR4181 */ 248 #if !defined(ONLY_VR4181) || !defined(ONLY_VR4122_4131) 249 if (cpuid != BCUREVID_FIXRID_4181 250 && cpuid <= BCUREVID_RID_4121 251 && cpuid >= BCUREVID_RID_4102) { 252 reg = vrbcu_read(sc, BCUSPEED_REG_W); 253 printf("vrbcu: SPEED %x: ", reg); 254 bitdisp16(reg); 255 reg = vrbcu_read(sc, BCUERRST_REG_W); 256 printf("vrbcu: ERRST %x: ", reg); 257 bitdisp16(reg); 258 reg = vrbcu_read(sc, BCURFCNT_REG_W); 259 printf("vrbcu: RFCNT %x\n", reg); 260 reg = vrbcu_read(sc, BCUREFCOUNT_REG_W); 261 printf("vrbcu: RFCOUNT %x\n", reg); 262 } 263 #endif /* !defined(ONLY_VR4181) || !defined(ONLY_VR4122_4131) */ 264 #if !defined(ONLY_VR4181) 265 if (cpuid != BCUREVID_FIXRID_4181 266 && cpuid <= BCUREVID_RID_4131 267 && cpuid >= BCUREVID_RID_4111) 268 { 269 reg = vrbcu_read(sc, BCUCNT3_REG_W); 270 printf("vrbcu: CNT3 %x: ", reg); 271 bitdisp16(reg); 272 } 273 #endif /* !defined ONLY_VR4181 */ 274 #endif /* VRBCUDEBUG */ 275 276 } 277 278 static char *cpuname[] = { 279 "VR4101", /* 0 */ 280 "VR4102", /* 1 */ 281 "VR4111", /* 2 */ 282 "VR4121", /* 3 */ 283 "VR4122", /* 4 */ 284 "VR4131", /* 5 */ 285 "UNKNOWN", 286 "UNKNOWN", 287 "UNKNOWN", 288 "UNKNOWN", 289 "UNKNOWN", 290 "UNKNOWN", 291 "UNKNOWN", 292 "UNKNOWN", 293 "UNKNOWN", 294 "UNKNOWN", 295 "VR4181", /* 0x10 + 0 */ 296 }; 297 298 int 299 vrbcu_vrip_getcpuid(void) 300 { 301 volatile u_int16_t *revreg; 302 303 if (vr_cpuid != -1) 304 return (vr_cpuid); 305 306 if (vr_cpuid == -1) { 307 if (VRIP_BCU_ADDR == VR4181_BCU_ADDR) 308 revreg = (u_int16_t *)MIPS_PHYS_TO_KSEG1 309 ((VRIP_BCU_ADDR+BCU81REVID_REG_W)); 310 else 311 revreg = (u_int16_t *)MIPS_PHYS_TO_KSEG1 312 ((VRIP_BCU_ADDR+BCUREVID_REG_W)); 313 314 vr_cpuid = *revreg; 315 vr_cpuid = (vr_cpuid&BCUREVID_RIDMASK)>>BCUREVID_RIDSHFT; 316 if (VRIP_BCU_ADDR == VR4181_BCU_ADDR 317 && vr_cpuid == BCUREVID_RID_4181) /* conflict vr4101 */ 318 vr_cpuid = BCUREVID_FIXRID_4181; 319 } 320 return (vr_cpuid); 321 } 322 323 char * 324 vrbcu_vrip_getcpuname(void) 325 { 326 int cpuid; 327 328 if (vr_cpuname != NULL) 329 return (vr_cpuname); 330 331 cpuid = vrbcu_vrip_getcpuid(); 332 vr_cpuname = cpuname[cpuid]; 333 334 return (vr_cpuname); 335 } 336 337 338 int 339 vrbcu_vrip_getcpumajor(void) 340 { 341 volatile u_int16_t *revreg; 342 343 if (vr_major != -1) 344 return (vr_major); 345 346 revreg = (u_int16_t *)MIPS_PHYS_TO_KSEG1 347 ((VRIP_BCU_ADDR+BCUREVID_REG_W)); 348 349 vr_major = *revreg; 350 vr_major = (vr_major&BCUREVID_MJREVMASK)>>BCUREVID_MJREVSHFT; 351 352 return (vr_major); 353 } 354 355 int 356 vrbcu_vrip_getcpuminor(void) 357 { 358 volatile u_int16_t *revreg; 359 360 if (vr_minor != -1) 361 return (vr_minor); 362 363 revreg = (u_int16_t *)MIPS_PHYS_TO_KSEG1 364 ((VRIP_BCU_ADDR+BCUREVID_REG_W)); 365 366 vr_minor = *revreg; 367 vr_minor = (vr_minor&BCUREVID_MNREVMASK)>>BCUREVID_MNREVSHFT; 368 369 return (vr_minor); 370 } 371 372 #define CLKX 18432000 /* CLKX1,CLKX2: 18.432MHz */ 373 #define MHZ 1000000 374 375 int 376 vrbcu_vrip_getcpuclock(void) 377 { 378 u_int16_t clksp; 379 int cpuid, cpuclock; 380 381 cpuid = vrbcu_vrip_getcpuid(); 382 if (cpuid != BCUREVID_FIXRID_4181 && cpuid >= BCUREVID_RID_4111) { 383 clksp = *(u_int16_t *)MIPS_PHYS_TO_KSEG1 384 ((VRIP_BCU_ADDR+BCUCLKSPEED_REG_W)) & 385 BCUCLKSPEED_CLKSPMASK; 386 } else if (cpuid == BCUREVID_FIXRID_4181) { 387 clksp = *(u_int16_t *)MIPS_PHYS_TO_KSEG1 388 ((VRIP_BCU_ADDR+BCU81CLKSPEED_REG_W)) & 389 BCUCLKSPEED_CLKSPMASK; 390 } 391 392 switch (cpuid) { 393 case BCUREVID_FIXRID_4181: 394 cpuclock = CLKX / clksp * 64; 395 /* branch delay is 1 clock; 2 clock/loop */ 396 cpuspeed = (cpuclock / 2 + MHZ / 2) / MHZ; 397 break; 398 case BCUREVID_RID_4101: 399 /* assume 33MHz */ 400 cpuclock = 33000000; 401 /* branch delay is 1 clock; 2 clock/loop */ 402 cpuspeed = (cpuclock / 2 + MHZ / 2) / MHZ; 403 break; 404 case BCUREVID_RID_4102: 405 cpuclock = CLKX / clksp * 32; 406 /* branch delay is 1 clock; 2 clock/loop */ 407 cpuspeed = (cpuclock / 2 + MHZ / 2) / MHZ; 408 break; 409 case BCUREVID_RID_4111: 410 cpuclock = CLKX / clksp * 64; 411 /* branch delay is 1 clock; 2 clock/loop */ 412 cpuspeed = (cpuclock / 2 + MHZ / 2) / MHZ; 413 break; 414 case BCUREVID_RID_4121: 415 cpuclock = CLKX / clksp * 64; 416 /* branch delay is 2 clock; 3 clock/loop */ 417 cpuspeed = (cpuclock / 3 + MHZ / 2) / MHZ; 418 break; 419 case BCUREVID_RID_4122: 420 cpuclock = CLKX / clksp * 98; 421 /* branch delay is 2 clock; 3 clock/loop */ 422 cpuspeed = (cpuclock / 3 + MHZ / 2) / MHZ; 423 break; 424 case BCUREVID_RID_4131: 425 cpuclock = CLKX / clksp * 98; 426 /* branch delay is 2 clock; 3 clock/loop */ 427 cpuspeed = (cpuclock / 3 + MHZ / 2) / MHZ; 428 break; 429 default: 430 panic("unknown CPU type %d\n", cpuid); 431 break; 432 } 433 434 return (cpuclock); 435 } 436
Indexes created Mon Sep 29 21:09:56 GMT 2025