bcu_vrip.c revision 1.7
1 /* $NetBSD: bcu_vrip.c,v 1.7 2001/04/18 11:07:26 sato Exp $ */ 2 3 /*- 4 * Copyright (c) 1999-2001 SATO Kazumi. All rights reserved. 5 * Copyright (c) 1999 PocketBSD Project. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the PocketBSD project 18 * and its contributors. 19 * 4. Neither the name of the project nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 */ 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/device.h> 40 #include <sys/reboot.h> 41 42 #include <machine/bus.h> 43 44 #include <mips/cpuregs.h> 45 46 #include "opt_vr41xx.h" 47 #include <hpcmips/vr/vr.h> 48 #include <hpcmips/vr/vrcpudef.h> 49 #include <hpcmips/vr/vripvar.h> 50 #include <hpcmips/vr/vripreg.h> 51 #include <hpcmips/vr/bcureg.h> 52 #include <hpcmips/vr/bcuvar.h> 53 54 static int vrbcu_match __P((struct device *, struct cfdata *, void *)); 55 static void vrbcu_attach __P((struct device *, struct device *, void *)); 56 57 static void vrbcu_write __P((struct vrbcu_softc *, int, unsigned short)); 58 static unsigned short vrbcu_read __P((struct vrbcu_softc *, int)); 59 60 static void vrbcu_dump_regs __P((void)); 61 62 char *vr_cpuname=NULL; 63 int vr_major=-1; 64 int vr_minor=-1; 65 int vr_cpuid=-1; 66 67 struct cfattach vrbcu_ca = { 68 sizeof(struct vrbcu_softc), vrbcu_match, vrbcu_attach 69 }; 70 71 struct vrbcu_softc *the_bcu_sc = NULL; 72 73 static inline void 74 vrbcu_write(sc, port, val) 75 struct vrbcu_softc *sc; 76 int port; 77 unsigned short val; 78 { 79 bus_space_write_2(sc->sc_iot, sc->sc_ioh, port, val); 80 } 81 82 static inline unsigned short 83 vrbcu_read(sc, port) 84 struct vrbcu_softc *sc; 85 int port; 86 { 87 return bus_space_read_2(sc->sc_iot, sc->sc_ioh, port); 88 } 89 90 static int 91 vrbcu_match(parent, cf, aux) 92 struct device *parent; 93 struct cfdata *cf; 94 void *aux; 95 { 96 return 2; 97 } 98 99 static void 100 vrbcu_attach(parent, self, aux) 101 struct device *parent; 102 struct device *self; 103 void *aux; 104 { 105 struct vrip_attach_args *va = aux; 106 struct vrbcu_softc *sc = (struct vrbcu_softc *)self; 107 108 sc->sc_iot = va->va_iot; 109 bus_space_map(sc->sc_iot, va->va_addr, va->va_size, 110 0, /* no flags */ 111 &sc->sc_ioh); 112 113 printf("\n"); 114 the_bcu_sc = sc; 115 vrbcu_dump_regs(); 116 } 117 118 static void 119 vrbcu_dump_regs() 120 { 121 struct vrbcu_softc *sc = the_bcu_sc; 122 int cpuclock = 0, tclock = 0, vtclock = 0, cpuid; 123 #if !defined(ONLY_VR4181) && !defined(ONLY_VR4102) && defined VRGROUP_4111_4122 124 int spdreg; 125 #endif 126 #ifdef VRBCUDEBUG 127 int reg; 128 #endif /* VRBCUDEBUG */ 129 130 cpuid = vrbcu_vrip_getcpuid(); 131 #if !defined(ONLY_VR4181) && !defined(ONLY_VR4102) && defined VRGROUP_4111_4122 132 if (cpuid != BCUREVID_FIXRID_4181 133 && cpuid <= BCUREVID_RID_4122 134 && cpuid >= BCUREVID_RID_4111) { 135 spdreg = vrbcu_read(sc, BCUCLKSPEED_REG_W); 136 #ifdef VRBCUDEBUG 137 printf("vrbcu: CLKSPEED %x: \n", spdreg); 138 #endif /* VRBCUDEBUG */ 139 } 140 #endif 141 142 cpuclock = vrbcu_vrip_getcpuclock(); 143 144 switch (cpuid) { 145 case BCUREVID_FIXRID_4181: 146 case BCUREVID_RID_4101: 147 case BCUREVID_RID_4102: 148 vtclock = tclock = cpuclock/2; 149 break; 150 #if defined VR4111 151 case BCUREVID_RID_4111: 152 if ((spdreg&BCUCLKSPEED_DIVT2B) == 0) 153 vtclock = tclock = cpuclock/2; 154 else if ((spdreg&BCUCLKSPEED_DIVT3B) == 0) 155 vtclock = tclock = cpuclock/3; 156 else if ((spdreg&BCUCLKSPEED_DIVT4B) == 0) 157 vtclock = tclock = cpuclock/4; 158 else 159 vtclock = tclock = 0; /* XXX */ 160 break; 161 #endif /* VR4111 */ 162 #if defined VR4121 163 case BCUREVID_RID_4121: 164 { 165 int vt; 166 tclock = cpuclock / ((spdreg&BCUCLKSPEED_DIVTMASK)>>BCUCLKSPEED_DIVTSHFT); 167 vt = ((spdreg&BCUCLKSPEED_DIVVTMASK)>>BCUCLKSPEED_DIVVTSHFT); 168 if (vt == 0) 169 vtclock = 0; /* XXX */ 170 else if (vt < 0x9) 171 vtclock = cpuclock / vt; 172 else 173 vtclock = cpuclock / ((vt - 8)*2+1) * 2; 174 } 175 break; 176 #endif /* VR4121 */ 177 default: 178 break; 179 } 180 if (tclock) 181 printf("%s: cpu %d.%03dMHz, bus %d.%03dMHz, ram %d.%03dMHz\n", 182 sc->sc_dev.dv_xname, 183 cpuclock/1000000, (cpuclock%1000000)/1000, 184 tclock/1000000, (tclock%1000000)/1000, 185 vtclock/1000000, (vtclock%1000000)/1000); 186 else { 187 printf("%s: cpu %d.%03dMHz\n", 188 sc->sc_dev.dv_xname, 189 cpuclock/1000000, (cpuclock%1000000)/1000); 190 printf("%s: UNKNOWN BUS CLOCK SPEED: CPU is UNKNOWN or NOT CONFIGURED\n", 191 sc->sc_dev.dv_xname); 192 } 193 #ifdef VRBCUDEBUG 194 reg = vrbcu_read(sc, BCUCNT1_REG_W); 195 printf("vrbcu: CNT1 %x: ", reg); 196 bitdisp16(reg); 197 #if !defined(ONLY_VR4181) 198 if (cpuid != BCUREVID_FIXRID_4181 199 && cpuid <= BCUREVID_RID_4121 200 && cpuid >= BCUREVID_RID_4102) { 201 reg = vrbcu_read(sc, BCUCNT2_REG_W); 202 printf("vrbcu: CNT2 %x: ", reg); 203 bitdisp16(reg); 204 } 205 #endif /* !defined ONLY_VR4181 */ 206 #if !defined(ONLY_VR4181) || !defined(ONLY_VR4122) 207 if (cpuid != BCUREVID_FIXRID_4181 208 && cpuid <= BCUREVID_RID_4121 209 && cpuid >= BCUREVID_RID_4102) { 210 reg = vrbcu_read(sc, BCUSPEED_REG_W); 211 printf("vrbcu: SPEED %x: ", reg); 212 bitdisp16(reg); 213 reg = vrbcu_read(sc, BCUERRST_REG_W); 214 printf("vrbcu: ERRST %x: ", reg); 215 bitdisp16(reg); 216 reg = vrbcu_read(sc, BCURFCNT_REG_W); 217 printf("vrbcu: RFCNT %x\n", reg); 218 reg = vrbcu_read(sc, BCUREFCOUNT_REG_W); 219 printf("vrbcu: RFCOUNT %x\n", reg); 220 } 221 #endif /* !defined(ONLY_VR4181) || !defined(ONLY_VR4122) */ 222 #if !defined(ONLY_VR4181) 223 if (cpuid != BCUREVID_FIXRID_4181 224 && cpuid <= BCUREVID_RID_4122 225 && cpuid >= BCUREVID_RID_4111) 226 { 227 reg = vrbcu_read(sc, BCUCNT3_REG_W); 228 printf("vrbcu: CNT3 %x: ", reg); 229 bitdisp16(reg); 230 } 231 #endif /* !defined ONLY_VR4181 */ 232 #endif /* VRBCUDEBUG */ 233 234 } 235 236 static char *cpuname[] = { 237 "VR4101", /* 0 */ 238 "VR4102", /* 1 */ 239 "VR4111", /* 2 */ 240 "VR4121", /* 3 */ 241 "VR4122", /* 4 */ 242 "UNKNOWN", 243 "UNKNOWN", 244 "UNKNOWN", 245 "UNKNOWN", 246 "UNKNOWN", 247 "UNKNOWN", 248 "UNKNOWN", 249 "UNKNOWN", 250 "UNKNOWN", 251 "UNKNOWN", 252 "UNKNOWN", 253 "VR4181", /* 0x10 + 0 */ 254 }; 255 256 int 257 vrbcu_vrip_getcpuid(void) 258 { 259 volatile u_int16_t *revreg; 260 261 if (vr_cpuid != -1) 262 return vr_cpuid; 263 264 if (vr_cpuid == -1) { 265 revreg = (u_int16_t *)MIPS_PHYS_TO_KSEG1((VRIP_BCU_ADDR+BCUREVID_REG_W)); 266 267 vr_cpuid = *revreg; 268 vr_cpuid = (vr_cpuid&BCUREVID_RIDMASK)>>BCUREVID_RIDSHFT; 269 #if !defined(VR4101) && defined(VR4181) 270 if (vr_cpuid == BCUREVID_RID_4181) /* conflict vr4101 */ 271 vr_cpuid = BCUREVID_FIXRID_4181; 272 #endif /* !defined(VR4101) && defined(VR4181) */ 273 } 274 return vr_cpuid; 275 } 276 277 char * 278 vrbcu_vrip_getcpuname(void) 279 { 280 int cpuid; 281 282 if (vr_cpuname != NULL) 283 return vr_cpuname; 284 285 cpuid = vrbcu_vrip_getcpuid(); 286 vr_cpuname = cpuname[cpuid]; 287 return vr_cpuname; 288 } 289 290 291 int 292 vrbcu_vrip_getcpumajor(void) 293 { 294 volatile u_int16_t *revreg; 295 296 if (vr_major != -1) 297 return vr_major; 298 299 revreg = (u_int16_t *)MIPS_PHYS_TO_KSEG1((VRIP_BCU_ADDR+BCUREVID_REG_W)); 300 301 vr_major = *revreg; 302 vr_major = (vr_major&BCUREVID_MJREVMASK)>>BCUREVID_MJREVSHFT; 303 return vr_major; 304 } 305 306 int 307 vrbcu_vrip_getcpuminor(void) 308 { 309 volatile u_int16_t *revreg; 310 311 if (vr_minor != -1) 312 return vr_minor; 313 314 revreg = (u_int16_t *)MIPS_PHYS_TO_KSEG1((VRIP_BCU_ADDR+BCUREVID_REG_W)); 315 316 vr_minor = *revreg; 317 vr_minor = (vr_minor&BCUREVID_MNREVMASK)>>BCUREVID_MNREVSHFT; 318 return vr_minor; 319 } 320 321 #define CLKX 18432000 /* CLKX1,CLKX2: 18.432MHz */ 322 #define MHZ 1000000 323 324 int 325 vrbcu_vrip_getcpuclock(void) 326 { 327 u_int16_t clksp; 328 int cpuid, cpuclock; 329 330 cpuid = vrbcu_vrip_getcpuid(); 331 if (cpuid != BCUREVID_FIXRID_4181 && cpuid >= BCUREVID_RID_4111) { 332 clksp = *(u_int16_t *)MIPS_PHYS_TO_KSEG1((VRIP_BCU_ADDR+BCUCLKSPEED_REG_W)) & BCUCLKSPEED_CLKSPMASK; 333 } 334 335 switch (cpuid) { 336 case BCUREVID_FIXRID_4181: 337 /* assume 66MHz */ 338 cpuclock = 66000000; 339 /* branch delay is 1 clock; 2 clock/loop */ 340 cpuspeed = (cpuclock / 2 + MHZ / 2) / MHZ; 341 break; 342 case BCUREVID_RID_4101: 343 /* assume 33MHz */ 344 cpuclock = 33000000; 345 /* branch delay is 1 clock; 2 clock/loop */ 346 cpuspeed = (cpuclock / 2 + MHZ / 2) / MHZ; 347 break; 348 case BCUREVID_RID_4102: 349 cpuclock = CLKX / clksp * 32; 350 /* branch delay is 1 clock; 2 clock/loop */ 351 cpuspeed = (cpuclock / 2 + MHZ / 2) / MHZ; 352 break; 353 case BCUREVID_RID_4111: 354 cpuclock = CLKX / clksp * 64; 355 /* branch delay is 1 clock; 2 clock/loop */ 356 cpuspeed = (cpuclock / 2 + MHZ / 2) / MHZ; 357 break; 358 case BCUREVID_RID_4121: 359 cpuclock = CLKX / clksp * 64; 360 /* branch delay is 2 clock; 3 clock/loop */ 361 cpuspeed = (cpuclock / 3 + MHZ / 2) / MHZ; 362 break; 363 default: 364 panic("unknown CPU type %d\n", cpuid); 365 break; 366 } 367 return cpuclock; 368 } 369
Indexes created Sun Sep 28 16:09:52 GMT 2025