bcu_vrip.c revision 1.8
1 /* $NetBSD: bcu_vrip.c,v 1.8 2001/04/21 14:44:40 sato Exp $ */ 2 3 /*- 4 * Copyright (c) 1999-2001 SATO Kazumi. All rights reserved. 5 * Copyright (c) 1999 PocketBSD Project. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the PocketBSD project 18 * and its contributors. 19 * 4. Neither the name of the project nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 */ 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/device.h> 40 #include <sys/reboot.h> 41 42 #include <machine/bus.h> 43 44 #include <mips/cpuregs.h> 45 46 #include "opt_vr41xx.h" 47 #include <hpcmips/vr/vr.h> 48 #include <hpcmips/vr/vrcpudef.h> 49 #include <hpcmips/vr/vripvar.h> 50 #include <hpcmips/vr/vripreg.h> 51 #include <hpcmips/vr/bcureg.h> 52 #include <hpcmips/vr/bcuvar.h> 53 54 static int vrbcu_match __P((struct device *, struct cfdata *, void *)); 55 static void vrbcu_attach __P((struct device *, struct device *, void *)); 56 57 static void vrbcu_write __P((struct vrbcu_softc *, int, unsigned short)); 58 static unsigned short vrbcu_read __P((struct vrbcu_softc *, int)); 59 60 static void vrbcu_dump_regs __P((void)); 61 62 char *vr_cpuname=NULL; 63 int vr_major=-1; 64 int vr_minor=-1; 65 int vr_cpuid=-1; 66 67 struct cfattach vrbcu_ca = { 68 sizeof(struct vrbcu_softc), vrbcu_match, vrbcu_attach 69 }; 70 71 struct vrbcu_softc *the_bcu_sc = NULL; 72 73 static inline void 74 vrbcu_write(sc, port, val) 75 struct vrbcu_softc *sc; 76 int port; 77 unsigned short val; 78 { 79 bus_space_write_2(sc->sc_iot, sc->sc_ioh, port, val); 80 } 81 82 static inline unsigned short 83 vrbcu_read(sc, port) 84 struct vrbcu_softc *sc; 85 int port; 86 { 87 return bus_space_read_2(sc->sc_iot, sc->sc_ioh, port); 88 } 89 90 static int 91 vrbcu_match(parent, cf, aux) 92 struct device *parent; 93 struct cfdata *cf; 94 void *aux; 95 { 96 return 2; 97 } 98 99 static void 100 vrbcu_attach(parent, self, aux) 101 struct device *parent; 102 struct device *self; 103 void *aux; 104 { 105 struct vrip_attach_args *va = aux; 106 struct vrbcu_softc *sc = (struct vrbcu_softc *)self; 107 108 sc->sc_iot = va->va_iot; 109 bus_space_map(sc->sc_iot, va->va_addr, va->va_size, 110 0, /* no flags */ 111 &sc->sc_ioh); 112 113 printf("\n"); 114 the_bcu_sc = sc; 115 vrbcu_dump_regs(); 116 } 117 118 static void 119 vrbcu_dump_regs() 120 { 121 struct vrbcu_softc *sc = the_bcu_sc; 122 int cpuclock = 0, tclock = 0, vtclock = 0, cpuid; 123 #if !defined(ONLY_VR4102) 124 int spdreg; 125 #endif 126 #ifdef VRBCUDEBUG 127 int reg; 128 #endif /* VRBCUDEBUG */ 129 130 cpuid = vrbcu_vrip_getcpuid(); 131 #if !defined(ONLY_VR4181) && !defined(ONLY_VR4102) 132 if (cpuid != BCUREVID_FIXRID_4181 133 && cpuid <= BCUREVID_RID_4122 134 && cpuid >= BCUREVID_RID_4111) { 135 spdreg = vrbcu_read(sc, BCUCLKSPEED_REG_W); 136 #ifdef VRBCUDEBUG 137 printf("vrbcu: CLKSPEED %x: \n", spdreg); 138 #endif /* VRBCUDEBUG */ 139 } 140 #endif 141 #if defined VR4181 142 if (cpuid == BCUREVID_FIXRID_4181){ 143 spdreg = vrbcu_read(sc, BCU81CLKSPEED_REG_W); 144 #ifdef VRBCUDEBUG 145 printf("vrbcu: CLKSPEED %x: \n", spdreg); 146 #endif /* VRBCUDEBUG */ 147 } 148 #endif 149 150 cpuclock = vrbcu_vrip_getcpuclock(); 151 152 switch (cpuid) { 153 #if defined VR4181 154 case BCUREVID_FIXRID_4181: 155 switch ((spdreg&BCU81CLKSPEED_DIVTMASK)>>BCU81CLKSPEED_DIVTSHFT){ 156 case BCU81CLKSPEED_DIVT1: 157 vtclock = tclock = cpuclock; 158 break; 159 case BCU81CLKSPEED_DIVT2: 160 vtclock = tclock = cpuclock/2; 161 break; 162 case BCU81CLKSPEED_DIVT3: 163 vtclock = tclock = cpuclock/3; 164 break; 165 case BCU81CLKSPEED_DIVT4: 166 vtclock = tclock = cpuclock/4; 167 break; 168 default: 169 vtclock = tclock = 0; 170 } 171 break; 172 #endif /* VR4181 */ 173 case BCUREVID_RID_4101: 174 case BCUREVID_RID_4102: 175 vtclock = tclock = cpuclock/2; 176 break; 177 #if defined VR4111 178 case BCUREVID_RID_4111: 179 if ((spdreg&BCUCLKSPEED_DIVT2B) == 0) 180 vtclock = tclock = cpuclock/2; 181 else if ((spdreg&BCUCLKSPEED_DIVT3B) == 0) 182 vtclock = tclock = cpuclock/3; 183 else if ((spdreg&BCUCLKSPEED_DIVT4B) == 0) 184 vtclock = tclock = cpuclock/4; 185 else 186 vtclock = tclock = 0; /* XXX */ 187 break; 188 #endif /* VR4111 */ 189 #if defined VR4121 190 case BCUREVID_RID_4121: 191 { 192 int vt; 193 tclock = cpuclock / ((spdreg&BCUCLKSPEED_DIVTMASK)>>BCUCLKSPEED_DIVTSHFT); 194 vt = ((spdreg&BCUCLKSPEED_DIVVTMASK)>>BCUCLKSPEED_DIVVTSHFT); 195 if (vt == 0) 196 vtclock = 0; /* XXX */ 197 else if (vt < 0x9) 198 vtclock = cpuclock / vt; 199 else 200 vtclock = cpuclock / ((vt - 8)*2+1) * 2; 201 } 202 break; 203 #endif /* VR4121 */ 204 default: 205 break; 206 } 207 if (tclock) 208 printf("%s: cpu %d.%03dMHz, bus %d.%03dMHz, ram %d.%03dMHz\n", 209 sc->sc_dev.dv_xname, 210 cpuclock/1000000, (cpuclock%1000000)/1000, 211 tclock/1000000, (tclock%1000000)/1000, 212 vtclock/1000000, (vtclock%1000000)/1000); 213 else { 214 printf("%s: cpu %d.%03dMHz\n", 215 sc->sc_dev.dv_xname, 216 cpuclock/1000000, (cpuclock%1000000)/1000); 217 printf("%s: UNKNOWN BUS CLOCK SPEED: CPU is UNKNOWN or NOT CONFIGURED\n", 218 sc->sc_dev.dv_xname); 219 } 220 #ifdef VRBCUDEBUG 221 reg = vrbcu_read(sc, BCUCNT1_REG_W); 222 printf("vrbcu: CNT1 %x: ", reg); 223 bitdisp16(reg); 224 #if !defined(ONLY_VR4181) 225 if (cpuid != BCUREVID_FIXRID_4181 226 && cpuid <= BCUREVID_RID_4121 227 && cpuid >= BCUREVID_RID_4102) { 228 reg = vrbcu_read(sc, BCUCNT2_REG_W); 229 printf("vrbcu: CNT2 %x: ", reg); 230 bitdisp16(reg); 231 } 232 #endif /* !defined ONLY_VR4181 */ 233 #if !defined(ONLY_VR4181) || !defined(ONLY_VR4122) 234 if (cpuid != BCUREVID_FIXRID_4181 235 && cpuid <= BCUREVID_RID_4121 236 && cpuid >= BCUREVID_RID_4102) { 237 reg = vrbcu_read(sc, BCUSPEED_REG_W); 238 printf("vrbcu: SPEED %x: ", reg); 239 bitdisp16(reg); 240 reg = vrbcu_read(sc, BCUERRST_REG_W); 241 printf("vrbcu: ERRST %x: ", reg); 242 bitdisp16(reg); 243 reg = vrbcu_read(sc, BCURFCNT_REG_W); 244 printf("vrbcu: RFCNT %x\n", reg); 245 reg = vrbcu_read(sc, BCUREFCOUNT_REG_W); 246 printf("vrbcu: RFCOUNT %x\n", reg); 247 } 248 #endif /* !defined(ONLY_VR4181) || !defined(ONLY_VR4122) */ 249 #if !defined(ONLY_VR4181) 250 if (cpuid != BCUREVID_FIXRID_4181 251 && cpuid <= BCUREVID_RID_4122 252 && cpuid >= BCUREVID_RID_4111) 253 { 254 reg = vrbcu_read(sc, BCUCNT3_REG_W); 255 printf("vrbcu: CNT3 %x: ", reg); 256 bitdisp16(reg); 257 } 258 #endif /* !defined ONLY_VR4181 */ 259 #endif /* VRBCUDEBUG */ 260 261 } 262 263 static char *cpuname[] = { 264 "VR4101", /* 0 */ 265 "VR4102", /* 1 */ 266 "VR4111", /* 2 */ 267 "VR4121", /* 3 */ 268 "VR4122", /* 4 */ 269 "UNKNOWN", 270 "UNKNOWN", 271 "UNKNOWN", 272 "UNKNOWN", 273 "UNKNOWN", 274 "UNKNOWN", 275 "UNKNOWN", 276 "UNKNOWN", 277 "UNKNOWN", 278 "UNKNOWN", 279 "UNKNOWN", 280 "VR4181", /* 0x10 + 0 */ 281 }; 282 283 int 284 vrbcu_vrip_getcpuid(void) 285 { 286 volatile u_int16_t *revreg; 287 288 if (vr_cpuid != -1) 289 return vr_cpuid; 290 291 if (vr_cpuid == -1) { 292 if (VRIP_BCU_ADDR == VR4181_BCU_ADDR) 293 revreg = (u_int16_t *)MIPS_PHYS_TO_KSEG1((VRIP_BCU_ADDR+BCU81REVID_REG_W)); 294 else 295 revreg = (u_int16_t *)MIPS_PHYS_TO_KSEG1((VRIP_BCU_ADDR+BCUREVID_REG_W)); 296 297 vr_cpuid = *revreg; 298 vr_cpuid = (vr_cpuid&BCUREVID_RIDMASK)>>BCUREVID_RIDSHFT; 299 if (VRIP_BCU_ADDR == VR4181_BCU_ADDR 300 && vr_cpuid == BCUREVID_RID_4181) /* conflict vr4101 */ 301 vr_cpuid = BCUREVID_FIXRID_4181; 302 } 303 return vr_cpuid; 304 } 305 306 char * 307 vrbcu_vrip_getcpuname(void) 308 { 309 int cpuid; 310 311 if (vr_cpuname != NULL) 312 return vr_cpuname; 313 314 cpuid = vrbcu_vrip_getcpuid(); 315 vr_cpuname = cpuname[cpuid]; 316 return vr_cpuname; 317 } 318 319 320 int 321 vrbcu_vrip_getcpumajor(void) 322 { 323 volatile u_int16_t *revreg; 324 325 if (vr_major != -1) 326 return vr_major; 327 328 revreg = (u_int16_t *)MIPS_PHYS_TO_KSEG1((VRIP_BCU_ADDR+BCUREVID_REG_W)); 329 330 vr_major = *revreg; 331 vr_major = (vr_major&BCUREVID_MJREVMASK)>>BCUREVID_MJREVSHFT; 332 return vr_major; 333 } 334 335 int 336 vrbcu_vrip_getcpuminor(void) 337 { 338 volatile u_int16_t *revreg; 339 340 if (vr_minor != -1) 341 return vr_minor; 342 343 revreg = (u_int16_t *)MIPS_PHYS_TO_KSEG1((VRIP_BCU_ADDR+BCUREVID_REG_W)); 344 345 vr_minor = *revreg; 346 vr_minor = (vr_minor&BCUREVID_MNREVMASK)>>BCUREVID_MNREVSHFT; 347 return vr_minor; 348 } 349 350 #define CLKX 18432000 /* CLKX1,CLKX2: 18.432MHz */ 351 #define MHZ 1000000 352 353 int 354 vrbcu_vrip_getcpuclock(void) 355 { 356 u_int16_t clksp; 357 int cpuid, cpuclock; 358 359 cpuid = vrbcu_vrip_getcpuid(); 360 if (cpuid != BCUREVID_FIXRID_4181 && cpuid >= BCUREVID_RID_4111) { 361 clksp = *(u_int16_t *)MIPS_PHYS_TO_KSEG1((VRIP_BCU_ADDR+BCUCLKSPEED_REG_W)) & BCUCLKSPEED_CLKSPMASK; 362 } else if (cpuid == BCUREVID_FIXRID_4181) { 363 clksp = *(u_int16_t *)MIPS_PHYS_TO_KSEG1((VRIP_BCU_ADDR+BCU81CLKSPEED_REG_W)) & BCUCLKSPEED_CLKSPMASK; 364 } 365 366 switch (cpuid) { 367 case BCUREVID_FIXRID_4181: 368 cpuclock = CLKX / clksp * 64; 369 /* branch delay is 1 clock; 2 clock/loop */ 370 cpuspeed = (cpuclock / 2 + MHZ / 2) / MHZ; 371 break; 372 case BCUREVID_RID_4101: 373 /* assume 33MHz */ 374 cpuclock = 33000000; 375 /* branch delay is 1 clock; 2 clock/loop */ 376 cpuspeed = (cpuclock / 2 + MHZ / 2) / MHZ; 377 break; 378 case BCUREVID_RID_4102: 379 cpuclock = CLKX / clksp * 32; 380 /* branch delay is 1 clock; 2 clock/loop */ 381 cpuspeed = (cpuclock / 2 + MHZ / 2) / MHZ; 382 break; 383 case BCUREVID_RID_4111: 384 cpuclock = CLKX / clksp * 64; 385 /* branch delay is 1 clock; 2 clock/loop */ 386 cpuspeed = (cpuclock / 2 + MHZ / 2) / MHZ; 387 break; 388 case BCUREVID_RID_4121: 389 cpuclock = CLKX / clksp * 64; 390 /* branch delay is 2 clock; 3 clock/loop */ 391 cpuspeed = (cpuclock / 3 + MHZ / 2) / MHZ; 392 break; 393 default: 394 panic("unknown CPU type %d\n", cpuid); 395 break; 396 } 397 return cpuclock; 398 } 399
Indexes created Mon Sep 29 21:09:56 GMT 2025