bcureg.h revision 1.2
1 /* $NetBSD: bcureg.h,v 1.2 1999/12/13 03:11:36 sato Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 SATO Kazumi. All rights reserved. 5 * Copyright (c) 1999 PocketBSD Project. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the PocketBSD project 18 * and its contributors. 19 * 4. Neither the name of the project nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 */ 36 37 /* 38 * BCU (Bus Control Unit) Registers definitions. 39 * start 0xB000000 40 */ 41 42 #define BCUCNT1_REG_W 0x000 /* BCU Control Register 1 */ 43 44 #define BCUCNT1_ROMMASK (1<<15) /* ROM SIZE */ 45 #define BCUCNT1_ROM64M (1<<15) /* ROM SIZE 64Mbit*/ 46 #define BCUCNT1_ROM32M (0<<15) /* ROM SIZE 32Mbit*/ 47 48 #define BCUCNT1_DRAMMASK (1<<14) /* DRAM SIZE */ 49 #define BCUCNT1_DRAM64M (1<<14) /* DRAM SIZE 64Mbit*/ 50 #define BCUCNT1_DRAM32M (0<<14) /* DRAM SIZE 32Mbit*/ 51 52 #define BCUCNT1_ISAMLCD (1<<13) /* ISAM/LCD 0x0a000000 to 0xaffffff*/ 53 #define BCUCNT1_ISA (1<<13) /* ISA memory space */ 54 #define BCUCNT1_LCD (0<<13) /* LCD space*/ 55 56 #define BCUCNT1_PAGEMASK (1<<12) /* Maximum burst access size for Page Rom */ 57 #define BCUCNT1_PAGE128 (1<<12) /* 128bit */ 58 #define BCUCNT1_PAGE64 (0<<12) /* 64bit */ 59 60 #define BCUCNT1_PAGE2MASK (1<<10) /* */ 61 #define BCUCNT1_PAGE2PAGE (1<<10) /* Page ROM */ 62 #define BCUCNT1_PAGE2ORD (0<<10) /* Prginary ROM */ 63 64 #define BCUCNT1_PAGE0MASK (1<<8) /* */ 65 #define BCUCNT1_PAGE0PAGE (1<<8) /* Page ROM */ 66 #define BCUCNT1_PAGE0ORD (0<<8) /* Prginary ROM */ 67 68 #define BCUCNT1_ROMWEN2 (1<<6) /* Enable Flash memory write ROM 2*/ 69 #define BCUCNT1_ROMWEN2EN (1<<6) /* Enable */ 70 #define BCUCNT1_ROMWEN2DS (0<<6) /* Prohibit */ 71 72 #define BCUCNT1_ROMWEN0 (1<<4) /* Enable Flash memory write ROM 0*/ 73 #define BCUCNT1_ROMWEN0EN (1<<4) /* Enable */ 74 #define BCUCNT1_ROMWEN0DS (0<<4) /* Prohibit */ 75 76 #define BCUCNT1_BUSHERR (1<<1) /* Bus Timeout detection enable */ 77 78 #define BCUCNT1_BUSHERREN (1<<1) /* Enable */ 79 #define BCUCNT1_BUSHERRDS (0<<1) /* Prohibit */ 80 81 #define BCUCNT1_RSTOUT (1) /* RSTOUT control bit */ 82 #define BCUCNT1_RSTOUTH (1) /* RSTOUT high level*/ 83 #define BCUCNT1_RSTOUTL (0) /* RSTOUT low level*/ 84 85 86 #define BCUCNT2_REG_W 0x002 /* BCU Control Register 2 */ 87 88 #define BCUCNT2_GMODE (1) /* LCD access control */ 89 #define BCUCNT2_GMODENOM (1) /* not invert LCD */ 90 #define BCUCNT2_GMODEINV (0) /* invert LCD */ 91 92 93 #define BCUSPEED_REG_W 0x00A /* BCU Access Cycle Change Register */ 94 95 #define BCUSPD_WPROM (0x3<<12) /* Page ROM access speed */ 96 #define BCUSPD_WPROMRFU (0x3<<12) /* RFU */ 97 #define BCUSPD_WPROM1T (0x2<<12) /* 1TClock */ 98 #define BCUSPD_WPROM2T (0x1<<12) /* 2TClock */ 99 #define BCUSPD_WPROM3T (0x0<<12) /* 3TClock */ 100 101 #define BCUSPD_WLCDM (0x7<<18) /* access speed 0x0a000000-0affffff */ 102 103 /* BCUCNT1_ISAMLCD == BCUCNT1_LCD */ 104 #define BCUSPD_WLCDRFU (0x7<<12) /* LCD RFU */ 105 #define BCUSPD_WLCDRFU1 (0x6<<12) /* LCD RFU */ 106 #define BCUSPD_WLCDRFU2 (0x5<<12) /* LCD RFU */ 107 #define BCUSPD_WLCDRFU3 (0x4<<12) /* LCD RFU */ 108 #define BCUSPD_WLCD2T (0x3<<12) /* LCD 2TClock */ 109 #define BCUSPD_WLCD4T (0x2<<12) /* LCD 4TClock */ 110 #define BCUSPD_WLCD6T (0x1<<12) /* LCD 6TClock */ 111 #define BCUSPD_WLCD8T (0x0<<12) /* LCD 8TClock */ 112 /* BCUCNT1_ISAMLCD == BCUCNT1_ISAM */ 113 #define BCUSPD_ISAM1T (0x7<<12) /* ISAM 1TClock */ 114 #define BCUSPD_ISAM2T (0x6<<12) /* ISAM 2TClock */ 115 #define BCUSPD_ISAM3T (0x5<<12) /* ISAM 3TClock */ 116 #define BCUSPD_ISAM4T (0x4<<12) /* ISAM 4TClock */ 117 #define BCUSPD_ISAM5T (0x3<<12) /* ISAM 5TClock */ 118 #define BCUSPD_ISAM6T (0x2<<12) /* ISAM 6TClock */ 119 #define BCUSPD_ISAM7T (0x1<<12) /* ISAM 7TClock */ 120 #define BCUSPD_ISAM8T (0x0<<12) /* ISAM 8TClock */ 121 122 #define BCUSPD_WISAA (0x7<<4) /* System Bus Access Speed */ 123 #define BCUSPD_WISAA3T (0x5<<4) /* 3TClock */ 124 #define BCUSPD_WISAA4T (0x4<<4) /* 4TClock */ 125 #define BCUSPD_WISAA5T (0x3<<4) /* 5TClock */ 126 #define BCUSPD_WISAA6T (0x2<<4) /* 6TClock */ 127 #define BCUSPD_WISAA7T (0x1<<4) /* 7TClock */ 128 #define BCUSPD_WISAA8T (0x0<<4) /* 8TClock */ 129 130 #define BCUSPD_WROMA (0x7<<0) /* System Bus Access Speed */ 131 #define BCUSPD_WROMA2T (0x7<<0) /* 2TClock */ 132 #define BCUSPD_WROMA3T (0x6<<0) /* 3TClock */ 133 #define BCUSPD_WROMA4T (0x5<<0) /* 4TClock */ 134 #define BCUSPD_WROMA5T (0x4<<0) /* 5TClock */ 135 #define BCUSPD_WROMA6T (0x3<<0) /* 6TClock */ 136 #define BCUSPD_WROMA7T (0x2<<0) /* 7TClock */ 137 #define BCUSPD_WROMA8T (0x1<<0) /* 8TClock */ 138 #define BCUSPD_WROMA9T (0x0<<0) /* 9TClock */ 139 140 141 #define BCUERRST_REG_W 0x00C /* BCU BUS ERROR Status Register */ 142 143 #define BCUERRST_BUSERRMASK (1) /* Bus error, clear to 0 when 1 is written */ 144 #define BCUERRST_BUSERR (1) /* Bus error */ 145 #define BCUERRST_BUSNORM (0) /* Normal */ 146 147 148 #define BCURFCNT_REG_W 0x00E /* BCU Refresh Control Register */ 149 150 #define BCURFCNT_MASK 0x3fff /* refresh interval MASK */ 151 152 153 #define BCUREVID_REG_W 0x010 /* BCU Revision ID Register */ 154 155 #define BCUREVID_RIDMASK (0x7<<12) /* Revision ID */ 156 #define BCUREVID_RIDSHFT (12) /* Revision ID */ 157 #define BCUREVID_RID_4121 (0x3) /* VR4121 */ 158 #define BCUREVID_RID_4111 (0x2) /* VR4111 */ 159 #define BCUREVID_RID_4102 (0x1) /* VR4102 */ 160 #define BCUREVID_RID_4101 (0x0) /* VR4101 */ 161 162 #define BCUREVID_MJREVMASK (0x7<<8) /* Major Revision */ 163 #define BCUREVID_MJREVSHFT (8) /* Major Revision */ 164 165 #define BCUREVID_MNREVMASK (0x7) /* Minor Revision */ 166 #define BCUREVID_MNREVSHFT (0) /* Minor Revision */ 167 168 169 #define BCUREFCOUNT_REG_W 0x012 /* BCU Refresh Count Register */ 170 171 #define BCUREFCOUNT_MASK 0x3fff /* refresh count MASK */ 172 173 174 #define BCUCLKSPEED_REG_W 0x014 /* Clock Speed Register */ 175 176 #define BCUCLKSPEED_DIV2B (1<<15) 177 #define BCUCLKSPEED_DIV3B (1<<14) 178 #define BCUCLKSPEED_DIV4B (1<<13) 179 180 #define BCUCLKSPEED_CLKSPMASK (0xf) /* calculate for Clock */ 181 #define BCUCLKSPEED_CLKSPSHFT (0) 182 183 #define BCUCNT3_REG_W 0x016 /* BCU Control Register 3 (>= vr4111) */ 184 185 #define BCUCNT3_EXTROMMASK (1<<15) /* ROM SIZE */ 186 #define BCUCNT3_EXTROM64M (1<<15) /* 64Mbit DRAM */ 187 #define BCUCNT3_EXTROM32M (0<<15) /* 32Mbit DRAM */ 188 189 #define BCUCNT3_EXTDRAMMASK (1<<14) /* DRAM SIZE */ 190 #define BCUCNT3_EXTDRAM64M (1<<14) /* 64Mbit DRAM */ 191 #define BCUCNT3_EXTDRAM16M (0<<14) /* 16Mbit DRAM */ 192 193 #define BCUCNT3_EXTROMCS (0x3<<12) /* Bank3,2 */ 194 #define BCUCNT3_ROMROM (0x3<<12) /* Bank3 ROM ,2 ROM */ 195 #define BCUCNT3_ROMRAM (0x2<<12) /* Bank3 ROM ,2 RAM */ 196 #define BCUCNT3_RAMRAM (0x0<<12) /* Bank3 RAM ,2 RAM */ 197 198 #define BCUCNT3_EXTMEM (1<<11) /* EXT MEN enable */ 199 #define BCUCNT3_EXTMEMEN (1<<11) /* EXT MEN enable */ 200 #define BCUCNT3_EXTMEMDS (0<<11) /* EXT MEN disable */ 201 202 #define BCUCNT3_LCDSIZE (1<<7) /* LCD bus size */ 203 #define BCUCNT3_LCD32 (1<<7) /* LCD bus 32bit */ 204 #define BCUCNT3_LCD16 (0<<7) /* LCD bus 16bit */ 205 206 /* END bcureg.h */ 207
Indexes created Mon Sep 29 21:09:56 GMT 2025