flash_vrip.c revision 1.8 1 1.8 chs /* $NetBSD: flash_vrip.c,v 1.8 2012/10/27 17:17:55 chs Exp $ */
2 1.1 igy
3 1.1 igy /*
4 1.1 igy * Copyright (c) 2002 The NetBSD Foundation, Inc.
5 1.1 igy * All rights reserved.
6 1.1 igy *
7 1.1 igy * This code is derived from software contributed to The NetBSD Foundation
8 1.1 igy * by Naoto Shimazaki of YOKOGAWA Electric Corporation.
9 1.1 igy *
10 1.1 igy * Redistribution and use in source and binary forms, with or without
11 1.1 igy * modification, are permitted provided that the following conditions
12 1.1 igy * are met:
13 1.1 igy * 1. Redistributions of source code must retain the above copyright
14 1.1 igy * notice, this list of conditions and the following disclaimer.
15 1.1 igy * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 igy * notice, this list of conditions and the following disclaimer in the
17 1.1 igy * documentation and/or other materials provided with the distribution.
18 1.1 igy *
19 1.1 igy * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 1.1 igy * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 1.1 igy * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 1.1 igy * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 1.1 igy * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 1.1 igy * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 1.1 igy * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 1.1 igy * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 1.1 igy * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 1.1 igy * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 1.1 igy * POSSIBILITY OF SUCH DAMAGE.
30 1.1 igy */
31 1.1 igy
32 1.1 igy /*
33 1.1 igy * Flash Memory Driver
34 1.1 igy */
35 1.2 lukem
36 1.2 lukem #include <sys/cdefs.h>
37 1.8 chs __KERNEL_RCSID(0, "$NetBSD: flash_vrip.c,v 1.8 2012/10/27 17:17:55 chs Exp $");
38 1.1 igy
39 1.1 igy #include <sys/param.h>
40 1.1 igy #include <sys/conf.h>
41 1.1 igy #include <sys/device.h>
42 1.1 igy #include <sys/kernel.h>
43 1.1 igy #include <sys/malloc.h>
44 1.1 igy #include <sys/proc.h>
45 1.1 igy #include <sys/systm.h>
46 1.1 igy
47 1.1 igy #include <machine/bus.h>
48 1.1 igy
49 1.1 igy #include <hpcmips/vr/vripif.h>
50 1.1 igy #include <hpcmips/vr/cfireg.h>
51 1.1 igy #include <hpcmips/vr/flashreg.h>
52 1.1 igy #include <hpcmips/vr/flashvar.h>
53 1.1 igy
54 1.1 igy #ifdef FLASH_DEBUG
55 1.1 igy int flash_debug = 0;
56 1.1 igy #define DPRINTF(x) if (flash_debug) printf x
57 1.1 igy #else
58 1.1 igy #define DPRINTF(x)
59 1.1 igy #endif
60 1.1 igy
61 1.8 chs static int flash_probe(device_t, cfdata_t, void *);
62 1.8 chs static void flash_attach(device_t, device_t, void *);
63 1.1 igy
64 1.1 igy const static struct flashops * find_command_set(u_int8_t cmdset0,
65 1.1 igy u_int8_t cmdset1);
66 1.1 igy static int i28f128_probe(bus_space_tag_t, bus_space_handle_t);
67 1.1 igy static int mbm29160_probe(bus_space_tag_t, bus_space_handle_t);
68 1.1 igy static int is_block_same(struct flash_softc *, bus_size_t, const void *);
69 1.1 igy static int probe_cfi(bus_space_tag_t iot, bus_space_handle_t ioh);
70 1.1 igy
71 1.1 igy static int intel_erase(struct flash_softc *, bus_size_t);
72 1.1 igy static int intel_write(struct flash_softc *, bus_size_t);
73 1.1 igy static int amd_erase(struct flash_softc *, bus_size_t);
74 1.1 igy static int amd_write(struct flash_softc *, bus_size_t);
75 1.1 igy
76 1.1 igy extern struct cfdriver flash_cd;
77 1.1 igy
78 1.8 chs CFATTACH_DECL_NEW(flash_vrip, sizeof(struct flash_softc),
79 1.1 igy flash_probe, flash_attach, NULL, NULL);
80 1.1 igy
81 1.1 igy dev_type_open(flashopen);
82 1.1 igy dev_type_close(flashclose);
83 1.1 igy dev_type_read(flashread);
84 1.1 igy dev_type_write(flashwrite);
85 1.1 igy
86 1.1 igy const struct cdevsw flash_cdevsw = {
87 1.1 igy flashopen, flashclose, flashread, flashwrite, noioctl,
88 1.1 igy nostop, notty, nopoll, nommap, nokqfilter,
89 1.1 igy };
90 1.1 igy
91 1.1 igy static const struct flash_command_set {
92 1.1 igy u_int8_t fc_set0;
93 1.1 igy u_int8_t fc_set1;
94 1.1 igy struct flashops fc_ops;
95 1.1 igy } flash_cmd[] = {
96 1.1 igy {
97 1.1 igy .fc_set0 = CFI_COMMSET_INTEL0,
98 1.1 igy .fc_set1 = CFI_COMMSET_INTEL1,
99 1.1 igy .fc_ops = {
100 1.1 igy .fo_name = "Intel",
101 1.1 igy .fo_erase = intel_erase,
102 1.1 igy .fo_write = intel_write,
103 1.1 igy }
104 1.1 igy },
105 1.1 igy {
106 1.1 igy .fc_set0 = CFI_COMMSET_AMDFJITU0,
107 1.1 igy .fc_set1 = CFI_COMMSET_AMDFJITU1,
108 1.1 igy .fc_ops = {
109 1.1 igy .fo_name = "AMD/Fujitsu",
110 1.1 igy .fo_erase = amd_erase,
111 1.1 igy .fo_write = amd_write,
112 1.1 igy }
113 1.1 igy },
114 1.1 igy {
115 1.1 igy .fc_set0 = 0,
116 1.1 igy .fc_set1 = 0,
117 1.1 igy .fc_ops = {
118 1.1 igy .fo_name = NULL,
119 1.1 igy .fo_erase = NULL,
120 1.1 igy .fo_write = NULL,
121 1.1 igy }
122 1.1 igy }
123 1.1 igy };
124 1.1 igy
125 1.1 igy
126 1.1 igy const static struct flashops *
127 1.1 igy find_command_set(u_int8_t cmdset0, u_int8_t cmdset1)
128 1.1 igy {
129 1.1 igy const struct flash_command_set *fc;
130 1.1 igy
131 1.1 igy for (fc = flash_cmd; fc->fc_ops.fo_name; fc++) {
132 1.1 igy if (cmdset0 == fc->fc_set0 && cmdset1 == fc->fc_set1)
133 1.1 igy return &fc->fc_ops;
134 1.1 igy }
135 1.1 igy return NULL;
136 1.1 igy }
137 1.1 igy
138 1.1 igy static int
139 1.1 igy probe_cfi(bus_space_tag_t iot, bus_space_handle_t ioh)
140 1.1 igy {
141 1.1 igy const u_int8_t *idstr = CFI_QUERY_ID_STR;
142 1.1 igy int i;
143 1.1 igy u_int8_t cmdset0;
144 1.1 igy u_int8_t cmdset1;
145 1.1 igy
146 1.1 igy /* start Common Flash Interface Query */
147 1.1 igy bus_space_write_2(iot, ioh, CFI_QUERY_OFFSET, CFI_READ_CFI_QUERY);
148 1.1 igy
149 1.1 igy /* read CFI Query ID string */
150 1.1 igy i = CFI_QUERY_ID_STR_REG << 1;
151 1.1 igy do {
152 1.1 igy if (bus_space_read_2(iot, ioh, i) != *idstr) {
153 1.1 igy bus_space_write_2(iot, ioh, 0, FLASH_RESET);
154 1.1 igy return 1;
155 1.1 igy }
156 1.1 igy i += 2;
157 1.1 igy idstr++;
158 1.1 igy } while (*idstr);
159 1.1 igy
160 1.1 igy cmdset0 = bus_space_read_2(iot, ioh, CFI_PRIM_COMM_REG0 << 1);
161 1.1 igy cmdset1 = bus_space_read_2(iot, ioh, CFI_PRIM_COMM_REG1 << 1);
162 1.1 igy
163 1.1 igy /* switch flash to read mode */
164 1.1 igy bus_space_write_2(iot, ioh, 0, FLASH_RESET);
165 1.1 igy
166 1.1 igy if (!find_command_set(cmdset0, cmdset1))
167 1.1 igy return 1;
168 1.1 igy
169 1.1 igy return 0;
170 1.1 igy }
171 1.1 igy
172 1.1 igy static int
173 1.8 chs flash_probe(device_t parent, cfdata_t match, void *aux)
174 1.1 igy {
175 1.1 igy struct vrip_attach_args *va = aux;
176 1.1 igy bus_space_handle_t ioh;
177 1.1 igy
178 1.1 igy if (bus_space_map(va->va_iot, va->va_addr, va->va_size, 0, &ioh))
179 1.1 igy return 0;
180 1.1 igy if (!probe_cfi(va->va_iot, ioh)) {
181 1.1 igy DPRINTF("CFI ID str and command set recognized\n");
182 1.1 igy goto detect;
183 1.1 igy }
184 1.1 igy if (!i28f128_probe(va->va_iot, ioh)) {
185 1.1 igy DPRINTF("28F128 detected\n");
186 1.1 igy goto detect;
187 1.1 igy }
188 1.1 igy if (!mbm29160_probe(va->va_iot, ioh)) {
189 1.1 igy DPRINTF("29LV160 detected\n");
190 1.1 igy goto detect;
191 1.1 igy }
192 1.1 igy return 0;
193 1.1 igy
194 1.1 igy detect:
195 1.1 igy bus_space_unmap(va->va_iot, ioh, va->va_size);
196 1.1 igy return 1;
197 1.1 igy }
198 1.1 igy
199 1.1 igy static void
200 1.8 chs flash_attach(device_t parent, device_t self, void *aux)
201 1.1 igy {
202 1.8 chs struct flash_softc *sc = device_private(self);
203 1.1 igy struct vrip_attach_args *va = aux;
204 1.1 igy int i;
205 1.1 igy int fence;
206 1.1 igy bus_space_tag_t iot = va->va_iot;
207 1.1 igy bus_space_handle_t ioh;
208 1.1 igy size_t block_size;
209 1.1 igy
210 1.1 igy if (bus_space_map(iot, va->va_addr, va->va_size, 0, &ioh)) {
211 1.1 igy printf(": can't map i/o space\n");
212 1.1 igy return;
213 1.1 igy }
214 1.1 igy
215 1.1 igy sc->sc_iot = iot;
216 1.1 igy sc->sc_ioh = ioh;
217 1.1 igy sc->sc_size = va->va_size;
218 1.1 igy sc->sc_status = 0;
219 1.1 igy
220 1.1 igy /*
221 1.1 igy * Read entire CFI structure
222 1.1 igy */
223 1.1 igy bus_space_write_2(iot, ioh, CFI_QUERY_OFFSET, CFI_READ_CFI_QUERY);
224 1.1 igy for (i = 0; i < CFI_TOTAL_SIZE; i++) {
225 1.1 igy sc->sc_cfi_raw[i] = bus_space_read_2(iot, ioh, i << 1);
226 1.1 igy }
227 1.1 igy bus_space_write_2(iot, ioh, 0, FLASH_RESET);
228 1.1 igy
229 1.1 igy sc->sc_ops = find_command_set(sc->sc_cfi_raw[CFI_PRIM_COMM_REG0],
230 1.1 igy sc->sc_cfi_raw[CFI_PRIM_COMM_REG1]);
231 1.1 igy if (sc->sc_ops) {
232 1.1 igy printf(": using %s command set", sc->sc_ops->fo_name);
233 1.1 igy } else {
234 1.1 igy printf("opps sc->sc_ops is NULL\n");
235 1.1 igy }
236 1.1 igy
237 1.1 igy /*
238 1.1 igy * determine size of the largest block
239 1.1 igy */
240 1.1 igy sc->sc_block_size = 0;
241 1.1 igy i = CFI_EBLK1_INFO_REG;
242 1.1 igy fence = sc->sc_cfi_raw[CFI_NUM_ERASE_BLK_REG] * CFI_EBLK_INFO_SIZE
243 1.1 igy + i;
244 1.1 igy for (; i < fence; i += CFI_EBLK_INFO_SIZE) {
245 1.1 igy if (sc->sc_cfi_raw[i + CFI_EBLK_INFO_NSECT0] == 0
246 1.1 igy && sc->sc_cfi_raw[i + CFI_EBLK_INFO_NSECT1] == 0)
247 1.1 igy continue;
248 1.1 igy block_size
249 1.1 igy = (sc->sc_cfi_raw[i + CFI_EBLK_INFO_SECSIZE0] << 8)
250 1.1 igy + (sc->sc_cfi_raw[i + CFI_EBLK_INFO_SECSIZE1] << 16);
251 1.1 igy if (sc->sc_block_size < block_size)
252 1.1 igy sc->sc_block_size = block_size;
253 1.1 igy }
254 1.1 igy
255 1.1 igy if ((sc->sc_buf = malloc(sc->sc_block_size, M_DEVBUF, M_NOWAIT))
256 1.1 igy == NULL) {
257 1.1 igy printf(": can't alloc buffer space\n");
258 1.1 igy return;
259 1.1 igy }
260 1.1 igy
261 1.1 igy sc->sc_write_buffer_size
262 1.1 igy = 1 << (sc->sc_cfi_raw[CFI_MAX_WBUF_SIZE_REG0]
263 1.1 igy + (sc->sc_cfi_raw[CFI_MAX_WBUF_SIZE_REG1] << 8));
264 1.1 igy sc->sc_typ_word_prog_timo
265 1.1 igy = 1 << sc->sc_cfi_raw[CFI_TYP_WORD_PROG_REG];
266 1.1 igy sc->sc_max_word_prog_timo
267 1.1 igy = 1 << sc->sc_cfi_raw[CFI_MAX_WORD_PROG_REG];
268 1.1 igy sc->sc_typ_buffer_write_timo
269 1.1 igy = 1 << sc->sc_cfi_raw[CFI_TYP_BUF_WRITE_REG];
270 1.1 igy sc->sc_max_buffer_write_timo
271 1.1 igy = 1 << sc->sc_cfi_raw[CFI_MAX_BUF_WRITE_REG];
272 1.1 igy sc->sc_typ_block_erase_timo
273 1.1 igy = 1 << sc->sc_cfi_raw[CFI_TYP_BLOCK_ERASE_REG];
274 1.1 igy sc->sc_max_block_erase_timo
275 1.1 igy = 1 << sc->sc_cfi_raw[CFI_MAX_BLOCK_ERASE_REG];
276 1.1 igy
277 1.1 igy printf("\n");
278 1.1 igy
279 1.1 igy #ifdef FLASH_DEBUG
280 1.1 igy printf("read_cfi: extract cfi\n");
281 1.1 igy printf("max block size: %dbyte\n", sc->sc_block_size);
282 1.1 igy printf("write buffer size: %dbyte\n", sc->sc_write_buffer_size);
283 1.1 igy printf("typical word program timeout: %dusec\n",
284 1.1 igy sc->sc_typ_word_prog_timo);
285 1.1 igy printf("maximam word program timeout: %dusec (%d time of typ)\n",
286 1.1 igy sc->sc_typ_word_prog_timo * sc->sc_max_word_prog_timo,
287 1.1 igy sc->sc_max_word_prog_timo);
288 1.1 igy printf("typical buffer write timeout: %dusec\n",
289 1.1 igy sc->sc_typ_buffer_write_timo);
290 1.1 igy printf("maximam buffer write timeout: %dusec (%d time of typ)\n",
291 1.1 igy sc->sc_typ_buffer_write_timo * sc->sc_max_buffer_write_timo,
292 1.1 igy sc->sc_max_buffer_write_timo);
293 1.1 igy printf("typical block erase timeout: %dmsec\n",
294 1.1 igy sc->sc_typ_block_erase_timo);
295 1.1 igy printf("maximam block erase timeout: %dmsec (%d time of typ)\n",
296 1.1 igy sc->sc_typ_block_erase_timo * sc->sc_max_block_erase_timo,
297 1.1 igy sc->sc_max_block_erase_timo);
298 1.1 igy
299 1.1 igy printf("read_cfi: dump cfi\n");
300 1.1 igy for (i = 0; i < CFI_TOTAL_SIZE;) {
301 1.1 igy int j;
302 1.1 igy for (j = 0; j < 16; j++) {
303 1.1 igy printf("%02x ", sc->sc_cfi_raw[i++]);
304 1.1 igy }
305 1.1 igy printf("\n");
306 1.1 igy }
307 1.1 igy #endif
308 1.1 igy }
309 1.1 igy
310 1.1 igy int
311 1.5 christos flashopen(dev_t dev, int flag, int mode, struct lwp *l)
312 1.1 igy {
313 1.1 igy struct flash_softc *sc;
314 1.1 igy
315 1.7 cegger sc = device_lookup_private(&flash_cd, minor(dev));
316 1.7 cegger if (sc == NULL)
317 1.1 igy return ENXIO;
318 1.1 igy if (sc->sc_status & FLASH_ST_BUSY)
319 1.1 igy return EBUSY;
320 1.1 igy sc->sc_status |= FLASH_ST_BUSY;
321 1.1 igy return 0;
322 1.1 igy }
323 1.1 igy
324 1.1 igy int
325 1.5 christos flashclose(dev_t dev, int flag, int mode, struct lwp *l)
326 1.1 igy {
327 1.1 igy struct flash_softc *sc;
328 1.1 igy
329 1.7 cegger sc = device_lookup_private(&flash_cd, minor(dev));
330 1.1 igy sc->sc_status &= ~FLASH_ST_BUSY;
331 1.1 igy return 0;
332 1.1 igy }
333 1.1 igy
334 1.1 igy int
335 1.1 igy flashread(dev_t dev, struct uio *uio, int flag)
336 1.1 igy {
337 1.1 igy struct flash_softc *sc;
338 1.1 igy bus_space_tag_t iot;
339 1.1 igy bus_space_handle_t ioh;
340 1.1 igy bus_size_t off;
341 1.1 igy int total;
342 1.1 igy int count;
343 1.1 igy int error;
344 1.1 igy
345 1.7 cegger sc = device_lookup_private(&flash_cd, minor(dev));
346 1.1 igy iot = sc->sc_iot;
347 1.1 igy ioh = sc->sc_ioh;
348 1.1 igy
349 1.1 igy off = uio->uio_offset;
350 1.1 igy total = min(sc->sc_size - off, uio->uio_resid);
351 1.1 igy
352 1.1 igy while (total > 0) {
353 1.1 igy count = min(sc->sc_block_size, uio->uio_resid);
354 1.1 igy bus_space_read_region_1(iot, ioh, off, sc->sc_buf, count);
355 1.1 igy if ((error = uiomove(sc->sc_buf, count, uio)) != 0)
356 1.1 igy return error;
357 1.1 igy off += count;
358 1.1 igy total -= count;
359 1.1 igy }
360 1.1 igy return 0;
361 1.1 igy }
362 1.1 igy
363 1.1 igy
364 1.1 igy int
365 1.1 igy flashwrite(dev_t dev, struct uio *uio, int flag)
366 1.1 igy {
367 1.1 igy struct flash_softc *sc;
368 1.1 igy bus_space_tag_t iot;
369 1.1 igy bus_space_handle_t ioh;
370 1.1 igy bus_size_t off;
371 1.1 igy int stat;
372 1.1 igy int error;
373 1.1 igy
374 1.7 cegger sc = device_lookup_private(&flash_cd, minor(dev));
375 1.1 igy
376 1.1 igy if (sc->sc_size < uio->uio_offset + uio->uio_resid)
377 1.1 igy return ENOSPC;
378 1.1 igy if (uio->uio_offset % sc->sc_block_size)
379 1.1 igy return EINVAL;
380 1.1 igy if (uio->uio_resid % sc->sc_block_size)
381 1.1 igy return EINVAL;
382 1.1 igy
383 1.1 igy iot = sc->sc_iot;
384 1.1 igy ioh = sc->sc_ioh;
385 1.1 igy
386 1.1 igy for (off = uio->uio_offset;
387 1.1 igy uio->uio_resid > 0;
388 1.1 igy off += sc->sc_block_size) {
389 1.1 igy if ((error = uiomove(sc->sc_buf, sc->sc_block_size, uio)) != 0)
390 1.1 igy return error;
391 1.1 igy if (is_block_same(sc, off, sc->sc_buf))
392 1.1 igy continue;
393 1.1 igy if ((stat = flash_block_erase(sc, off)) != 0) {
394 1.1 igy printf("block erase failed status = 0x%x\n", stat);
395 1.1 igy return EIO;
396 1.1 igy }
397 1.1 igy if ((stat = flash_block_write(sc, off)) != 0) {
398 1.1 igy printf("block write failed status = 0x%x\n", stat);
399 1.1 igy return EIO;
400 1.1 igy }
401 1.1 igy }
402 1.1 igy return 0;
403 1.1 igy }
404 1.1 igy
405 1.1 igy /*
406 1.1 igy * XXX
407 1.1 igy * this function is too much specific for the device.
408 1.1 igy */
409 1.1 igy static int
410 1.1 igy i28f128_probe(bus_space_tag_t iot, bus_space_handle_t ioh)
411 1.1 igy {
412 1.1 igy static const u_int8_t vendor_code[] = {
413 1.1 igy 0x89, /* manufacturer code: intel */
414 1.1 igy 0x18, /* device code: 28F128 */
415 1.1 igy };
416 1.1 igy
417 1.1 igy static const u_int8_t idstr[] = {
418 1.1 igy 'Q', 'R', 'Y',
419 1.1 igy 0x01, 0x00,
420 1.1 igy 0x31, 0x00,
421 1.1 igy 0xff
422 1.1 igy };
423 1.1 igy
424 1.1 igy int i;
425 1.1 igy
426 1.1 igy /* start Common Flash Interface Query */
427 1.1 igy bus_space_write_2(iot, ioh, 0, CFI_READ_CFI_QUERY);
428 1.1 igy /* read CFI Query ID string */
429 1.1 igy for (i = 0; idstr[i] != 0xff; i++) {
430 1.1 igy if (bus_space_read_2(iot, ioh, (0x10 + i) << 1) != idstr[i])
431 1.1 igy return 1;
432 1.1 igy }
433 1.1 igy
434 1.1 igy /* read manufacturer code and device code */
435 1.1 igy if (bus_space_read_2(iot, ioh, 0x00) != vendor_code[0])
436 1.1 igy return 1;
437 1.1 igy if (bus_space_read_2(iot, ioh, 0x02) != vendor_code[1])
438 1.1 igy return 1;
439 1.1 igy
440 1.1 igy bus_space_write_2(iot, ioh, 0, I28F128_RESET);
441 1.1 igy return 0;
442 1.1 igy }
443 1.1 igy
444 1.1 igy /*
445 1.1 igy * XXX
446 1.1 igy * this function is too much specific for the device.
447 1.1 igy */
448 1.1 igy static int
449 1.1 igy mbm29160_probe(bus_space_tag_t iot, bus_space_handle_t ioh)
450 1.1 igy {
451 1.1 igy static const u_int16_t vendor_code[] = {
452 1.1 igy 0x0004, /* manufacturer code: intel */
453 1.1 igy 0x2249, /* device code: 29LV160BE */
454 1.1 igy };
455 1.1 igy
456 1.1 igy static const u_int8_t idstr[] = {
457 1.1 igy 'Q', 'R', 'Y',
458 1.1 igy 0x02, 0x00,
459 1.1 igy 0x40, 0x00,
460 1.1 igy 0xff
461 1.1 igy };
462 1.1 igy
463 1.1 igy int i;
464 1.1 igy
465 1.1 igy /* start Common Flash Interface Query */
466 1.1 igy bus_space_write_2(iot, ioh, 0xaa, CFI_READ_CFI_QUERY);
467 1.1 igy /* read CFI Query ID string */
468 1.1 igy for (i = 0; idstr[i] != 0xff; i++) {
469 1.1 igy if (bus_space_read_2(iot, ioh, (0x10 + i) << 1) != idstr[i])
470 1.1 igy return 1;
471 1.1 igy }
472 1.1 igy
473 1.1 igy bus_space_write_2(iot, ioh, 0, 0xff);
474 1.1 igy
475 1.1 igy /* read manufacturer code and device code */
476 1.1 igy bus_space_write_2(iot, ioh, 0x555 << 1, 0xaa);
477 1.1 igy bus_space_write_2(iot, ioh, 0x2aa << 1, 0x55);
478 1.1 igy bus_space_write_2(iot, ioh, 0x555 << 1, 0x90);
479 1.1 igy if (bus_space_read_2(iot, ioh, 0x00) != vendor_code[0])
480 1.1 igy return 1;
481 1.1 igy if (bus_space_read_2(iot, ioh, 0x02) != vendor_code[1])
482 1.1 igy return 1;
483 1.1 igy
484 1.1 igy bus_space_write_2(iot, ioh, 0, 0xff);
485 1.1 igy return 0;
486 1.1 igy }
487 1.1 igy
488 1.1 igy static int
489 1.1 igy is_block_same(struct flash_softc *sc, bus_size_t offset, const void *bufp)
490 1.1 igy {
491 1.1 igy bus_space_tag_t iot = sc->sc_iot;
492 1.1 igy bus_space_handle_t ioh = sc->sc_ioh;
493 1.1 igy const u_int8_t *p = bufp;
494 1.1 igy int count = sc->sc_block_size;
495 1.1 igy
496 1.1 igy while (count-- > 0) {
497 1.1 igy if (bus_space_read_1(iot, ioh, offset++) != *p++)
498 1.1 igy return 0;
499 1.1 igy }
500 1.1 igy return 1;
501 1.1 igy }
502 1.1 igy
503 1.1 igy static int
504 1.1 igy intel_erase(struct flash_softc *sc, bus_size_t offset)
505 1.1 igy {
506 1.1 igy bus_space_tag_t iot = sc->sc_iot;
507 1.1 igy bus_space_handle_t ioh = sc->sc_ioh;
508 1.1 igy int status;
509 1.1 igy int i;
510 1.1 igy
511 1.1 igy bus_space_write_2(iot, ioh, offset, I28F128_BLK_ERASE_1ST);
512 1.1 igy bus_space_write_2(iot, ioh, offset, I28F128_BLK_ERASE_2ND);
513 1.1 igy
514 1.3 igy status = 0;
515 1.1 igy for (i = sc->sc_max_block_erase_timo; i > 0; i--) {
516 1.1 igy tsleep(sc, PRIBIO, "blockerase",
517 1.1 igy 1 + (sc->sc_typ_block_erase_timo * hz) / 1000);
518 1.1 igy if ((status = bus_space_read_2(iot, ioh, offset))
519 1.1 igy & I28F128_S_READY)
520 1.1 igy break;
521 1.1 igy }
522 1.4 igy if (i == 0)
523 1.4 igy status |= FLASH_TIMEOUT;
524 1.1 igy
525 1.1 igy bus_space_write_2(iot, ioh, offset, I28F128_CLEAR_STATUS);
526 1.1 igy bus_space_write_2(iot, ioh, offset, I28F128_RESET);
527 1.1 igy
528 1.4 igy return status & (FLASH_TIMEOUT
529 1.4 igy | I28F128_S_ERASE_SUSPEND
530 1.1 igy | I28F128_S_COMSEQ_ERROR
531 1.1 igy | I28F128_S_ERASE_ERROR
532 1.1 igy | I28F128_S_BLOCK_LOCKED);
533 1.1 igy }
534 1.1 igy
535 1.1 igy static int
536 1.1 igy intel_write(struct flash_softc *sc, bus_size_t offset)
537 1.1 igy {
538 1.1 igy bus_space_tag_t iot = sc->sc_iot;
539 1.1 igy bus_space_handle_t ioh = sc->sc_ioh;
540 1.1 igy int wbuf_size;
541 1.1 igy int timo;
542 1.1 igy int status;
543 1.1 igy bus_size_t fence;
544 1.1 igy int i;
545 1.1 igy const u_int16_t *p;
546 1.1 igy
547 1.1 igy /* wbuf_size = size in u_int16_t */
548 1.1 igy wbuf_size = sc->sc_write_buffer_size >> 1;
549 1.1 igy
550 1.1 igy p = (u_int16_t *) sc->sc_buf;
551 1.1 igy fence = offset + sc->sc_block_size;
552 1.1 igy do {
553 1.3 igy status = 0;
554 1.1 igy for (timo = sc->sc_max_buffer_write_timo; timo > 0; timo--) {
555 1.1 igy bus_space_write_2(iot, ioh, offset,
556 1.1 igy I28F128_WRITE_BUFFER);
557 1.1 igy status = bus_space_read_2(iot, ioh, offset);
558 1.1 igy if (status & I28F128_XS_BUF_AVAIL)
559 1.1 igy break;
560 1.1 igy DELAY(sc->sc_typ_buffer_write_timo);
561 1.1 igy }
562 1.1 igy if (timo == 0) {
563 1.1 igy status |= FLASH_TIMEOUT;
564 1.1 igy goto errout;
565 1.1 igy }
566 1.1 igy
567 1.1 igy bus_space_write_2(iot, ioh, offset, wbuf_size - 1);
568 1.1 igy
569 1.1 igy for (i = wbuf_size; i > 0; i--, p++, offset += 2)
570 1.1 igy bus_space_write_2(iot, ioh, offset, *p);
571 1.1 igy
572 1.1 igy bus_space_write_2(iot, ioh, offset, I28F128_WBUF_CONFIRM);
573 1.1 igy
574 1.1 igy do {
575 1.1 igy bus_space_write_2(iot, ioh, offset,
576 1.1 igy I28F128_READ_STATUS);
577 1.1 igy status = bus_space_read_2(iot, ioh, offset);
578 1.1 igy } while (!(status & I28F128_S_READY));
579 1.1 igy
580 1.1 igy } while (offset < fence);
581 1.1 igy
582 1.1 igy bus_space_write_2(iot, ioh, offset, I28F128_CLEAR_STATUS);
583 1.1 igy bus_space_write_2(iot, ioh, offset, I28F128_RESET);
584 1.1 igy
585 1.1 igy return 0;
586 1.1 igy
587 1.1 igy errout:
588 1.1 igy bus_space_write_2(iot, ioh, offset, I28F128_CLEAR_STATUS);
589 1.1 igy bus_space_write_2(iot, ioh, offset, I28F128_RESET);
590 1.1 igy
591 1.1 igy status &= (FLASH_TIMEOUT
592 1.1 igy | I28F128_S_PROG_ERROR
593 1.1 igy | I28F128_S_COMSEQ_ERROR
594 1.1 igy | I28F128_S_LOW_VOLTAGE
595 1.1 igy | I28F128_S_PROG_SUSPEND
596 1.1 igy | I28F128_S_BLOCK_LOCKED);
597 1.1 igy return status;
598 1.1 igy }
599 1.1 igy
600 1.1 igy static int
601 1.1 igy amd_erase_sector(struct flash_softc *sc, bus_size_t offset)
602 1.1 igy {
603 1.1 igy bus_space_tag_t iot = sc->sc_iot;
604 1.1 igy bus_space_handle_t ioh = sc->sc_ioh;
605 1.1 igy int i;
606 1.1 igy
607 1.1 igy DPRINTF(("amd_erase_sector offset = %08lx\n", offset));
608 1.1 igy
609 1.1 igy bus_space_write_2(iot, ioh,
610 1.1 igy MBM29LV160_COMM_ADDR0, MBM29LV160_COMM_CMD0);
611 1.1 igy bus_space_write_2(iot, ioh,
612 1.1 igy MBM29LV160_COMM_ADDR1, MBM29LV160_COMM_CMD1);
613 1.1 igy bus_space_write_2(iot, ioh,
614 1.1 igy MBM29LV160_COMM_ADDR2, MBM29LV160_ESECT_CMD2);
615 1.1 igy bus_space_write_2(iot, ioh,
616 1.1 igy MBM29LV160_COMM_ADDR3, MBM29LV160_ESECT_CMD3);
617 1.1 igy bus_space_write_2(iot, ioh,
618 1.1 igy MBM29LV160_COMM_ADDR4, MBM29LV160_ESECT_CMD4);
619 1.1 igy bus_space_write_2(iot, ioh, offset, MBM29LV160_ESECT_CMD5);
620 1.1 igy
621 1.1 igy for (i = sc->sc_max_block_erase_timo; i > 0; i--) {
622 1.1 igy tsleep(sc, PRIBIO, "blockerase",
623 1.1 igy 1 + (sc->sc_typ_block_erase_timo * hz) / 1000);
624 1.1 igy if (bus_space_read_2(iot, ioh, offset) == 0xffff)
625 1.1 igy return 0;
626 1.1 igy }
627 1.1 igy
628 1.1 igy return FLASH_TIMEOUT;
629 1.1 igy }
630 1.1 igy
631 1.1 igy static int
632 1.1 igy amd_erase(struct flash_softc *sc, bus_size_t offset)
633 1.1 igy {
634 1.1 igy static const struct mbm29lv_subsect {
635 1.1 igy u_int16_t devcode;
636 1.1 igy u_int32_t subsect_mask;
637 1.1 igy u_int32_t subsect_addr;
638 1.1 igy } subsect[] = {
639 1.1 igy {
640 1.1 igy MBM29LV160TE_DEVCODE,
641 1.1 igy MBM29LV160_SUBSECT_MASK,
642 1.1 igy MBM29LV160TE_SUBSECT_ADDR
643 1.1 igy },
644 1.1 igy {
645 1.1 igy MBM29LV160BE_DEVCODE,
646 1.1 igy MBM29LV160_SUBSECT_MASK,
647 1.1 igy MBM29LV160BE_SUBSECT_ADDR
648 1.1 igy },
649 1.1 igy { 0, 0, 0 }
650 1.1 igy };
651 1.1 igy
652 1.1 igy bus_space_tag_t iot = sc->sc_iot;
653 1.1 igy bus_space_handle_t ioh = sc->sc_ioh;
654 1.1 igy u_int16_t devcode;
655 1.1 igy const struct mbm29lv_subsect *ss;
656 1.1 igy bus_size_t fence;
657 1.1 igy int step;
658 1.1 igy int status;
659 1.1 igy
660 1.1 igy bus_space_write_2(iot, ioh,
661 1.1 igy MBM29LV160_COMM_ADDR0, MBM29LV160_COMM_CMD0);
662 1.1 igy bus_space_write_2(iot, ioh,
663 1.1 igy MBM29LV160_COMM_ADDR1, MBM29LV160_COMM_CMD1);
664 1.1 igy bus_space_write_2(iot, ioh,
665 1.1 igy MBM29LV160_COMM_ADDR2, MBM29LV160_SIGN_CMD2);
666 1.1 igy devcode = bus_space_read_2(iot, ioh, MBM29LV160_DEVCODE_REG);
667 1.1 igy
668 1.1 igy for (ss = subsect; ss->devcode; ss++) {
669 1.1 igy if (ss->devcode == devcode)
670 1.1 igy break;
671 1.1 igy }
672 1.1 igy if (ss->devcode == 0) {
673 1.1 igy printf("flash: amd_erase(): unknown device code %04x\n",
674 1.1 igy devcode);
675 1.1 igy return -1;
676 1.1 igy }
677 1.1 igy
678 1.1 igy DPRINTF(("flash: amd_erase(): devcode = %04x subsect = %08x\n",
679 1.1 igy devcode, ss->subsect_addr));
680 1.1 igy
681 1.1 igy fence = offset + sc->sc_block_size;
682 1.1 igy step = (offset & ss->subsect_mask) == ss->subsect_addr
683 1.1 igy ? MBM29LV160_SUBSECT_SIZE : MBM29LV160_SECT_SIZE;
684 1.1 igy do {
685 1.1 igy if ((status = amd_erase_sector(sc, offset)) != 0)
686 1.1 igy return status;
687 1.1 igy offset += step;
688 1.1 igy } while (offset < fence);
689 1.1 igy
690 1.1 igy return 0;
691 1.1 igy }
692 1.1 igy
693 1.1 igy static int
694 1.1 igy amd_write(struct flash_softc *sc, bus_size_t offset)
695 1.1 igy {
696 1.1 igy bus_space_tag_t iot = sc->sc_iot;
697 1.1 igy bus_space_handle_t ioh = sc->sc_ioh;
698 1.1 igy int timo;
699 1.1 igy bus_size_t fence;
700 1.1 igy const u_int16_t *p;
701 1.1 igy
702 1.1 igy p = (u_int16_t *) sc->sc_buf;
703 1.1 igy fence = offset + sc->sc_block_size;
704 1.1 igy do {
705 1.1 igy bus_space_write_2(iot, ioh,
706 1.1 igy MBM29LV160_COMM_ADDR0,
707 1.1 igy MBM29LV160_COMM_CMD0);
708 1.1 igy bus_space_write_2(iot, ioh,
709 1.1 igy MBM29LV160_COMM_ADDR1,
710 1.1 igy MBM29LV160_COMM_CMD1);
711 1.1 igy bus_space_write_2(iot, ioh,
712 1.1 igy MBM29LV160_COMM_ADDR2,
713 1.1 igy MBM29LV160_PROG_CMD2);
714 1.1 igy bus_space_write_2(iot, ioh, offset, *p);
715 1.1 igy
716 1.1 igy for (timo = sc->sc_max_word_prog_timo; timo > 0; timo--) {
717 1.1 igy if (bus_space_read_2(iot, ioh, offset) == *p)
718 1.1 igy break;
719 1.1 igy DELAY(sc->sc_typ_word_prog_timo);
720 1.1 igy }
721 1.1 igy if (timo == 0)
722 1.1 igy return FLASH_TIMEOUT;
723 1.1 igy
724 1.1 igy p++;
725 1.1 igy offset += 2;
726 1.1 igy } while (offset < fence);
727 1.1 igy
728 1.1 igy return 0;
729 1.1 igy }
730