flash_vrip.c revision 1.3
1 /* $NetBSD: flash_vrip.c,v 1.3 2003/12/29 12:31:48 igy Exp $ */ 2 3 /* 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Naoto Shimazaki of YOKOGAWA Electric Corporation. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Flash Memory Driver 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: flash_vrip.c,v 1.3 2003/12/29 12:31:48 igy Exp $"); 45 46 #include <sys/param.h> 47 #include <sys/conf.h> 48 #include <sys/device.h> 49 #include <sys/kernel.h> 50 #include <sys/malloc.h> 51 #include <sys/proc.h> 52 #include <sys/systm.h> 53 54 #include <machine/bus.h> 55 56 #include <hpcmips/vr/vripif.h> 57 #include <hpcmips/vr/cfireg.h> 58 #include <hpcmips/vr/flashreg.h> 59 #include <hpcmips/vr/flashvar.h> 60 61 #ifdef FLASH_DEBUG 62 int flash_debug = 0; 63 #define DPRINTF(x) if (flash_debug) printf x 64 #else 65 #define DPRINTF(x) 66 #endif 67 68 static int flash_probe(struct device *, struct cfdata *, void *); 69 static void flash_attach(struct device *, struct device *, void *); 70 71 const static struct flashops * find_command_set(u_int8_t cmdset0, 72 u_int8_t cmdset1); 73 static int i28f128_probe(bus_space_tag_t, bus_space_handle_t); 74 static int mbm29160_probe(bus_space_tag_t, bus_space_handle_t); 75 static int is_block_same(struct flash_softc *, bus_size_t, const void *); 76 static int probe_cfi(bus_space_tag_t iot, bus_space_handle_t ioh); 77 78 static int intel_erase(struct flash_softc *, bus_size_t); 79 static int intel_write(struct flash_softc *, bus_size_t); 80 static int amd_erase(struct flash_softc *, bus_size_t); 81 static int amd_write(struct flash_softc *, bus_size_t); 82 83 extern struct cfdriver flash_cd; 84 85 CFATTACH_DECL(flash_vrip, sizeof(struct flash_softc), 86 flash_probe, flash_attach, NULL, NULL); 87 88 dev_type_open(flashopen); 89 dev_type_close(flashclose); 90 dev_type_read(flashread); 91 dev_type_write(flashwrite); 92 93 const struct cdevsw flash_cdevsw = { 94 flashopen, flashclose, flashread, flashwrite, noioctl, 95 nostop, notty, nopoll, nommap, nokqfilter, 96 }; 97 98 static const struct flash_command_set { 99 u_int8_t fc_set0; 100 u_int8_t fc_set1; 101 struct flashops fc_ops; 102 } flash_cmd[] = { 103 { 104 .fc_set0 = CFI_COMMSET_INTEL0, 105 .fc_set1 = CFI_COMMSET_INTEL1, 106 .fc_ops = { 107 .fo_name = "Intel", 108 .fo_erase = intel_erase, 109 .fo_write = intel_write, 110 } 111 }, 112 { 113 .fc_set0 = CFI_COMMSET_AMDFJITU0, 114 .fc_set1 = CFI_COMMSET_AMDFJITU1, 115 .fc_ops = { 116 .fo_name = "AMD/Fujitsu", 117 .fo_erase = amd_erase, 118 .fo_write = amd_write, 119 } 120 }, 121 { 122 .fc_set0 = 0, 123 .fc_set1 = 0, 124 .fc_ops = { 125 .fo_name = NULL, 126 .fo_erase = NULL, 127 .fo_write = NULL, 128 } 129 } 130 }; 131 132 133 const static struct flashops * 134 find_command_set(u_int8_t cmdset0, u_int8_t cmdset1) 135 { 136 const struct flash_command_set *fc; 137 138 for (fc = flash_cmd; fc->fc_ops.fo_name; fc++) { 139 if (cmdset0 == fc->fc_set0 && cmdset1 == fc->fc_set1) 140 return &fc->fc_ops; 141 } 142 return NULL; 143 } 144 145 static int 146 probe_cfi(bus_space_tag_t iot, bus_space_handle_t ioh) 147 { 148 const u_int8_t *idstr = CFI_QUERY_ID_STR; 149 int i; 150 u_int8_t cmdset0; 151 u_int8_t cmdset1; 152 153 /* start Common Flash Interface Query */ 154 bus_space_write_2(iot, ioh, CFI_QUERY_OFFSET, CFI_READ_CFI_QUERY); 155 156 /* read CFI Query ID string */ 157 i = CFI_QUERY_ID_STR_REG << 1; 158 do { 159 if (bus_space_read_2(iot, ioh, i) != *idstr) { 160 bus_space_write_2(iot, ioh, 0, FLASH_RESET); 161 return 1; 162 } 163 i += 2; 164 idstr++; 165 } while (*idstr); 166 167 cmdset0 = bus_space_read_2(iot, ioh, CFI_PRIM_COMM_REG0 << 1); 168 cmdset1 = bus_space_read_2(iot, ioh, CFI_PRIM_COMM_REG1 << 1); 169 170 /* switch flash to read mode */ 171 bus_space_write_2(iot, ioh, 0, FLASH_RESET); 172 173 if (!find_command_set(cmdset0, cmdset1)) 174 return 1; 175 176 return 0; 177 } 178 179 static int 180 flash_probe(struct device *parent, struct cfdata *match, void *aux) 181 { 182 struct vrip_attach_args *va = aux; 183 bus_space_handle_t ioh; 184 185 if (bus_space_map(va->va_iot, va->va_addr, va->va_size, 0, &ioh)) 186 return 0; 187 if (!probe_cfi(va->va_iot, ioh)) { 188 DPRINTF("CFI ID str and command set recognized\n"); 189 goto detect; 190 } 191 if (!i28f128_probe(va->va_iot, ioh)) { 192 DPRINTF("28F128 detected\n"); 193 goto detect; 194 } 195 if (!mbm29160_probe(va->va_iot, ioh)) { 196 DPRINTF("29LV160 detected\n"); 197 goto detect; 198 } 199 return 0; 200 201 detect: 202 bus_space_unmap(va->va_iot, ioh, va->va_size); 203 return 1; 204 } 205 206 static void 207 flash_attach(struct device *parent, struct device *self, void *aux) 208 { 209 struct flash_softc *sc = (void *) self; 210 struct vrip_attach_args *va = aux; 211 int i; 212 int fence; 213 bus_space_tag_t iot = va->va_iot; 214 bus_space_handle_t ioh; 215 size_t block_size; 216 217 if (bus_space_map(iot, va->va_addr, va->va_size, 0, &ioh)) { 218 printf(": can't map i/o space\n"); 219 return; 220 } 221 222 sc->sc_iot = iot; 223 sc->sc_ioh = ioh; 224 sc->sc_size = va->va_size; 225 sc->sc_status = 0; 226 227 /* 228 * Read entire CFI structure 229 */ 230 bus_space_write_2(iot, ioh, CFI_QUERY_OFFSET, CFI_READ_CFI_QUERY); 231 for (i = 0; i < CFI_TOTAL_SIZE; i++) { 232 sc->sc_cfi_raw[i] = bus_space_read_2(iot, ioh, i << 1); 233 } 234 bus_space_write_2(iot, ioh, 0, FLASH_RESET); 235 236 sc->sc_ops = find_command_set(sc->sc_cfi_raw[CFI_PRIM_COMM_REG0], 237 sc->sc_cfi_raw[CFI_PRIM_COMM_REG1]); 238 if (sc->sc_ops) { 239 printf(": using %s command set", sc->sc_ops->fo_name); 240 } else { 241 printf("opps sc->sc_ops is NULL\n"); 242 } 243 244 /* 245 * determine size of the largest block 246 */ 247 sc->sc_block_size = 0; 248 i = CFI_EBLK1_INFO_REG; 249 fence = sc->sc_cfi_raw[CFI_NUM_ERASE_BLK_REG] * CFI_EBLK_INFO_SIZE 250 + i; 251 for (; i < fence; i += CFI_EBLK_INFO_SIZE) { 252 if (sc->sc_cfi_raw[i + CFI_EBLK_INFO_NSECT0] == 0 253 && sc->sc_cfi_raw[i + CFI_EBLK_INFO_NSECT1] == 0) 254 continue; 255 block_size 256 = (sc->sc_cfi_raw[i + CFI_EBLK_INFO_SECSIZE0] << 8) 257 + (sc->sc_cfi_raw[i + CFI_EBLK_INFO_SECSIZE1] << 16); 258 if (sc->sc_block_size < block_size) 259 sc->sc_block_size = block_size; 260 } 261 262 if ((sc->sc_buf = malloc(sc->sc_block_size, M_DEVBUF, M_NOWAIT)) 263 == NULL) { 264 printf(": can't alloc buffer space\n"); 265 return; 266 } 267 268 sc->sc_write_buffer_size 269 = 1 << (sc->sc_cfi_raw[CFI_MAX_WBUF_SIZE_REG0] 270 + (sc->sc_cfi_raw[CFI_MAX_WBUF_SIZE_REG1] << 8)); 271 sc->sc_typ_word_prog_timo 272 = 1 << sc->sc_cfi_raw[CFI_TYP_WORD_PROG_REG]; 273 sc->sc_max_word_prog_timo 274 = 1 << sc->sc_cfi_raw[CFI_MAX_WORD_PROG_REG]; 275 sc->sc_typ_buffer_write_timo 276 = 1 << sc->sc_cfi_raw[CFI_TYP_BUF_WRITE_REG]; 277 sc->sc_max_buffer_write_timo 278 = 1 << sc->sc_cfi_raw[CFI_MAX_BUF_WRITE_REG]; 279 sc->sc_typ_block_erase_timo 280 = 1 << sc->sc_cfi_raw[CFI_TYP_BLOCK_ERASE_REG]; 281 sc->sc_max_block_erase_timo 282 = 1 << sc->sc_cfi_raw[CFI_MAX_BLOCK_ERASE_REG]; 283 284 printf("\n"); 285 286 #ifdef FLASH_DEBUG 287 printf("read_cfi: extract cfi\n"); 288 printf("max block size: %dbyte\n", sc->sc_block_size); 289 printf("write buffer size: %dbyte\n", sc->sc_write_buffer_size); 290 printf("typical word program timeout: %dusec\n", 291 sc->sc_typ_word_prog_timo); 292 printf("maximam word program timeout: %dusec (%d time of typ)\n", 293 sc->sc_typ_word_prog_timo * sc->sc_max_word_prog_timo, 294 sc->sc_max_word_prog_timo); 295 printf("typical buffer write timeout: %dusec\n", 296 sc->sc_typ_buffer_write_timo); 297 printf("maximam buffer write timeout: %dusec (%d time of typ)\n", 298 sc->sc_typ_buffer_write_timo * sc->sc_max_buffer_write_timo, 299 sc->sc_max_buffer_write_timo); 300 printf("typical block erase timeout: %dmsec\n", 301 sc->sc_typ_block_erase_timo); 302 printf("maximam block erase timeout: %dmsec (%d time of typ)\n", 303 sc->sc_typ_block_erase_timo * sc->sc_max_block_erase_timo, 304 sc->sc_max_block_erase_timo); 305 306 printf("read_cfi: dump cfi\n"); 307 for (i = 0; i < CFI_TOTAL_SIZE;) { 308 int j; 309 for (j = 0; j < 16; j++) { 310 printf("%02x ", sc->sc_cfi_raw[i++]); 311 } 312 printf("\n"); 313 } 314 #endif 315 } 316 317 int 318 flashopen(dev_t dev, int flag, int mode, struct proc *p) 319 { 320 struct flash_softc *sc; 321 322 if ((sc = device_lookup(&flash_cd, minor(dev))) == NULL) 323 return ENXIO; 324 if (sc->sc_status & FLASH_ST_BUSY) 325 return EBUSY; 326 sc->sc_status |= FLASH_ST_BUSY; 327 return 0; 328 } 329 330 int 331 flashclose(dev_t dev, int flag, int mode, struct proc *p) 332 { 333 struct flash_softc *sc; 334 335 sc = device_lookup(&flash_cd, minor(dev)); 336 sc->sc_status &= ~FLASH_ST_BUSY; 337 return 0; 338 } 339 340 int 341 flashread(dev_t dev, struct uio *uio, int flag) 342 { 343 struct flash_softc *sc; 344 bus_space_tag_t iot; 345 bus_space_handle_t ioh; 346 bus_size_t off; 347 int total; 348 int count; 349 int error; 350 351 sc = device_lookup(&flash_cd, minor(dev)); 352 iot = sc->sc_iot; 353 ioh = sc->sc_ioh; 354 355 off = uio->uio_offset; 356 total = min(sc->sc_size - off, uio->uio_resid); 357 358 while (total > 0) { 359 count = min(sc->sc_block_size, uio->uio_resid); 360 bus_space_read_region_1(iot, ioh, off, sc->sc_buf, count); 361 if ((error = uiomove(sc->sc_buf, count, uio)) != 0) 362 return error; 363 off += count; 364 total -= count; 365 } 366 return 0; 367 } 368 369 370 int 371 flashwrite(dev_t dev, struct uio *uio, int flag) 372 { 373 struct flash_softc *sc; 374 bus_space_tag_t iot; 375 bus_space_handle_t ioh; 376 bus_size_t off; 377 int stat; 378 int error; 379 380 sc = device_lookup(&flash_cd, minor(dev)); 381 382 if (sc->sc_size < uio->uio_offset + uio->uio_resid) 383 return ENOSPC; 384 if (uio->uio_offset % sc->sc_block_size) 385 return EINVAL; 386 if (uio->uio_resid % sc->sc_block_size) 387 return EINVAL; 388 389 iot = sc->sc_iot; 390 ioh = sc->sc_ioh; 391 392 for (off = uio->uio_offset; 393 uio->uio_resid > 0; 394 off += sc->sc_block_size) { 395 if ((error = uiomove(sc->sc_buf, sc->sc_block_size, uio)) != 0) 396 return error; 397 if (is_block_same(sc, off, sc->sc_buf)) 398 continue; 399 if ((stat = flash_block_erase(sc, off)) != 0) { 400 printf("block erase failed status = 0x%x\n", stat); 401 return EIO; 402 } 403 if ((stat = flash_block_write(sc, off)) != 0) { 404 printf("block write failed status = 0x%x\n", stat); 405 return EIO; 406 } 407 } 408 return 0; 409 } 410 411 /* 412 * XXX 413 * this function is too much specific for the device. 414 */ 415 static int 416 i28f128_probe(bus_space_tag_t iot, bus_space_handle_t ioh) 417 { 418 static const u_int8_t vendor_code[] = { 419 0x89, /* manufacturer code: intel */ 420 0x18, /* device code: 28F128 */ 421 }; 422 423 static const u_int8_t idstr[] = { 424 'Q', 'R', 'Y', 425 0x01, 0x00, 426 0x31, 0x00, 427 0xff 428 }; 429 430 int i; 431 432 /* start Common Flash Interface Query */ 433 bus_space_write_2(iot, ioh, 0, CFI_READ_CFI_QUERY); 434 /* read CFI Query ID string */ 435 for (i = 0; idstr[i] != 0xff; i++) { 436 if (bus_space_read_2(iot, ioh, (0x10 + i) << 1) != idstr[i]) 437 return 1; 438 } 439 440 /* read manufacturer code and device code */ 441 if (bus_space_read_2(iot, ioh, 0x00) != vendor_code[0]) 442 return 1; 443 if (bus_space_read_2(iot, ioh, 0x02) != vendor_code[1]) 444 return 1; 445 446 bus_space_write_2(iot, ioh, 0, I28F128_RESET); 447 return 0; 448 } 449 450 /* 451 * XXX 452 * this function is too much specific for the device. 453 */ 454 static int 455 mbm29160_probe(bus_space_tag_t iot, bus_space_handle_t ioh) 456 { 457 static const u_int16_t vendor_code[] = { 458 0x0004, /* manufacturer code: intel */ 459 0x2249, /* device code: 29LV160BE */ 460 }; 461 462 static const u_int8_t idstr[] = { 463 'Q', 'R', 'Y', 464 0x02, 0x00, 465 0x40, 0x00, 466 0xff 467 }; 468 469 int i; 470 471 /* start Common Flash Interface Query */ 472 bus_space_write_2(iot, ioh, 0xaa, CFI_READ_CFI_QUERY); 473 /* read CFI Query ID string */ 474 for (i = 0; idstr[i] != 0xff; i++) { 475 if (bus_space_read_2(iot, ioh, (0x10 + i) << 1) != idstr[i]) 476 return 1; 477 } 478 479 bus_space_write_2(iot, ioh, 0, 0xff); 480 481 /* read manufacturer code and device code */ 482 bus_space_write_2(iot, ioh, 0x555 << 1, 0xaa); 483 bus_space_write_2(iot, ioh, 0x2aa << 1, 0x55); 484 bus_space_write_2(iot, ioh, 0x555 << 1, 0x90); 485 if (bus_space_read_2(iot, ioh, 0x00) != vendor_code[0]) 486 return 1; 487 if (bus_space_read_2(iot, ioh, 0x02) != vendor_code[1]) 488 return 1; 489 490 bus_space_write_2(iot, ioh, 0, 0xff); 491 return 0; 492 } 493 494 static int 495 is_block_same(struct flash_softc *sc, bus_size_t offset, const void *bufp) 496 { 497 bus_space_tag_t iot = sc->sc_iot; 498 bus_space_handle_t ioh = sc->sc_ioh; 499 const u_int8_t *p = bufp; 500 int count = sc->sc_block_size; 501 502 while (count-- > 0) { 503 if (bus_space_read_1(iot, ioh, offset++) != *p++) 504 return 0; 505 } 506 return 1; 507 } 508 509 static int 510 intel_erase(struct flash_softc *sc, bus_size_t offset) 511 { 512 bus_space_tag_t iot = sc->sc_iot; 513 bus_space_handle_t ioh = sc->sc_ioh; 514 int status; 515 int i; 516 517 bus_space_write_2(iot, ioh, offset, I28F128_BLK_ERASE_1ST); 518 bus_space_write_2(iot, ioh, offset, I28F128_BLK_ERASE_2ND); 519 520 status = 0; 521 for (i = sc->sc_max_block_erase_timo; i > 0; i--) { 522 tsleep(sc, PRIBIO, "blockerase", 523 1 + (sc->sc_typ_block_erase_timo * hz) / 1000); 524 if ((status = bus_space_read_2(iot, ioh, offset)) 525 & I28F128_S_READY) 526 break; 527 } 528 529 bus_space_write_2(iot, ioh, offset, I28F128_CLEAR_STATUS); 530 bus_space_write_2(iot, ioh, offset, I28F128_RESET); 531 532 return status & (I28F128_S_ERASE_SUSPEND 533 | I28F128_S_COMSEQ_ERROR 534 | I28F128_S_ERASE_ERROR 535 | I28F128_S_BLOCK_LOCKED); 536 } 537 538 static int 539 intel_write(struct flash_softc *sc, bus_size_t offset) 540 { 541 bus_space_tag_t iot = sc->sc_iot; 542 bus_space_handle_t ioh = sc->sc_ioh; 543 int wbuf_size; 544 int timo; 545 int status; 546 bus_size_t fence; 547 int i; 548 const u_int16_t *p; 549 550 /* wbuf_size = size in u_int16_t */ 551 wbuf_size = sc->sc_write_buffer_size >> 1; 552 553 p = (u_int16_t *) sc->sc_buf; 554 fence = offset + sc->sc_block_size; 555 do { 556 status = 0; 557 for (timo = sc->sc_max_buffer_write_timo; timo > 0; timo--) { 558 bus_space_write_2(iot, ioh, offset, 559 I28F128_WRITE_BUFFER); 560 status = bus_space_read_2(iot, ioh, offset); 561 if (status & I28F128_XS_BUF_AVAIL) 562 break; 563 DELAY(sc->sc_typ_buffer_write_timo); 564 } 565 if (timo == 0) { 566 status |= FLASH_TIMEOUT; 567 goto errout; 568 } 569 570 bus_space_write_2(iot, ioh, offset, wbuf_size - 1); 571 572 for (i = wbuf_size; i > 0; i--, p++, offset += 2) 573 bus_space_write_2(iot, ioh, offset, *p); 574 575 bus_space_write_2(iot, ioh, offset, I28F128_WBUF_CONFIRM); 576 577 do { 578 bus_space_write_2(iot, ioh, offset, 579 I28F128_READ_STATUS); 580 status = bus_space_read_2(iot, ioh, offset); 581 } while (!(status & I28F128_S_READY)); 582 583 } while (offset < fence); 584 585 bus_space_write_2(iot, ioh, offset, I28F128_CLEAR_STATUS); 586 bus_space_write_2(iot, ioh, offset, I28F128_RESET); 587 588 return 0; 589 590 errout: 591 bus_space_write_2(iot, ioh, offset, I28F128_CLEAR_STATUS); 592 bus_space_write_2(iot, ioh, offset, I28F128_RESET); 593 594 status &= (FLASH_TIMEOUT 595 | I28F128_S_PROG_ERROR 596 | I28F128_S_COMSEQ_ERROR 597 | I28F128_S_LOW_VOLTAGE 598 | I28F128_S_PROG_SUSPEND 599 | I28F128_S_BLOCK_LOCKED); 600 return status; 601 } 602 603 static int 604 amd_erase_sector(struct flash_softc *sc, bus_size_t offset) 605 { 606 bus_space_tag_t iot = sc->sc_iot; 607 bus_space_handle_t ioh = sc->sc_ioh; 608 int i; 609 610 DPRINTF(("amd_erase_sector offset = %08lx\n", offset)); 611 612 bus_space_write_2(iot, ioh, 613 MBM29LV160_COMM_ADDR0, MBM29LV160_COMM_CMD0); 614 bus_space_write_2(iot, ioh, 615 MBM29LV160_COMM_ADDR1, MBM29LV160_COMM_CMD1); 616 bus_space_write_2(iot, ioh, 617 MBM29LV160_COMM_ADDR2, MBM29LV160_ESECT_CMD2); 618 bus_space_write_2(iot, ioh, 619 MBM29LV160_COMM_ADDR3, MBM29LV160_ESECT_CMD3); 620 bus_space_write_2(iot, ioh, 621 MBM29LV160_COMM_ADDR4, MBM29LV160_ESECT_CMD4); 622 bus_space_write_2(iot, ioh, offset, MBM29LV160_ESECT_CMD5); 623 624 for (i = sc->sc_max_block_erase_timo; i > 0; i--) { 625 tsleep(sc, PRIBIO, "blockerase", 626 1 + (sc->sc_typ_block_erase_timo * hz) / 1000); 627 if (bus_space_read_2(iot, ioh, offset) == 0xffff) 628 return 0; 629 } 630 631 return FLASH_TIMEOUT; 632 } 633 634 static int 635 amd_erase(struct flash_softc *sc, bus_size_t offset) 636 { 637 static const struct mbm29lv_subsect { 638 u_int16_t devcode; 639 u_int32_t subsect_mask; 640 u_int32_t subsect_addr; 641 } subsect[] = { 642 { 643 MBM29LV160TE_DEVCODE, 644 MBM29LV160_SUBSECT_MASK, 645 MBM29LV160TE_SUBSECT_ADDR 646 }, 647 { 648 MBM29LV160BE_DEVCODE, 649 MBM29LV160_SUBSECT_MASK, 650 MBM29LV160BE_SUBSECT_ADDR 651 }, 652 { 0, 0, 0 } 653 }; 654 655 bus_space_tag_t iot = sc->sc_iot; 656 bus_space_handle_t ioh = sc->sc_ioh; 657 u_int16_t devcode; 658 const struct mbm29lv_subsect *ss; 659 bus_size_t fence; 660 int step; 661 int status; 662 663 bus_space_write_2(iot, ioh, 664 MBM29LV160_COMM_ADDR0, MBM29LV160_COMM_CMD0); 665 bus_space_write_2(iot, ioh, 666 MBM29LV160_COMM_ADDR1, MBM29LV160_COMM_CMD1); 667 bus_space_write_2(iot, ioh, 668 MBM29LV160_COMM_ADDR2, MBM29LV160_SIGN_CMD2); 669 devcode = bus_space_read_2(iot, ioh, MBM29LV160_DEVCODE_REG); 670 671 for (ss = subsect; ss->devcode; ss++) { 672 if (ss->devcode == devcode) 673 break; 674 } 675 if (ss->devcode == 0) { 676 printf("flash: amd_erase(): unknown device code %04x\n", 677 devcode); 678 return -1; 679 } 680 681 DPRINTF(("flash: amd_erase(): devcode = %04x subsect = %08x\n", 682 devcode, ss->subsect_addr)); 683 684 fence = offset + sc->sc_block_size; 685 step = (offset & ss->subsect_mask) == ss->subsect_addr 686 ? MBM29LV160_SUBSECT_SIZE : MBM29LV160_SECT_SIZE; 687 do { 688 if ((status = amd_erase_sector(sc, offset)) != 0) 689 return status; 690 offset += step; 691 } while (offset < fence); 692 693 return 0; 694 } 695 696 static int 697 amd_write(struct flash_softc *sc, bus_size_t offset) 698 { 699 bus_space_tag_t iot = sc->sc_iot; 700 bus_space_handle_t ioh = sc->sc_ioh; 701 int timo; 702 bus_size_t fence; 703 const u_int16_t *p; 704 705 p = (u_int16_t *) sc->sc_buf; 706 fence = offset + sc->sc_block_size; 707 do { 708 bus_space_write_2(iot, ioh, 709 MBM29LV160_COMM_ADDR0, 710 MBM29LV160_COMM_CMD0); 711 bus_space_write_2(iot, ioh, 712 MBM29LV160_COMM_ADDR1, 713 MBM29LV160_COMM_CMD1); 714 bus_space_write_2(iot, ioh, 715 MBM29LV160_COMM_ADDR2, 716 MBM29LV160_PROG_CMD2); 717 bus_space_write_2(iot, ioh, offset, *p); 718 719 for (timo = sc->sc_max_word_prog_timo; timo > 0; timo--) { 720 if (bus_space_read_2(iot, ioh, offset) == *p) 721 break; 722 DELAY(sc->sc_typ_word_prog_timo); 723 } 724 if (timo == 0) 725 return FLASH_TIMEOUT; 726 727 p++; 728 offset += 2; 729 } while (offset < fence); 730 731 return 0; 732 } 733
Indexes created Thu Oct 02 07:10:07 GMT 2025