flash_vrip.c revision 1.6
1 /* $NetBSD: flash_vrip.c,v 1.6 2008/04/28 20:23:22 martin Exp $ */ 2 3 /* 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Naoto Shimazaki of YOKOGAWA Electric Corporation. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Flash Memory Driver 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: flash_vrip.c,v 1.6 2008/04/28 20:23:22 martin Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/conf.h> 41 #include <sys/device.h> 42 #include <sys/kernel.h> 43 #include <sys/malloc.h> 44 #include <sys/proc.h> 45 #include <sys/systm.h> 46 47 #include <machine/bus.h> 48 49 #include <hpcmips/vr/vripif.h> 50 #include <hpcmips/vr/cfireg.h> 51 #include <hpcmips/vr/flashreg.h> 52 #include <hpcmips/vr/flashvar.h> 53 54 #ifdef FLASH_DEBUG 55 int flash_debug = 0; 56 #define DPRINTF(x) if (flash_debug) printf x 57 #else 58 #define DPRINTF(x) 59 #endif 60 61 static int flash_probe(struct device *, struct cfdata *, void *); 62 static void flash_attach(struct device *, struct device *, void *); 63 64 const static struct flashops * find_command_set(u_int8_t cmdset0, 65 u_int8_t cmdset1); 66 static int i28f128_probe(bus_space_tag_t, bus_space_handle_t); 67 static int mbm29160_probe(bus_space_tag_t, bus_space_handle_t); 68 static int is_block_same(struct flash_softc *, bus_size_t, const void *); 69 static int probe_cfi(bus_space_tag_t iot, bus_space_handle_t ioh); 70 71 static int intel_erase(struct flash_softc *, bus_size_t); 72 static int intel_write(struct flash_softc *, bus_size_t); 73 static int amd_erase(struct flash_softc *, bus_size_t); 74 static int amd_write(struct flash_softc *, bus_size_t); 75 76 extern struct cfdriver flash_cd; 77 78 CFATTACH_DECL(flash_vrip, sizeof(struct flash_softc), 79 flash_probe, flash_attach, NULL, NULL); 80 81 dev_type_open(flashopen); 82 dev_type_close(flashclose); 83 dev_type_read(flashread); 84 dev_type_write(flashwrite); 85 86 const struct cdevsw flash_cdevsw = { 87 flashopen, flashclose, flashread, flashwrite, noioctl, 88 nostop, notty, nopoll, nommap, nokqfilter, 89 }; 90 91 static const struct flash_command_set { 92 u_int8_t fc_set0; 93 u_int8_t fc_set1; 94 struct flashops fc_ops; 95 } flash_cmd[] = { 96 { 97 .fc_set0 = CFI_COMMSET_INTEL0, 98 .fc_set1 = CFI_COMMSET_INTEL1, 99 .fc_ops = { 100 .fo_name = "Intel", 101 .fo_erase = intel_erase, 102 .fo_write = intel_write, 103 } 104 }, 105 { 106 .fc_set0 = CFI_COMMSET_AMDFJITU0, 107 .fc_set1 = CFI_COMMSET_AMDFJITU1, 108 .fc_ops = { 109 .fo_name = "AMD/Fujitsu", 110 .fo_erase = amd_erase, 111 .fo_write = amd_write, 112 } 113 }, 114 { 115 .fc_set0 = 0, 116 .fc_set1 = 0, 117 .fc_ops = { 118 .fo_name = NULL, 119 .fo_erase = NULL, 120 .fo_write = NULL, 121 } 122 } 123 }; 124 125 126 const static struct flashops * 127 find_command_set(u_int8_t cmdset0, u_int8_t cmdset1) 128 { 129 const struct flash_command_set *fc; 130 131 for (fc = flash_cmd; fc->fc_ops.fo_name; fc++) { 132 if (cmdset0 == fc->fc_set0 && cmdset1 == fc->fc_set1) 133 return &fc->fc_ops; 134 } 135 return NULL; 136 } 137 138 static int 139 probe_cfi(bus_space_tag_t iot, bus_space_handle_t ioh) 140 { 141 const u_int8_t *idstr = CFI_QUERY_ID_STR; 142 int i; 143 u_int8_t cmdset0; 144 u_int8_t cmdset1; 145 146 /* start Common Flash Interface Query */ 147 bus_space_write_2(iot, ioh, CFI_QUERY_OFFSET, CFI_READ_CFI_QUERY); 148 149 /* read CFI Query ID string */ 150 i = CFI_QUERY_ID_STR_REG << 1; 151 do { 152 if (bus_space_read_2(iot, ioh, i) != *idstr) { 153 bus_space_write_2(iot, ioh, 0, FLASH_RESET); 154 return 1; 155 } 156 i += 2; 157 idstr++; 158 } while (*idstr); 159 160 cmdset0 = bus_space_read_2(iot, ioh, CFI_PRIM_COMM_REG0 << 1); 161 cmdset1 = bus_space_read_2(iot, ioh, CFI_PRIM_COMM_REG1 << 1); 162 163 /* switch flash to read mode */ 164 bus_space_write_2(iot, ioh, 0, FLASH_RESET); 165 166 if (!find_command_set(cmdset0, cmdset1)) 167 return 1; 168 169 return 0; 170 } 171 172 static int 173 flash_probe(struct device *parent, struct cfdata *match, void *aux) 174 { 175 struct vrip_attach_args *va = aux; 176 bus_space_handle_t ioh; 177 178 if (bus_space_map(va->va_iot, va->va_addr, va->va_size, 0, &ioh)) 179 return 0; 180 if (!probe_cfi(va->va_iot, ioh)) { 181 DPRINTF("CFI ID str and command set recognized\n"); 182 goto detect; 183 } 184 if (!i28f128_probe(va->va_iot, ioh)) { 185 DPRINTF("28F128 detected\n"); 186 goto detect; 187 } 188 if (!mbm29160_probe(va->va_iot, ioh)) { 189 DPRINTF("29LV160 detected\n"); 190 goto detect; 191 } 192 return 0; 193 194 detect: 195 bus_space_unmap(va->va_iot, ioh, va->va_size); 196 return 1; 197 } 198 199 static void 200 flash_attach(struct device *parent, struct device *self, void *aux) 201 { 202 struct flash_softc *sc = (void *) self; 203 struct vrip_attach_args *va = aux; 204 int i; 205 int fence; 206 bus_space_tag_t iot = va->va_iot; 207 bus_space_handle_t ioh; 208 size_t block_size; 209 210 if (bus_space_map(iot, va->va_addr, va->va_size, 0, &ioh)) { 211 printf(": can't map i/o space\n"); 212 return; 213 } 214 215 sc->sc_iot = iot; 216 sc->sc_ioh = ioh; 217 sc->sc_size = va->va_size; 218 sc->sc_status = 0; 219 220 /* 221 * Read entire CFI structure 222 */ 223 bus_space_write_2(iot, ioh, CFI_QUERY_OFFSET, CFI_READ_CFI_QUERY); 224 for (i = 0; i < CFI_TOTAL_SIZE; i++) { 225 sc->sc_cfi_raw[i] = bus_space_read_2(iot, ioh, i << 1); 226 } 227 bus_space_write_2(iot, ioh, 0, FLASH_RESET); 228 229 sc->sc_ops = find_command_set(sc->sc_cfi_raw[CFI_PRIM_COMM_REG0], 230 sc->sc_cfi_raw[CFI_PRIM_COMM_REG1]); 231 if (sc->sc_ops) { 232 printf(": using %s command set", sc->sc_ops->fo_name); 233 } else { 234 printf("opps sc->sc_ops is NULL\n"); 235 } 236 237 /* 238 * determine size of the largest block 239 */ 240 sc->sc_block_size = 0; 241 i = CFI_EBLK1_INFO_REG; 242 fence = sc->sc_cfi_raw[CFI_NUM_ERASE_BLK_REG] * CFI_EBLK_INFO_SIZE 243 + i; 244 for (; i < fence; i += CFI_EBLK_INFO_SIZE) { 245 if (sc->sc_cfi_raw[i + CFI_EBLK_INFO_NSECT0] == 0 246 && sc->sc_cfi_raw[i + CFI_EBLK_INFO_NSECT1] == 0) 247 continue; 248 block_size 249 = (sc->sc_cfi_raw[i + CFI_EBLK_INFO_SECSIZE0] << 8) 250 + (sc->sc_cfi_raw[i + CFI_EBLK_INFO_SECSIZE1] << 16); 251 if (sc->sc_block_size < block_size) 252 sc->sc_block_size = block_size; 253 } 254 255 if ((sc->sc_buf = malloc(sc->sc_block_size, M_DEVBUF, M_NOWAIT)) 256 == NULL) { 257 printf(": can't alloc buffer space\n"); 258 return; 259 } 260 261 sc->sc_write_buffer_size 262 = 1 << (sc->sc_cfi_raw[CFI_MAX_WBUF_SIZE_REG0] 263 + (sc->sc_cfi_raw[CFI_MAX_WBUF_SIZE_REG1] << 8)); 264 sc->sc_typ_word_prog_timo 265 = 1 << sc->sc_cfi_raw[CFI_TYP_WORD_PROG_REG]; 266 sc->sc_max_word_prog_timo 267 = 1 << sc->sc_cfi_raw[CFI_MAX_WORD_PROG_REG]; 268 sc->sc_typ_buffer_write_timo 269 = 1 << sc->sc_cfi_raw[CFI_TYP_BUF_WRITE_REG]; 270 sc->sc_max_buffer_write_timo 271 = 1 << sc->sc_cfi_raw[CFI_MAX_BUF_WRITE_REG]; 272 sc->sc_typ_block_erase_timo 273 = 1 << sc->sc_cfi_raw[CFI_TYP_BLOCK_ERASE_REG]; 274 sc->sc_max_block_erase_timo 275 = 1 << sc->sc_cfi_raw[CFI_MAX_BLOCK_ERASE_REG]; 276 277 printf("\n"); 278 279 #ifdef FLASH_DEBUG 280 printf("read_cfi: extract cfi\n"); 281 printf("max block size: %dbyte\n", sc->sc_block_size); 282 printf("write buffer size: %dbyte\n", sc->sc_write_buffer_size); 283 printf("typical word program timeout: %dusec\n", 284 sc->sc_typ_word_prog_timo); 285 printf("maximam word program timeout: %dusec (%d time of typ)\n", 286 sc->sc_typ_word_prog_timo * sc->sc_max_word_prog_timo, 287 sc->sc_max_word_prog_timo); 288 printf("typical buffer write timeout: %dusec\n", 289 sc->sc_typ_buffer_write_timo); 290 printf("maximam buffer write timeout: %dusec (%d time of typ)\n", 291 sc->sc_typ_buffer_write_timo * sc->sc_max_buffer_write_timo, 292 sc->sc_max_buffer_write_timo); 293 printf("typical block erase timeout: %dmsec\n", 294 sc->sc_typ_block_erase_timo); 295 printf("maximam block erase timeout: %dmsec (%d time of typ)\n", 296 sc->sc_typ_block_erase_timo * sc->sc_max_block_erase_timo, 297 sc->sc_max_block_erase_timo); 298 299 printf("read_cfi: dump cfi\n"); 300 for (i = 0; i < CFI_TOTAL_SIZE;) { 301 int j; 302 for (j = 0; j < 16; j++) { 303 printf("%02x ", sc->sc_cfi_raw[i++]); 304 } 305 printf("\n"); 306 } 307 #endif 308 } 309 310 int 311 flashopen(dev_t dev, int flag, int mode, struct lwp *l) 312 { 313 struct flash_softc *sc; 314 315 if ((sc = device_lookup(&flash_cd, minor(dev))) == NULL) 316 return ENXIO; 317 if (sc->sc_status & FLASH_ST_BUSY) 318 return EBUSY; 319 sc->sc_status |= FLASH_ST_BUSY; 320 return 0; 321 } 322 323 int 324 flashclose(dev_t dev, int flag, int mode, struct lwp *l) 325 { 326 struct flash_softc *sc; 327 328 sc = device_lookup(&flash_cd, minor(dev)); 329 sc->sc_status &= ~FLASH_ST_BUSY; 330 return 0; 331 } 332 333 int 334 flashread(dev_t dev, struct uio *uio, int flag) 335 { 336 struct flash_softc *sc; 337 bus_space_tag_t iot; 338 bus_space_handle_t ioh; 339 bus_size_t off; 340 int total; 341 int count; 342 int error; 343 344 sc = device_lookup(&flash_cd, minor(dev)); 345 iot = sc->sc_iot; 346 ioh = sc->sc_ioh; 347 348 off = uio->uio_offset; 349 total = min(sc->sc_size - off, uio->uio_resid); 350 351 while (total > 0) { 352 count = min(sc->sc_block_size, uio->uio_resid); 353 bus_space_read_region_1(iot, ioh, off, sc->sc_buf, count); 354 if ((error = uiomove(sc->sc_buf, count, uio)) != 0) 355 return error; 356 off += count; 357 total -= count; 358 } 359 return 0; 360 } 361 362 363 int 364 flashwrite(dev_t dev, struct uio *uio, int flag) 365 { 366 struct flash_softc *sc; 367 bus_space_tag_t iot; 368 bus_space_handle_t ioh; 369 bus_size_t off; 370 int stat; 371 int error; 372 373 sc = device_lookup(&flash_cd, minor(dev)); 374 375 if (sc->sc_size < uio->uio_offset + uio->uio_resid) 376 return ENOSPC; 377 if (uio->uio_offset % sc->sc_block_size) 378 return EINVAL; 379 if (uio->uio_resid % sc->sc_block_size) 380 return EINVAL; 381 382 iot = sc->sc_iot; 383 ioh = sc->sc_ioh; 384 385 for (off = uio->uio_offset; 386 uio->uio_resid > 0; 387 off += sc->sc_block_size) { 388 if ((error = uiomove(sc->sc_buf, sc->sc_block_size, uio)) != 0) 389 return error; 390 if (is_block_same(sc, off, sc->sc_buf)) 391 continue; 392 if ((stat = flash_block_erase(sc, off)) != 0) { 393 printf("block erase failed status = 0x%x\n", stat); 394 return EIO; 395 } 396 if ((stat = flash_block_write(sc, off)) != 0) { 397 printf("block write failed status = 0x%x\n", stat); 398 return EIO; 399 } 400 } 401 return 0; 402 } 403 404 /* 405 * XXX 406 * this function is too much specific for the device. 407 */ 408 static int 409 i28f128_probe(bus_space_tag_t iot, bus_space_handle_t ioh) 410 { 411 static const u_int8_t vendor_code[] = { 412 0x89, /* manufacturer code: intel */ 413 0x18, /* device code: 28F128 */ 414 }; 415 416 static const u_int8_t idstr[] = { 417 'Q', 'R', 'Y', 418 0x01, 0x00, 419 0x31, 0x00, 420 0xff 421 }; 422 423 int i; 424 425 /* start Common Flash Interface Query */ 426 bus_space_write_2(iot, ioh, 0, CFI_READ_CFI_QUERY); 427 /* read CFI Query ID string */ 428 for (i = 0; idstr[i] != 0xff; i++) { 429 if (bus_space_read_2(iot, ioh, (0x10 + i) << 1) != idstr[i]) 430 return 1; 431 } 432 433 /* read manufacturer code and device code */ 434 if (bus_space_read_2(iot, ioh, 0x00) != vendor_code[0]) 435 return 1; 436 if (bus_space_read_2(iot, ioh, 0x02) != vendor_code[1]) 437 return 1; 438 439 bus_space_write_2(iot, ioh, 0, I28F128_RESET); 440 return 0; 441 } 442 443 /* 444 * XXX 445 * this function is too much specific for the device. 446 */ 447 static int 448 mbm29160_probe(bus_space_tag_t iot, bus_space_handle_t ioh) 449 { 450 static const u_int16_t vendor_code[] = { 451 0x0004, /* manufacturer code: intel */ 452 0x2249, /* device code: 29LV160BE */ 453 }; 454 455 static const u_int8_t idstr[] = { 456 'Q', 'R', 'Y', 457 0x02, 0x00, 458 0x40, 0x00, 459 0xff 460 }; 461 462 int i; 463 464 /* start Common Flash Interface Query */ 465 bus_space_write_2(iot, ioh, 0xaa, CFI_READ_CFI_QUERY); 466 /* read CFI Query ID string */ 467 for (i = 0; idstr[i] != 0xff; i++) { 468 if (bus_space_read_2(iot, ioh, (0x10 + i) << 1) != idstr[i]) 469 return 1; 470 } 471 472 bus_space_write_2(iot, ioh, 0, 0xff); 473 474 /* read manufacturer code and device code */ 475 bus_space_write_2(iot, ioh, 0x555 << 1, 0xaa); 476 bus_space_write_2(iot, ioh, 0x2aa << 1, 0x55); 477 bus_space_write_2(iot, ioh, 0x555 << 1, 0x90); 478 if (bus_space_read_2(iot, ioh, 0x00) != vendor_code[0]) 479 return 1; 480 if (bus_space_read_2(iot, ioh, 0x02) != vendor_code[1]) 481 return 1; 482 483 bus_space_write_2(iot, ioh, 0, 0xff); 484 return 0; 485 } 486 487 static int 488 is_block_same(struct flash_softc *sc, bus_size_t offset, const void *bufp) 489 { 490 bus_space_tag_t iot = sc->sc_iot; 491 bus_space_handle_t ioh = sc->sc_ioh; 492 const u_int8_t *p = bufp; 493 int count = sc->sc_block_size; 494 495 while (count-- > 0) { 496 if (bus_space_read_1(iot, ioh, offset++) != *p++) 497 return 0; 498 } 499 return 1; 500 } 501 502 static int 503 intel_erase(struct flash_softc *sc, bus_size_t offset) 504 { 505 bus_space_tag_t iot = sc->sc_iot; 506 bus_space_handle_t ioh = sc->sc_ioh; 507 int status; 508 int i; 509 510 bus_space_write_2(iot, ioh, offset, I28F128_BLK_ERASE_1ST); 511 bus_space_write_2(iot, ioh, offset, I28F128_BLK_ERASE_2ND); 512 513 status = 0; 514 for (i = sc->sc_max_block_erase_timo; i > 0; i--) { 515 tsleep(sc, PRIBIO, "blockerase", 516 1 + (sc->sc_typ_block_erase_timo * hz) / 1000); 517 if ((status = bus_space_read_2(iot, ioh, offset)) 518 & I28F128_S_READY) 519 break; 520 } 521 if (i == 0) 522 status |= FLASH_TIMEOUT; 523 524 bus_space_write_2(iot, ioh, offset, I28F128_CLEAR_STATUS); 525 bus_space_write_2(iot, ioh, offset, I28F128_RESET); 526 527 return status & (FLASH_TIMEOUT 528 | I28F128_S_ERASE_SUSPEND 529 | I28F128_S_COMSEQ_ERROR 530 | I28F128_S_ERASE_ERROR 531 | I28F128_S_BLOCK_LOCKED); 532 } 533 534 static int 535 intel_write(struct flash_softc *sc, bus_size_t offset) 536 { 537 bus_space_tag_t iot = sc->sc_iot; 538 bus_space_handle_t ioh = sc->sc_ioh; 539 int wbuf_size; 540 int timo; 541 int status; 542 bus_size_t fence; 543 int i; 544 const u_int16_t *p; 545 546 /* wbuf_size = size in u_int16_t */ 547 wbuf_size = sc->sc_write_buffer_size >> 1; 548 549 p = (u_int16_t *) sc->sc_buf; 550 fence = offset + sc->sc_block_size; 551 do { 552 status = 0; 553 for (timo = sc->sc_max_buffer_write_timo; timo > 0; timo--) { 554 bus_space_write_2(iot, ioh, offset, 555 I28F128_WRITE_BUFFER); 556 status = bus_space_read_2(iot, ioh, offset); 557 if (status & I28F128_XS_BUF_AVAIL) 558 break; 559 DELAY(sc->sc_typ_buffer_write_timo); 560 } 561 if (timo == 0) { 562 status |= FLASH_TIMEOUT; 563 goto errout; 564 } 565 566 bus_space_write_2(iot, ioh, offset, wbuf_size - 1); 567 568 for (i = wbuf_size; i > 0; i--, p++, offset += 2) 569 bus_space_write_2(iot, ioh, offset, *p); 570 571 bus_space_write_2(iot, ioh, offset, I28F128_WBUF_CONFIRM); 572 573 do { 574 bus_space_write_2(iot, ioh, offset, 575 I28F128_READ_STATUS); 576 status = bus_space_read_2(iot, ioh, offset); 577 } while (!(status & I28F128_S_READY)); 578 579 } while (offset < fence); 580 581 bus_space_write_2(iot, ioh, offset, I28F128_CLEAR_STATUS); 582 bus_space_write_2(iot, ioh, offset, I28F128_RESET); 583 584 return 0; 585 586 errout: 587 bus_space_write_2(iot, ioh, offset, I28F128_CLEAR_STATUS); 588 bus_space_write_2(iot, ioh, offset, I28F128_RESET); 589 590 status &= (FLASH_TIMEOUT 591 | I28F128_S_PROG_ERROR 592 | I28F128_S_COMSEQ_ERROR 593 | I28F128_S_LOW_VOLTAGE 594 | I28F128_S_PROG_SUSPEND 595 | I28F128_S_BLOCK_LOCKED); 596 return status; 597 } 598 599 static int 600 amd_erase_sector(struct flash_softc *sc, bus_size_t offset) 601 { 602 bus_space_tag_t iot = sc->sc_iot; 603 bus_space_handle_t ioh = sc->sc_ioh; 604 int i; 605 606 DPRINTF(("amd_erase_sector offset = %08lx\n", offset)); 607 608 bus_space_write_2(iot, ioh, 609 MBM29LV160_COMM_ADDR0, MBM29LV160_COMM_CMD0); 610 bus_space_write_2(iot, ioh, 611 MBM29LV160_COMM_ADDR1, MBM29LV160_COMM_CMD1); 612 bus_space_write_2(iot, ioh, 613 MBM29LV160_COMM_ADDR2, MBM29LV160_ESECT_CMD2); 614 bus_space_write_2(iot, ioh, 615 MBM29LV160_COMM_ADDR3, MBM29LV160_ESECT_CMD3); 616 bus_space_write_2(iot, ioh, 617 MBM29LV160_COMM_ADDR4, MBM29LV160_ESECT_CMD4); 618 bus_space_write_2(iot, ioh, offset, MBM29LV160_ESECT_CMD5); 619 620 for (i = sc->sc_max_block_erase_timo; i > 0; i--) { 621 tsleep(sc, PRIBIO, "blockerase", 622 1 + (sc->sc_typ_block_erase_timo * hz) / 1000); 623 if (bus_space_read_2(iot, ioh, offset) == 0xffff) 624 return 0; 625 } 626 627 return FLASH_TIMEOUT; 628 } 629 630 static int 631 amd_erase(struct flash_softc *sc, bus_size_t offset) 632 { 633 static const struct mbm29lv_subsect { 634 u_int16_t devcode; 635 u_int32_t subsect_mask; 636 u_int32_t subsect_addr; 637 } subsect[] = { 638 { 639 MBM29LV160TE_DEVCODE, 640 MBM29LV160_SUBSECT_MASK, 641 MBM29LV160TE_SUBSECT_ADDR 642 }, 643 { 644 MBM29LV160BE_DEVCODE, 645 MBM29LV160_SUBSECT_MASK, 646 MBM29LV160BE_SUBSECT_ADDR 647 }, 648 { 0, 0, 0 } 649 }; 650 651 bus_space_tag_t iot = sc->sc_iot; 652 bus_space_handle_t ioh = sc->sc_ioh; 653 u_int16_t devcode; 654 const struct mbm29lv_subsect *ss; 655 bus_size_t fence; 656 int step; 657 int status; 658 659 bus_space_write_2(iot, ioh, 660 MBM29LV160_COMM_ADDR0, MBM29LV160_COMM_CMD0); 661 bus_space_write_2(iot, ioh, 662 MBM29LV160_COMM_ADDR1, MBM29LV160_COMM_CMD1); 663 bus_space_write_2(iot, ioh, 664 MBM29LV160_COMM_ADDR2, MBM29LV160_SIGN_CMD2); 665 devcode = bus_space_read_2(iot, ioh, MBM29LV160_DEVCODE_REG); 666 667 for (ss = subsect; ss->devcode; ss++) { 668 if (ss->devcode == devcode) 669 break; 670 } 671 if (ss->devcode == 0) { 672 printf("flash: amd_erase(): unknown device code %04x\n", 673 devcode); 674 return -1; 675 } 676 677 DPRINTF(("flash: amd_erase(): devcode = %04x subsect = %08x\n", 678 devcode, ss->subsect_addr)); 679 680 fence = offset + sc->sc_block_size; 681 step = (offset & ss->subsect_mask) == ss->subsect_addr 682 ? MBM29LV160_SUBSECT_SIZE : MBM29LV160_SECT_SIZE; 683 do { 684 if ((status = amd_erase_sector(sc, offset)) != 0) 685 return status; 686 offset += step; 687 } while (offset < fence); 688 689 return 0; 690 } 691 692 static int 693 amd_write(struct flash_softc *sc, bus_size_t offset) 694 { 695 bus_space_tag_t iot = sc->sc_iot; 696 bus_space_handle_t ioh = sc->sc_ioh; 697 int timo; 698 bus_size_t fence; 699 const u_int16_t *p; 700 701 p = (u_int16_t *) sc->sc_buf; 702 fence = offset + sc->sc_block_size; 703 do { 704 bus_space_write_2(iot, ioh, 705 MBM29LV160_COMM_ADDR0, 706 MBM29LV160_COMM_CMD0); 707 bus_space_write_2(iot, ioh, 708 MBM29LV160_COMM_ADDR1, 709 MBM29LV160_COMM_CMD1); 710 bus_space_write_2(iot, ioh, 711 MBM29LV160_COMM_ADDR2, 712 MBM29LV160_PROG_CMD2); 713 bus_space_write_2(iot, ioh, offset, *p); 714 715 for (timo = sc->sc_max_word_prog_timo; timo > 0; timo--) { 716 if (bus_space_read_2(iot, ioh, offset) == *p) 717 break; 718 DELAY(sc->sc_typ_word_prog_timo); 719 } 720 if (timo == 0) 721 return FLASH_TIMEOUT; 722 723 p++; 724 offset += 2; 725 } while (offset < fence); 726 727 return 0; 728 } 729
Indexes created Wed Oct 15 16:09:53 GMT 2025