flashreg.h revision 1.1 1 1.1 igy /* $NetBSD: flashreg.h,v 1.1 2003/05/01 07:02:04 igy Exp $ */
2 1.1 igy
3 1.1 igy /*
4 1.1 igy * Copyright (c) 2002 The NetBSD Foundation, Inc.
5 1.1 igy * All rights reserved.
6 1.1 igy *
7 1.1 igy * This code is derived from software contributed to The NetBSD Foundation
8 1.1 igy * by Naoto Shimazaki of YOKOGAWA Electric Corporation.
9 1.1 igy *
10 1.1 igy * Redistribution and use in source and binary forms, with or without
11 1.1 igy * modification, are permitted provided that the following conditions
12 1.1 igy * are met:
13 1.1 igy * 1. Redistributions of source code must retain the above copyright
14 1.1 igy * notice, this list of conditions and the following disclaimer.
15 1.1 igy * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 igy * notice, this list of conditions and the following disclaimer in the
17 1.1 igy * documentation and/or other materials provided with the distribution.
18 1.1 igy * 3. All advertising materials mentioning features or use of this software
19 1.1 igy * must display the following acknowledgement:
20 1.1 igy * This product includes software developed by the NetBSD
21 1.1 igy * Foundation, Inc. and its contributors.
22 1.1 igy * 4. Neither the name of The NetBSD Foundation nor the names of its
23 1.1 igy * contributors may be used to endorse or promote products derived
24 1.1 igy * from this software without specific prior written permission.
25 1.1 igy *
26 1.1 igy * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 1.1 igy * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 1.1 igy * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 1.1 igy * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 1.1 igy * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 1.1 igy * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 1.1 igy * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 1.1 igy * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 1.1 igy * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 1.1 igy * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 1.1 igy * POSSIBILITY OF SUCH DAMAGE.
37 1.1 igy */
38 1.1 igy
39 1.1 igy /*
40 1.1 igy * Intel 28F128 Flash Memory registers
41 1.1 igy */
42 1.1 igy
43 1.1 igy #define I28F128_BLOCK_SIZE 0x20000 /* 128Kbyte */
44 1.1 igy #define I28F128_BLOCK_MASK 0x1ffff /* 128Kbyte */
45 1.1 igy
46 1.1 igy #define I28F128_MANUFACT 0x89
47 1.1 igy #define I28F128_DEVCODE 0x18
48 1.1 igy #define I28F128_PRIM_COMM0 0x01
49 1.1 igy #define I28F128_PRIM_COMM1 0x00
50 1.1 igy #define I28F128_PRIM_EXT_TBL0 0x31
51 1.1 igy #define I28F128_PRIM_EXT_TBL1 0x00
52 1.1 igy
53 1.1 igy #define I28F128_RESET 0xff
54 1.1 igy #define I28F128_READ_ARRAY I28F128_RESET
55 1.1 igy #define I28F128_READ_ID 0x90
56 1.1 igy #define I28F128_READ_STATUS 0x70
57 1.1 igy #define I28F128_CLEAR_STATUS 0x50
58 1.1 igy
59 1.1 igy #define I28F128_BLK_ERASE_1ST 0x20
60 1.1 igy #define I28F128_BLK_ERASE_2ND 0xd0
61 1.1 igy #define I28F128_WORDBYTE_PROG 0x40
62 1.1 igy #define I28F128_WRITE_BUFFER 0xe8
63 1.1 igy #define I28F128_WBUF_CONFIRM 0xd0
64 1.1 igy
65 1.1 igy #define I28F128_S_READY 0x80
66 1.1 igy #define I28F128_S_ERASE_SUSPEND 0x40
67 1.1 igy #define I28F128_S_COMSEQ_ERROR 0x30
68 1.1 igy #define I28F128_S_ERASE_ERROR 0x20
69 1.1 igy #define I28F128_S_PROG_ERROR 0x10
70 1.1 igy #define I28F128_S_LOW_VOLTAGE 0x08
71 1.1 igy #define I28F128_S_PROG_SUSPEND 0x04
72 1.1 igy #define I28F128_S_BLOCK_LOCKED 0x02
73 1.1 igy
74 1.1 igy #define I28F128_XS_BUF_AVAIL 0x80
75 1.1 igy
76 1.1 igy #define I28F128_BUFFER_SIZE 0x20
77 1.1 igy
78 1.1 igy #define I28F128_BLOCK_ERASE_TIME 1000000 /* usec */
79 1.1 igy #define I28F128_WRITE_BUFFER_TIMEOUT 800 /* usec */
80 1.1 igy #define I28F128_WRITE_WORD_TIMEOUT 800 /* usec */
81 1.1 igy
82 1.1 igy
83 1.1 igy #define MBM29LV160_MANUFACT 0x04
84 1.1 igy #define MBM29LV160TE_DEVCODE 0x22c4
85 1.1 igy #define MBM29LV160BE_DEVCODE 0x2249
86 1.1 igy
87 1.1 igy #define MBM29LV160_SUBSECT_MASK 0x000f8000
88 1.1 igy #define MBM29LV160TE_SUBSECT_ADDR 0x000f8000
89 1.1 igy #define MBM29LV160BE_SUBSECT_ADDR 0x00000000
90 1.1 igy
91 1.1 igy #define MBM29LV160_COMM_ADDR0 (0x555 << 1)
92 1.1 igy #define MBM29LV160_COMM_ADDR1 (0x2aa << 1)
93 1.1 igy #define MBM29LV160_COMM_ADDR2 (0x555 << 1)
94 1.1 igy #define MBM29LV160_COMM_ADDR3 (0x555 << 1)
95 1.1 igy #define MBM29LV160_COMM_ADDR4 (0x2aa << 1)
96 1.1 igy #define MBM29LV160_COMM_ADDR5 (0x555 << 1)
97 1.1 igy
98 1.1 igy #define MBM29LV160_COMM_CMD0 0xaa
99 1.1 igy #define MBM29LV160_COMM_CMD1 0x55
100 1.1 igy
101 1.1 igy #define MBM29LV160_SIGN_CMD2 0x90
102 1.1 igy #define MBM29LV160_PROG_CMD2 0xa0
103 1.1 igy #define MBM29LV160_ESECT_CMD2 0x80
104 1.1 igy #define MBM29LV160_ESECT_CMD3 0xaa
105 1.1 igy #define MBM29LV160_ESECT_CMD4 0x55
106 1.1 igy #define MBM29LV160_ESECT_CMD5 0x30
107 1.1 igy
108 1.1 igy #define MBM29LV160_DEVCODE_REG 0x02
109 1.1 igy
110 1.1 igy #define MBM29LV160_SECT_SIZE 0x00010000
111 1.1 igy #define MBM29LV160_SUBSECT_SIZE 0x00002000
112