icureg.h revision 1.4
1 /* $NetBSD: icureg.h,v 1.4 2001/04/18 11:07:27 sato Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 Shin Takemura. All rights reserved. 5 * Copyright (c) 1999-2001 SATO Kazumi. All rights reserved. 6 * Copyright (c) 1999 PocketBSD Project. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the PocketBSD project 19 * and its contributors. 20 * 4. Neither the name of the project nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 */ 37 38 /* 39 * ICU (Interrupt Control UNIT) Registers definitions 40 * start 0x0B000080 (vr4102/4111/4121) 41 * start 0x0F000080 (vr4122) 42 */ 43 #include "opt_vr41xx.h" 44 #include <hpcmips/vr/vrcpudef.h> 45 46 #if !defined SINGLE_VRIP_BASE 47 #error currently missconfiguraton. 48 #endif 49 50 #define NO_REG_W 0 /* no register */ 51 52 #define SYSINT1_REG_W 0x000 /* Level1 System intr reg 1 */ 53 #define MSYSINT1_REG_W 0x00c /* Level1 Mask System intr reg 1 */ 54 55 #define SYSINT1_INT15 (1<<15) 56 #define SYSINT1_INT14 (1<<14) 57 #define SYSINT1_INT13 (1<<13) 58 #define SYSINT1_DOZEPIU (1<<13) /* PIU intr during Suspend */ 59 #define SYSINT1_INT12 (1<<12) 60 #define SYSINT1_CLKRUN (1<<12) /* CLKRUN intr (=vr4122) */ 61 #define SYSINT1_INT11 (1<<11) 62 #define SYSINT1_SOFT (1<<11) /* Software intr */ 63 #define SYSINT1_INT10 (1<<10) 64 #define SYSINT1_WRBERR (1<<10) /* Bus error intr (4102 <=,<= 4121)*/ 65 #define SYSINT1_INT9 (1<<9) 66 #define SYSINT1_SIU (1<<9) /* SIU intr */ 67 #define SYSINT1_INT8 (1<<8) 68 #define SYSINT1_GIU (1<<8) /* GIU intr */ 69 #define SYSINT1_INT7 (1<<7) 70 #define SYSINT1_KIU (1<<7) /* KIU intr (4102 <=,<= 4121)*/ 71 #define SYSINT1_INT6 (1<<6) 72 #define SYSINT1_AIU (1<<6) /* AIU intr (4102 <=,<= 4121)*/ 73 #define SYSINT1_INT5 (1<<5) 74 #define SYSINT1_PIU (1<<5) /* PIU intr (4102 <=,<= 4121)*/ 75 #define SYSINT1_INT4 (1<<4) 76 #define SYSINT1_INT3 (1<<3) 77 #define SYSINT1_ETIMER (1<<3) /* ETIMER intr */ 78 #define SYSINT1_INT2 (1<<2) 79 #define SYSINT1_RTCL1 (1<<2) /* RTClong1 intr */ 80 #define SYSINT1_INT1 (1<<1) 81 #define SYSINT1_POWER (1<<1) /* PowerSW intr */ 82 #define SYSINT1_INT0 (1<<0) 83 #define SYSINT1_BAT (1<<0) /* Battery intr */ 84 85 86 #define ICUPIUINT_REG_W 0x002 /* Level2 PIU intr reg */ 87 #define MPIUINT_REG_W 0x00e /* Level2 Mask PIU intr reg */ 88 89 #define PIUINT_PADCMD (1<<6) /* PIU command scan intr */ 90 #define PIUINT_PADADP (1<<5) /* PIU AD port scan intr */ 91 #define PIUINT_PADPAGE1 (1<<4) /* PIU data page 1 intr */ 92 #define PIUINT_PADPAGE0 (1<<3) /* PIU data page 0 intr */ 93 #define PIUINT_PADLOST (1<<2) /* A/D data timeout intr */ 94 #define PIUINT_PENCHG (1) /* Touch Panel contact intr */ 95 96 #define VR4102_AIUINT_REG_W 0x004 /* Level2 AIU intr reg */ 97 #define VR4102_MAIUINT_REG_W 0x010 /* Level2 Mask AIU intr reg */ 98 #define VR4122_AIUINT_REG_W NO_REG_W /* Level2 AIU intr reg */ 99 #define VR4122_MAIUINT_REG_W NO_REG_W /* Level2 Mask AIU intr reg */ 100 #if defined SINGLE_VRIP_BASE 101 #if defined VRGROUP_4102_4121 102 #define AIUINT_REG_W VR4102_AIUINT_REG_W 103 #define MAIUINT_REG_W VR4102_MAIUINT_REG_W 104 #endif /* VRGROUP_4102_4121 */ 105 #if defined VRGROUP_4122 106 #define AIUINT_REG_W VR4122_AIUINT_REG_W 107 #define MAIUINT_REG_W VR4122_MAIUINT_REG_W 108 #endif /* VRGROUP_4122 */ 109 #endif 110 111 #define AIUINT_INTMEND (1<<11) /* Audio input DMA buffer 2 page */ 112 #define AIUINT_INTM (1<<10) /* Audio input DMA buffer 1 page */ 113 #define AIUINT_INTMIDLE (1<<9) /* Audio input idle intr */ 114 #define AIUINT_INTMST (1<<8) /* Audio input receive completion intr */ 115 #define AIUINT_INTSEND (1<<3) /* Audio output buffer 2 page */ 116 #define AIUINT_INTS (1<<2) /* Audio output buffer 1 page */ 117 #define AIUINT_INTSIDLE (1<<1) /* Audio output idle intr */ 118 119 120 #define VR4102_KIUINT_REG_W 0x006 /* Level2 KIU intr reg */ 121 #define VR4102_MKIUINT_REG_W 0x012 /* Level2 Mask KIU intr reg */ 122 #define VR4122_KIUINT_REG_W NO_REG_W /* Level2 KIU intr reg */ 123 #define VR4122_MKIUINT_REG_W NO_REG_W /* Level2 Mask KIU intr reg */ 124 #if defined SINGLE_VRIP_BASE 125 #if defined VRGROUP_4102_4121 126 #define KIUINT_REG_W VR4102_KIUINT_REG_W 127 #define MKIUINT_REG_W VR4102_MKIUINT_REG_W 128 #endif /* VRGROUP_4102_4121 */ 129 #if defined VRGROUP_4122 130 #define KIUINT_REG_W VR4122_KIUINT_REG_W 131 #define MKIUINT_REG_W VR4122_MKIUINT_REG_W 132 #endif /* VRGROUP_4122 */ 133 #endif 134 135 #define KIUINT_KDATLOST (1<<2) /* Key scan data lost */ 136 #define KIUINT_KDATRDY (1<<1) /* Key scan data complete */ 137 #define KIUINT_SCANINT (1) /* Key input detect intr */ 138 139 140 #define GIUINT_L_REG_W 0x008 /* Level2 GIU intr reg Low */ 141 #define MGIUINT_L_REG_W 0x014 /* Level2 Mask GIU intr reg Low */ 142 143 #define GIUINT_GPIO15 (1<<15) /* GPIO 15 */ 144 #define GIUINT_GPIO14 (1<<14) /* GPIO 14 */ 145 #define GIUINT_GPIO13 (1<<13) /* GPIO 13 */ 146 #define GIUINT_GPIO12 (1<<12) /* GPIO 12 */ 147 #define GIUINT_GPIO11 (1<<11) /* GPIO 11 */ 148 #define GIUINT_GPIO10 (1<<10) /* GPIO 10 */ 149 #define GIUINT_GPIO9 (1<<9) /* GPIO 9 */ 150 #define GIUINT_GPIO8 (1<<8) /* GPIO 8 */ 151 #define GIUINT_GPIO7 (1<<7) /* GPIO 7 */ 152 #define GIUINT_GPIO6 (1<<6) /* GPIO 6 */ 153 #define GIUINT_GPIO5 (1<<5) /* GPIO 5 */ 154 #define GIUINT_GPIO4 (1<<4) /* GPIO 4 */ 155 #define GIUINT_GPIO3 (1<<3) /* GPIO 3 */ 156 #define GIUINT_GPIO2 (1<<2) /* GPIO 2 */ 157 #define GIUINT_GPIO1 (1<<1) /* GPIO 1 */ 158 #define GIUINT_GPIO0 (1) /* GPIO 0 */ 159 160 161 #define DSIUINT_REG_W 0x00a /* Level2 DSIU intr reg */ 162 #define MDSIUINT_REG_W 0x016 /* Level2 Mask DSIU intr reg */ 163 164 #define DSIUINT_DCTS (1<<11) /* DCTS# change */ 165 #define DSIUINT_SER0 (1<<10) /* Debug serial receive error */ 166 #define DSIUINT_SR0 (1<<9) /* Debug serial receive */ 167 #define DSIUINT_ST0 (1<<8) /* Debug serial transmit */ 168 169 #define NMI_REG_W 0x018 /* NMI reg */ 170 171 #define LOWBATT_NMIORINT (1) /* Low battery type */ 172 #define LOWBATT_INT0 (1) /* Low battery int 0 */ 173 #define LOWBATT_NMI (0) /* Low battery NMI */ 174 175 176 #define SOFTINT_REG_W 0x01a /* Software intr reg */ 177 178 #define SOFTINT_MASK3 (1<<3) /* Softint3 mask */ 179 #define SOFTINT_SET3 (1<<3) /* Softint3 set */ 180 #define SOFTINT_CLEAR3 (0<<3) /* Softint3 clear */ 181 182 #define SOFTINT_MASK2 (1<<2) /* Softint2 mask */ 183 #define SOFTINT_SET2 (1<<2) /* Softint2 set */ 184 #define SOFTINT_CLEAR2 (0<<2) /* Softint2 clear */ 185 186 #define SOFTINT_MASK1 (1<<1) /* Softint1 mask */ 187 #define SOFTINT_SET1 (1<<1) /* Softint1 set */ 188 #define SOFTINT_CLEAR1 (0<<1) /* Softint1 clear */ 189 190 #define SOFTINT_MASK0 (1) /* Softint0 mask */ 191 #define SOFTINT_SET0 (1) /* Softint0 set */ 192 #define SOFTINT_CLEAR0 (0) /* Softint0 clear */ 193 194 195 #define VR4102_SYSINT2_REG_W 0x180 /* Level1 System intr reg 2 */ 196 #define VR4102_MSYSINT2_REG_W 0x186 /* Level1 Mask System intr reg 2 */ 197 #define VR4122_SYSINT2_REG_W 0x020 /* Level1 System intr reg 2 */ 198 #define VR4122_MSYSINT2_REG_W 0x026 /* Level1 Mask System intr reg 2 */ 199 #if defined SINGLE_VRIP_BASE 200 #if defined VRGROUP_4102_4121 201 #define SYSINT2_REG_W VR4102_SYSINT2_REG_W 202 #define MSYSINT2_REG_W VR4102_MSYSINT2_REG_W 203 #endif /* VRGROUP_4102_4121 */ 204 #if defined VRGROUP_4122 205 #define SYSINT2_REG_W VR4122_SYSINT2_REG_W 206 #define MSYSINT2_REG_W VR4122_MSYSINT2_REG_W 207 #endif /* VRGROUP_4122 */ 208 #endif 209 210 #define SYSINT2_INT31 (1<<15) 211 #define SYSINT2_INT30 (1<<14) 212 #define SYSINT2_INT29 (1<<13) 213 #define SYSINT2_INT28 (1<<12) 214 #define SYSINT2_INT27 (1<<11) 215 #define SYSINT2_INT26 (1<<10) 216 #define SYSINT2_INT25 (1<<9) 217 #define SYSINT2_BCU (1<<9) /* BCU intr (=vr4122) */ 218 #define SYSINT2_INT24 (1<<8) 219 #define SYSINT2_CSI (1<<8) /* CSI intr (=vr4122) */ 220 #define SYSINT2_INT23 (1<<7) 221 #define SYSINT2_SCU (1<<7) /* SCU intr (=vr4122) */ 222 #define SYSINT2_INT22 (1<<6) 223 #define SYSINT2_PCI (1<<6) /* PCI intr (=vr4122) */ 224 #define SYSINT2_DSIU (1<<5) /* DSUI intr */ 225 #define SYSINT2_FIR (1<<4) /* FIR intr */ 226 #define SYSINT2_TCLK (1<<3) /* TClock Counter intr */ 227 #define SYSINT2_HSP (1<<2) /* HSP intr (4122>=4102)*/ 228 #define SYSINT2_LED (1<<1) /* LED intr */ 229 #define SYSINT2_RTCL2 (1<<0) /* RTCLong2 intr */ 230 231 232 #define VR4102_GIUINT_H_REG_W 0x182 /* Level2 GIU intr reg High */ 233 #define VR4102_MGIUINT_H_REG_W 0x188 /* Level2 Mask GIU intr reg High */ 234 #define VR4122_GIUINT_H_REG_W 0x022 /* Level2 GIU intr reg High */ 235 #define VR4122_MGIUINT_H_REG_W 0x028 /* Level2 Mask GIU intr reg High */ 236 #if defined SINGLE_VRIP_BASE 237 #if defined VRGROUP_4102_4121 238 #define GIUINT_H_REG_W VR4102_GIUINT_H_REG_W 239 #define MGIUINT_H_REG_W VR4102_MGIUINT_H_REG_W 240 #endif /* VRGROUP_4102_4121 */ 241 #if defined VRGROUP_4122 242 #define GIUINT_H_REG_W VR4122_GIUINT_H_REG_W 243 #define MGIUINT_H_REG_W VR4122_MGIUINT_H_REG_W 244 #endif /* VRGROUP_4122 */ 245 #endif 246 247 #define GIUINT_GPIO31 (1<<15) /* GPIO 31 */ 248 #define GIUINT_GPIO30 (1<<14) /* GPIO 30 */ 249 #define GIUINT_GPIO29 (1<<13) /* GPIO 29 */ 250 #define GIUINT_GPIO28 (1<<12) /* GPIO 28 */ 251 #define GIUINT_GPIO27 (1<<11) /* GPIO 27 */ 252 #define GIUINT_GPIO26 (1<<10) /* GPIO 26 */ 253 #define GIUINT_GPIO25 (1<<9) /* GPIO 25 */ 254 #define GIUINT_GPIO24 (1<<8) /* GPIO 24 */ 255 #define GIUINT_GPIO23 (1<<7) /* GPIO 23 */ 256 #define GIUINT_GPIO22 (1<<6) /* GPIO 22 */ 257 #define GIUINT_GPIO21 (1<<5) /* GPIO 21 */ 258 #define GIUINT_GPIO20 (1<<4) /* GPIO 20 */ 259 #define GIUINT_GPIO19 (1<<3) /* GPIO 19 */ 260 #define GIUINT_GPIO18 (1<<2) /* GPIO 18 */ 261 #define GIUINT_GPIO17 (1<<1) /* GPIO 17 */ 262 #define GIUINT_GPIO16 (1) /* GPIO 16 */ 263 264 265 #define VR4102_FIRINT_REG_W 0x184 /* Level2 FIR intr reg */ 266 #define VR4102_MFIRINT_REG_W 0x18a /* Level2 Mask FIR intr reg */ 267 #define VR4122_FIRINT_REG_W 0x024 /* Level2 FIR intr reg */ 268 #define VR4122_MFIRINT_REG_W 0x02a /* Level2 Mask FIR intr reg */ 269 #if defined SINGLE_VRIP_BASE 270 #if defined VRGROUP_4102_4121 271 #define FIRINT_REG_W VR4102_FIRINT_REG_W 272 #define MFIRINT_REG_W VR4102_MFIRINT_REG_W 273 #endif /* VRGROUP_4102_4121 */ 274 #if defined VRGROUP_4122 275 #define FIRINT_REG_W VR4122_FIRINT_REG_W 276 #define MFIRINT_REG_W VR4122_MFIRINT_REG_W 277 #endif /* VRGROUP_4122 */ 278 #endif 279 280 #define FIRINT_FIR (1<<4) /* FIR intr */ 281 #define FIRINT_RECV2 (1<<3) /* FIR DMA buf recv buffer2 */ 282 #define FIRINT_TRNS2 (1<<2) /* FIR DMA buf transmit buffer2 */ 283 #define FIRINT_RECV1 (1<<1) /* FIR DMA buf recv buffer1 */ 284 #define FIRINT_TRNS1 (1) /* FIR DMA buf transmit buffer1 */ 285 286 #define VR4102_PCIINT_REG_W NO_REG_W /* Level2 PCI intr reg */ 287 #define VR4102_MPCIINT_REG_W NO_REG_W /* Level2 PCI intr mask */ 288 #define VR4122_PCIINT_REG_W 0x2c /* Level2 PCI intr reg */ 289 #define VR4122_MPCIINT_REG_W 0x32 /* Level2 PCI intr mask */ 290 #if defined SINGLE_VRIP_BASE 291 #if defined VRGROUP_4102_4121 292 #define PCIINT_REG_W VR4102_PCIINT_REG_W 293 #define MPCIINT_REG_W VR4102_MPCIINT_REG_W 294 #endif /* VRGROUP_4102_4121 */ 295 #if defined VRGROUP_4122 296 #define PCIINT_REG_W VR4122_PCIINT_REG_W 297 #define MPCIINT_REG_W VR4122_MPCIINT_REG_W 298 #endif /* VRGROUP_4122 */ 299 #endif 300 301 #define PCIINT_INT0 (1) /* PCI INT 0 */ 302 303 #define VR4102_SCUINT_REG_W NO_REG_W /* Level2 SCU intr reg */ 304 #define VR4102_MSCUINT_REG_W NO_REG_W /* Level2 SCU intr mask */ 305 #define VR4122_SCUINT_REG_W 0x2e /* Level2 SCU intr reg */ 306 #define VR4122_MSCUINT_REG_W 0x34 /* Level2 SCU intr mask */ 307 #if defined SINGLE_VRIP_BASE 308 #if defined VRGROUP_4102_4121 309 #define SCUINT_REG_W VR4102_SCUINT_REG_W 310 #define MSCUINT_REG_W VR4102_MSCUINT_REG_W 311 #endif /* VRGROUP_4102_4121 */ 312 #if defined VRGROUP_4122 313 #define SCUINT_REG_W VR4122_SCUINT_REG_W 314 #define MSCUINT_REG_W VR4122_MSCUINT_REG_W 315 #endif /* VRGROUP_4122 */ 316 #endif 317 318 #define SCUINT_INT0 (1) /* SCU INT 0 */ 319 320 #define VR4102_CSIINT_REG_W NO_REG_W /* Level2 CSI intr reg */ 321 #define VR4102_MCSIINT_REG_W NO_REG_W /* Level2 CSI intr mask */ 322 #define VR4122_CSIINT_REG_W 0x30 /* Level2 CSI intr reg */ 323 #define VR4122_MCSIINT_REG_W 0x36 /* Level2 CSI intr mask */ 324 #if defined SINGLE_VRIP_BASE 325 #if defined VRGROUP_4102_4121 326 #define CSIINT_REG_W VR4102_CSIINT_REG_W 327 #define MCSIINT_REG_W VR4102_MCSIINT_REG_W 328 #endif /* VRGROUP_4102_4121 */ 329 #if defined VRGROUP_4122 330 #define CSIINT_REG_W VR4122_CSIINT_REG_W 331 #define MCSIINT_REG_W VR4122_MCSIINT_REG_W 332 #endif /* VRGROUP_4122 */ 333 #endif 334 335 #define CSIINT_TRPAGE2 (1<<6) /* DMA send page 2 intr */ 336 #define CSIINT_TRPAGE1 (1<<5) /* DMA send page 1 intr */ 337 #define CSIINT_TREND (1<<4) /* send every data intr */ 338 #define CSIINT_TREMPTY (1<<3) /* send FIFO empty intr */ 339 #define CSIINT_RCPAGE2 (1<<2) /* DMA recv page 2 intr */ 340 #define CSIINT_RCPAGE1 (1<<1) /* DMA recv page 1 intr */ 341 #define CSIINT_RCOVER (1) /* recv FIFO overrun intr */ 342 343 #define VR4102_BCUINT_REG_W NO_REG_W /* Level2 BCU intr reg */ 344 #define VR4102_MBCUINT_REG_W NO_REG_W /* Level2 BCU intr mask */ 345 #define VR4122_BCUINT_REG_W 0x38 /* Level2 BCU intr reg */ 346 #define VR4122_MBCUINT_REG_W 0x3a /* Level2 BCU intr mask */ 347 #if defined SINGLE_VRIP_BASE 348 #if defined VRGROUP_4102_4121 349 #define BCUINT_REG_W VR4102_BCUINT_REG_W 350 #define MBCUINT_REG_W VR4102_MBCUINT_REG_W 351 #endif /* VRGROUP_4102_4121 */ 352 #if defined VRGROUP_4122 353 #define BCUINT_REG_W VR4122_BCUINT_REG_W 354 #define MBCUINT_REG_W VR4122_MBCUINT_REG_W 355 #endif /* VRGROUP_4122 */ 356 #endif 357 358 #define BCUINT_INT (1) /* BCU INT */ 359 360 /* END icureg.h */ 361
Indexes created Tue Sep 30 06:09:59 GMT 2025