icureg.h revision 1.6
1 /* $NetBSD: icureg.h,v 1.6 2002/02/09 14:54:05 sato Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 Shin Takemura. All rights reserved. 5 * Copyright (c) 1999-2001 SATO Kazumi. All rights reserved. 6 * Copyright (c) 1999 PocketBSD Project. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the PocketBSD project 19 * and its contributors. 20 * 4. Neither the name of the project nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 */ 37 38 /* 39 * ICU (Interrupt Control UNIT) Registers definitions 40 * start 0x0B000080 (vr4102/4111/4121) 41 * start 0x0F000080 (vr4122) 42 */ 43 #include "opt_vr41xx.h" 44 #include <hpcmips/vr/vrcpudef.h> 45 46 #if !defined SINGLE_VRIP_BASE 47 #error currently missconfiguraton. 48 #endif 49 50 #define ICU_NO_REG_W 0xffffffff /* no register */ 51 52 53 /* SYSINT1 & MSYSINT1 */ 54 #define SYSINT1_REG_W 0x000 /* Level1 System intr reg 1 */ 55 #define MSYSINT1_REG_W 0x00c /* Level1 Mask System intr reg 1 */ 56 57 #define SYSINT1_INT15 (1<<15) 58 #define SYSINT1_INT14 (1<<14) 59 #define SYSINT1_INT13 (1<<13) 60 #define SYSINT1_DOZEPIU (1<<13) /* PIU intr during Suspend */ 61 #define SYSINT1_INT12 (1<<12) 62 #define SYSINT1_CLKRUN (1<<12) /* CLKRUN intr (=vr4122) */ 63 #define SYSINT1_INT11 (1<<11) 64 #define SYSINT1_SOFT (1<<11) /* Software intr */ 65 #define SYSINT1_INT10 (1<<10) 66 #define SYSINT1_WRBERR (1<<10) /* Bus error intr (4102 <=,<= 4121)*/ 67 #define SYSINT1_INT9 (1<<9) 68 #define SYSINT1_SIU (1<<9) /* SIU intr */ 69 #define SYSINT1_INT8 (1<<8) 70 #define SYSINT1_GIU (1<<8) /* GIU intr */ 71 #define SYSINT1_INT7 (1<<7) 72 #define SYSINT1_KIU (1<<7) /* KIU intr (4102 <=,<= 4121)*/ 73 #define SYSINT1_INT6 (1<<6) 74 #define SYSINT1_AIU (1<<6) /* AIU intr (4102 <=,<= 4121)*/ 75 #define SYSINT1_INT5 (1<<5) 76 #define SYSINT1_PIU (1<<5) /* PIU intr (4102 <=,<= 4121)*/ 77 #define SYSINT1_INT4 (1<<4) 78 #define SYSINT1_INT3 (1<<3) 79 #define SYSINT1_ETIMER (1<<3) /* ETIMER intr */ 80 #define SYSINT1_INT2 (1<<2) 81 #define SYSINT1_RTCL1 (1<<2) /* RTClong1 intr */ 82 #define SYSINT1_INT1 (1<<1) 83 #define SYSINT1_POWER (1<<1) /* PowerSW intr */ 84 #define SYSINT1_INT0 (1<<0) 85 #define SYSINT1_BAT (1<<0) /* Battery intr */ 86 87 88 /* PIUINT & MPIUINT */ 89 #define ICUPIUINT_REG_W 0x002 /* Level2 PIU intr reg */ 90 #define MPIUINT_REG_W 0x00e /* Level2 Mask PIU intr reg */ 91 92 #define PIUINT_PADCMD (1<<6) /* PIU command scan intr */ 93 #define PIUINT_PADADP (1<<5) /* PIU AD port scan intr */ 94 #define PIUINT_PADPAGE1 (1<<4) /* PIU data page 1 intr */ 95 #define PIUINT_PADPAGE0 (1<<3) /* PIU data page 0 intr */ 96 #define PIUINT_PADLOST (1<<2) /* A/D data timeout intr */ 97 #define PIUINT_PENCHG (1) /* Touch Panel contact intr */ 98 99 100 /* AIUINT & MAIUINT */ 101 #define VR4102_AIUINT_REG_W 0x004 /* Level2 AIU intr reg */ 102 #define VR4102_MAIUINT_REG_W 0x010 /* Level2 Mask AIU intr reg */ 103 #define VR4122_AIUINT_REG_W ICU_NO_REG_W /* Level2 AIU intr reg */ 104 #define VR4122_MAIUINT_REG_W ICU_NO_REG_W /* Level2 Mask AIU intr reg */ 105 #define VR4181_AIUINT_REG_W 0x004 /* Level2 AIU intr reg */ 106 #define VR4181_MAIUINT_REG_W 0x010 /* Level2 Mask AIU intr reg */ 107 #if defined SINGLE_VRIP_BASE 108 #if defined VRGROUP_4102_4121 109 #define AIUINT_REG_W VR4102_AIUINT_REG_W 110 #define MAIUINT_REG_W VR4102_MAIUINT_REG_W 111 #endif /* VRGROUP_4102_4121 */ 112 #if defined VRGROUP_4122_4131 113 #define AIUINT_REG_W VR4122_AIUINT_REG_W 114 #define MAIUINT_REG_W VR4122_MAIUINT_REG_W 115 #endif /* VRGROUP_4122_4131 */ 116 #if defined VRGROUP_4181 117 #define AIUINT_REG_W VR4181_AIUINT_REG_W 118 #define MAIUINT_REG_W VR4181_MAIUINT_REG_W 119 #endif /* VRGROUP_4181 */ 120 #endif 121 122 #define AIUINT_INTMEND (1<<11) /* Audio input DMA buffer 2 page */ 123 #define AIUINT_INTM (1<<10) /* Audio input DMA buffer 1 page */ 124 #define AIUINT_INTMIDLE (1<<9) /* Audio input idle intr */ 125 #define AIUINT_INTMST (1<<8) /* Audio input receive completion intr */ 126 #define AIUINT_INTSEND (1<<3) /* Audio output buffer 2 page */ 127 #define AIUINT_INTS (1<<2) /* Audio output buffer 1 page */ 128 #define AIUINT_INTSIDLE (1<<1) /* Audio output idle intr */ 129 130 131 /* KIUINT & MKIUINT */ 132 #define VR4102_KIUINT_REG_W 0x006 /* Level2 KIU intr reg */ 133 #define VR4102_MKIUINT_REG_W 0x012 /* Level2 Mask KIU intr reg */ 134 #define VR4122_KIUINT_REG_W ICU_NO_REG_W /* Level2 KIU intr reg */ 135 #define VR4122_MKIUINT_REG_W ICU_NO_REG_W /* Level2 Mask KIU intr reg */ 136 #define VR4181_KIUINT_REG_W 0x118 /* Level2 KIU intr reg */ 137 #define VR4181_MKIUINT_REG_W 0x012 /* Level2 Mask KIU intr reg */ 138 #if defined SINGLE_VRIP_BASE 139 #if defined VRGROUP_4102_4121 140 #define KIUINT_REG_W VR4102_KIUINT_REG_W 141 #define MKIUINT_REG_W VR4102_MKIUINT_REG_W 142 #endif /* VRGROUP_4102_4121 */ 143 #if defined VRGROUP_4122_4131 144 #define KIUINT_REG_W VR4122_KIUINT_REG_W 145 #define MKIUINT_REG_W VR4122_MKIUINT_REG_W 146 #endif /* VRGROUP_4122_4131 */ 147 #if defined VRGROUP_4181 148 #define KIUINT_REG_W VR4181_KIUINT_REG_W 149 #define MKIUINT_REG_W VR4181_MKIUINT_REG_W 150 #endif /* VRGROUP_4181 */ 151 #endif 152 153 #define KIUINT_KDATLOST (1<<2) /* Key scan data lost */ 154 #define KIUINT_KDATRDY (1<<1) /* Key scan data complete */ 155 #define KIUINT_SCANINT (1) /* Key input detect intr */ 156 157 158 /* GIUINTL & MGIUINTL */ 159 #define VR4102_GIUINT_L_REG_W 0x008 /* Level2 GIU intr reg Low */ 160 #define VR4102_MGIUINT_L_REG_W 0x014 /* Level2 Mask GIU intr reg Low */ 161 #define VR4122_GIUINT_L_REG_W 0x008 /* Level2 GIU intr reg Low */ 162 #define VR4122_MGIUINT_L_REG_W 0x014 /* Level2 Mask GIU intr reg Low */ 163 #define VR4181_GIUINT_L_REG_W ICU_NO_REG_W /* Level2 GIU intr reg Low */ 164 #define VR4181_MGIUINT_L_REG_W ICU_NO_REG_W /* Level2 Mask GIU intr reg Low */ 165 #if defined SINGLE_VRIP_BASE 166 #if defined VRGROUP_4102_4121 167 #define GIUINT_L_REG_W VR4102_GIUINT_L_REG_W 168 #define MGIUINT_L_REG_W VR4102_MGIUINT_L_REG_W 169 #endif /* VRGROUP_4102_4121 */ 170 #if defined VRGROUP_4122_4131 171 #define GIUINT_L_REG_W VR4122_GIUINT_L_REG_W 172 #define MGIUINT_L_REG_W VR4122_MGIUINT_L_REG_W 173 #endif /* VRGROUP_4122_4131 */ 174 #if defined VRGROUP_4181 175 #define GIUINT_L_REG_W VR4181_GIUINT_L_REG_W 176 #define MGIUINT_L_REG_W VR4181_MGIUINT_L_REG_W 177 #endif /* VRGROUP_4181 */ 178 #endif 179 180 #define GIUINT_GPIO15 (1<<15) /* GPIO 15 */ 181 #define GIUINT_GPIO14 (1<<14) /* GPIO 14 */ 182 #define GIUINT_GPIO13 (1<<13) /* GPIO 13 */ 183 #define GIUINT_GPIO12 (1<<12) /* GPIO 12 */ 184 #define GIUINT_GPIO11 (1<<11) /* GPIO 11 */ 185 #define GIUINT_GPIO10 (1<<10) /* GPIO 10 */ 186 #define GIUINT_GPIO9 (1<<9) /* GPIO 9 */ 187 #define GIUINT_GPIO8 (1<<8) /* GPIO 8 */ 188 #define GIUINT_GPIO7 (1<<7) /* GPIO 7 */ 189 #define GIUINT_GPIO6 (1<<6) /* GPIO 6 */ 190 #define GIUINT_GPIO5 (1<<5) /* GPIO 5 */ 191 #define GIUINT_GPIO4 (1<<4) /* GPIO 4 */ 192 #define GIUINT_GPIO3 (1<<3) /* GPIO 3 */ 193 #define GIUINT_GPIO2 (1<<2) /* GPIO 2 */ 194 #define GIUINT_GPIO1 (1<<1) /* GPIO 1 */ 195 #define GIUINT_GPIO0 (1) /* GPIO 0 */ 196 197 198 /* DSIUINT & MDSIUINT */ 199 #define VR4102_DSIUINT_REG_W 0x00a /* Level2 DSIU intr reg */ 200 #define VR4102_MDSIUINT_REG_W 0x016 /* Level2 Mask DSIU intr reg */ 201 #define VR4122_DSIUINT_REG_W 0x00a /* Level2 DSIU intr reg */ 202 #define VR4122_MDSIUINT_REG_W 0x016 /* Level2 Mask DSIU intr reg */ 203 #define VR4181_DSIUINT_REG_W ICU_NO_REG_W /* Level2 DSIU intr reg */ 204 #define VR4181_MDSIUINT_REG_W ICU_NO_REG_W /* Level2 Mask DSIU intr reg */ 205 #if defined SINGLE_VRIP_BASE 206 #if defined VRGROUP_4102_4121 207 #define DSIUINT_REG_W VR4102_DSIUINT_REG_W 208 #define MDSIUINT_REG_W VR4102_MDSIUINT_REG_W 209 #endif /* VRGROUP_4102_4121 */ 210 #if defined VRGROUP_4122_4131 211 #define DSIUINT_REG_W VR4122_DSIUINT_REG_W 212 #define MDSIUINT_REG_W VR4122_MDSIUINT_REG_W 213 #endif /* VRGROUP_4122_4131 */ 214 #if defined VRGROUP_4181 215 #define DSIUINT_REG_W VR4181_DSIUINT_REG_W 216 #define MDSIUINT_REG_W VR4181_MDSIUINT_REG_W 217 #endif /* VRGROUP_4181 */ 218 #endif 219 220 #define DSIUINT_DCTS (1<<11) /* DCTS# change */ 221 #define DSIUINT_SER0 (1<<10) /* Debug serial receive error */ 222 #define DSIUINT_SR0 (1<<9) /* Debug serial receive */ 223 #define DSIUINT_ST0 (1<<8) /* Debug serial transmit */ 224 225 226 /* NMI */ 227 #define NMI_REG_W 0x018 /* NMI reg */ 228 229 #define LOWBATT_NMIORINT (1) /* Low battery type */ 230 #define LOWBATT_INT0 (1) /* Low battery int 0 */ 231 #define LOWBATT_NMI (0) /* Low battery NMI */ 232 233 234 /* SOFTINT */ 235 #define SOFTINT_REG_W 0x01a /* Software intr reg */ 236 237 #define SOFTINT_MASK3 (1<<3) /* Softint3 mask */ 238 #define SOFTINT_SET3 (1<<3) /* Softint3 set */ 239 #define SOFTINT_CLEAR3 (0<<3) /* Softint3 clear */ 240 241 #define SOFTINT_MASK2 (1<<2) /* Softint2 mask */ 242 #define SOFTINT_SET2 (1<<2) /* Softint2 set */ 243 #define SOFTINT_CLEAR2 (0<<2) /* Softint2 clear */ 244 245 #define SOFTINT_MASK1 (1<<1) /* Softint1 mask */ 246 #define SOFTINT_SET1 (1<<1) /* Softint1 set */ 247 #define SOFTINT_CLEAR1 (0<<1) /* Softint1 clear */ 248 249 #define SOFTINT_MASK0 (1) /* Softint0 mask */ 250 #define SOFTINT_SET0 (1) /* Softint0 set */ 251 #define SOFTINT_CLEAR0 (0) /* Softint0 clear */ 252 253 254 /* SYSINT2 & MSYSINT2 */ 255 #define VR4102_SYSINT2_REG_W 0x180 /* Level1 System intr reg 2 */ 256 #define VR4102_MSYSINT2_REG_W 0x186 /* Level1 Mask System intr reg 2 */ 257 #define VR4122_SYSINT2_REG_W 0x020 /* Level1 System intr reg 2 */ 258 #define VR4122_MSYSINT2_REG_W 0x026 /* Level1 Mask System intr reg 2 */ 259 #define VR4181_SYSINT2_REG_W 0x180 /* Level1 System intr reg 2 */ 260 #define VR4181_MSYSINT2_REG_W 0x186 /* Level1 Mask System intr reg 2 */ 261 #if defined SINGLE_VRIP_BASE 262 #if defined VRGROUP_4102_4121 263 #define SYSINT2_REG_W VR4102_SYSINT2_REG_W 264 #define MSYSINT2_REG_W VR4102_MSYSINT2_REG_W 265 #endif /* VRGROUP_4102_4121 */ 266 #if defined VRGROUP_4122_4131 267 #define SYSINT2_REG_W VR4122_SYSINT2_REG_W 268 #define MSYSINT2_REG_W VR4122_MSYSINT2_REG_W 269 #endif /* VRGROUP_4122_4131 */ 270 #if defined VRGROUP_4181 271 #define SYSINT2_REG_W VR4181_SYSINT2_REG_W 272 #define MSYSINT2_REG_W VR4181_MSYSINT2_REG_W 273 #endif /* VRGROUP_4181 */ 274 #endif 275 276 #define SYSINT2_INT31 (1<<15) 277 #define SYSINT2_INT30 (1<<14) 278 #define SYSINT2_INT29 (1<<13) 279 #define SYSINT2_INT28 (1<<12) 280 #define SYSINT2_INT27 (1<<11) 281 #define SYSINT2_INT26 (1<<10) 282 #define SYSINT2_INT25 (1<<9) 283 #define SYSINT2_BCU (1<<9) /* BCU intr (=vr4122) */ 284 #define SYSINT2_INT24 (1<<8) 285 #define SYSINT2_CSI (1<<8) /* CSI intr (=vr4122) */ 286 #define SYSINT2_INT23 (1<<7) 287 #define SYSINT2_SCU (1<<7) /* SCU intr (=vr4122) */ 288 #define SYSINT2_INT22 (1<<6) 289 #define SYSINT2_PCI (1<<6) /* PCI intr (=vr4122) */ 290 #define SYSINT2_LCD (1<<6) /* LCD intr (=vr4181) */ 291 #define SYSINT2_DSIU (1<<5) /* DSUI intr */ 292 #define SYSINT2_DCU81 (1<<5) /* DCU intr (=4181) */ 293 #define SYSINT2_FIR (1<<4) /* FIR intr */ 294 #define SYSINT2_TCLK (1<<3) /* TClock Counter intr */ 295 #define SYSINT2_CSI81 (1<<3) /* CSI intr (=4181) */ 296 #define SYSINT2_HSP (1<<2) /* HSP intr (4122>=4102)*/ 297 #define SYSINT2_ECU (1<<2) /* EUC intr (=4181)*/ 298 #define SYSINT2_LED (1<<1) /* LED intr */ 299 #define SYSINT2_RTCL2 (1<<0) /* RTCLong2 intr */ 300 301 302 /* GIUINTH & MGIUINTH */ 303 #define VR4102_GIUINT_H_REG_W 0x182 /* Level2 GIU intr reg High */ 304 #define VR4102_MGIUINT_H_REG_W 0x188 /* Level2 Mask GIU intr reg High */ 305 #define VR4122_GIUINT_H_REG_W 0x022 /* Level2 GIU intr reg High */ 306 #define VR4122_MGIUINT_H_REG_W 0x028 /* Level2 Mask GIU intr reg High */ 307 #define VR4181_GIUINT_H_REG_W ICU_NO_REG_W /* Level2 GIU intr reg High */ 308 #define VR4181_MGIUINT_H_REG_W ICU_NO_REG_W /* Level2 Mask GIU intr reg High */ 309 #if defined SINGLE_VRIP_BASE 310 #if defined VRGROUP_4102_4121 311 #define GIUINT_H_REG_W VR4102_GIUINT_H_REG_W 312 #define MGIUINT_H_REG_W VR4102_MGIUINT_H_REG_W 313 #endif /* VRGROUP_4102_4121 */ 314 #if defined VRGROUP_4122_4131 315 #define GIUINT_H_REG_W VR4122_GIUINT_H_REG_W 316 #define MGIUINT_H_REG_W VR4122_MGIUINT_H_REG_W 317 #endif /* VRGROUP_4122_4131 */ 318 #if defined VRGROUP_4181 319 #define GIUINT_H_REG_W VR4181_GIUINT_H_REG_W 320 #define MGIUINT_H_REG_W VR4181_MGIUINT_H_REG_W 321 #endif /* VRGROUP_4181 */ 322 #endif 323 324 #define GIUINT_GPIO31 (1<<15) /* GPIO 31 */ 325 #define GIUINT_GPIO30 (1<<14) /* GPIO 30 */ 326 #define GIUINT_GPIO29 (1<<13) /* GPIO 29 */ 327 #define GIUINT_GPIO28 (1<<12) /* GPIO 28 */ 328 #define GIUINT_GPIO27 (1<<11) /* GPIO 27 */ 329 #define GIUINT_GPIO26 (1<<10) /* GPIO 26 */ 330 #define GIUINT_GPIO25 (1<<9) /* GPIO 25 */ 331 #define GIUINT_GPIO24 (1<<8) /* GPIO 24 */ 332 #define GIUINT_GPIO23 (1<<7) /* GPIO 23 */ 333 #define GIUINT_GPIO22 (1<<6) /* GPIO 22 */ 334 #define GIUINT_GPIO21 (1<<5) /* GPIO 21 */ 335 #define GIUINT_GPIO20 (1<<4) /* GPIO 20 */ 336 #define GIUINT_GPIO19 (1<<3) /* GPIO 19 */ 337 #define GIUINT_GPIO18 (1<<2) /* GPIO 18 */ 338 #define GIUINT_GPIO17 (1<<1) /* GPIO 17 */ 339 #define GIUINT_GPIO16 (1) /* GPIO 16 */ 340 341 342 /* FIRINT & MFIRINT */ 343 #define VR4102_FIRINT_REG_W 0x184 /* Level2 FIR intr reg */ 344 #define VR4102_MFIRINT_REG_W 0x18a /* Level2 Mask FIR intr reg */ 345 #define VR4122_FIRINT_REG_W 0x024 /* Level2 FIR intr reg */ 346 #define VR4122_MFIRINT_REG_W 0x02a /* Level2 Mask FIR intr reg */ 347 #define VR4181_FIRINT_REG_W ICU_NO_REG_W /* Level2 FIR intr reg */ 348 #define VR4181_MFIRINT_REG_W ICU_NO_REG_W /* Level2 Mask FIR intr reg */ 349 #if defined SINGLE_VRIP_BASE 350 #if defined VRGROUP_4102_4121 351 #define FIRINT_REG_W VR4102_FIRINT_REG_W 352 #define MFIRINT_REG_W VR4102_MFIRINT_REG_W 353 #endif /* VRGROUP_4102_4121 */ 354 #if defined VRGROUP_4122_4131 355 #define FIRINT_REG_W VR4122_FIRINT_REG_W 356 #define MFIRINT_REG_W VR4122_MFIRINT_REG_W 357 #endif /* VRGROUP_4122_4131 */ 358 #if defined VRGROUP_4181 359 #define FIRINT_REG_W VR4181_FIRINT_REG_W 360 #define MFIRINT_REG_W VR4181_MFIRINT_REG_W 361 #endif /* VRGROUP_4181 */ 362 #endif 363 364 #define FIRINT_FIR (1<<4) /* FIR intr */ 365 #define FIRINT_RECV2 (1<<3) /* FIR DMA buf recv buffer2 */ 366 #define FIRINT_TRNS2 (1<<2) /* FIR DMA buf transmit buffer2 */ 367 #define FIRINT_RECV1 (1<<1) /* FIR DMA buf recv buffer1 */ 368 #define FIRINT_TRNS1 (1) /* FIR DMA buf transmit buffer1 */ 369 370 371 /* PCIINT & MPCIINT */ 372 #define VR4102_PCIINT_REG_W ICU_NO_REG_W /* Level2 PCI intr reg */ 373 #define VR4102_MPCIINT_REG_W ICU_NO_REG_W /* Level2 PCI intr mask */ 374 #define VR4122_PCIINT_REG_W 0x2c /* Level2 PCI intr reg */ 375 #define VR4122_MPCIINT_REG_W 0x32 /* Level2 PCI intr mask */ 376 #define VR4181_PCIINT_REG_W ICU_NO_REG_W /* Level2 PCI intr reg */ 377 #define VR4181_MPCIINT_REG_W ICU_NO_REG_W /* Level2 PCI intr mask */ 378 #if defined SINGLE_VRIP_BASE 379 #if defined VRGROUP_4102_4121 380 #define PCIINT_REG_W VR4102_PCIINT_REG_W 381 #define MPCIINT_REG_W VR4102_MPCIINT_REG_W 382 #endif /* VRGROUP_4102_4121 */ 383 #if defined VRGROUP_4122_4131 384 #define PCIINT_REG_W VR4122_PCIINT_REG_W 385 #define MPCIINT_REG_W VR4122_MPCIINT_REG_W 386 #endif /* VRGROUP_4122_4131 */ 387 #if defined VRGROUP_4181 388 #define PCIINT_REG_W VR4181_PCIINT_REG_W 389 #define MPCIINT_REG_W VR4181_MPCIINT_REG_W 390 #endif /* VRGROUP_4181 */ 391 #endif 392 393 #define PCIINT_INT0 (1) /* PCI INT 0 */ 394 395 396 /* SCUINT & MSCUINT */ 397 #define VR4102_SCUINT_REG_W ICU_NO_REG_W /* Level2 SCU intr reg */ 398 #define VR4102_MSCUINT_REG_W ICU_NO_REG_W /* Level2 SCU intr mask */ 399 #define VR4122_SCUINT_REG_W 0x2e /* Level2 SCU intr reg */ 400 #define VR4122_MSCUINT_REG_W 0x34 /* Level2 SCU intr mask */ 401 #define VR4181_SCUINT_REG_W ICU_NO_REG_W /* Level2 SCU intr reg */ 402 #define VR4181_MSCUINT_REG_W ICU_NO_REG_W /* Level2 SCU intr mask */ 403 #if defined SINGLE_VRIP_BASE 404 #if defined VRGROUP_4102_4121 405 #define SCUINT_REG_W VR4102_SCUINT_REG_W 406 #define MSCUINT_REG_W VR4102_MSCUINT_REG_W 407 #endif /* VRGROUP_4102_4121 */ 408 #if defined VRGROUP_4122_4131 409 #define SCUINT_REG_W VR4122_SCUINT_REG_W 410 #define MSCUINT_REG_W VR4122_MSCUINT_REG_W 411 #endif /* VRGROUP_4122_4131 */ 412 #if defined VRGROUP_4181 413 #define SCUINT_REG_W VR4181_SCUINT_REG_W 414 #define MSCUINT_REG_W VR4181_MSCUINT_REG_W 415 #endif /* VRGROUP_4181 */ 416 #endif 417 418 #define SCUINT_INT0 (1) /* SCU INT 0 */ 419 420 421 /* CSIINT & MCSIINT */ 422 #define VR4102_CSIINT_REG_W ICU_NO_REG_W /* Level2 CSI intr reg */ 423 #define VR4102_MCSIINT_REG_W ICU_NO_REG_W /* Level2 CSI intr mask */ 424 #define VR4122_CSIINT_REG_W 0x30 /* Level2 CSI intr reg */ 425 #define VR4122_MCSIINT_REG_W 0x36 /* Level2 CSI intr mask */ 426 #define VR4181_CSIINT_REG_W ICU_NO_REG_W /* Level2 CSI intr reg */ 427 #define VR4181_MCSIINT_REG_W ICU_NO_REG_W /* Level2 CSI intr mask */ 428 #if defined SINGLE_VRIP_BASE 429 #if defined VRGROUP_4102_4121 430 #define CSIINT_REG_W VR4102_CSIINT_REG_W 431 #define MCSIINT_REG_W VR4102_MCSIINT_REG_W 432 #endif /* VRGROUP_4102_4121 */ 433 #if defined VRGROUP_4122_4131 434 #define CSIINT_REG_W VR4122_CSIINT_REG_W 435 #define MCSIINT_REG_W VR4122_MCSIINT_REG_W 436 #endif /* VRGROUP_4122_4131 */ 437 #if defined VRGROUP_4181 438 #define CSIINT_REG_W VR4181_CSIINT_REG_W 439 #define MCSIINT_REG_W VR4181_MCSIINT_REG_W 440 #endif /* VRGROUP_4181 */ 441 #endif 442 443 #define CSIINT_TRPAGE2 (1<<6) /* DMA send page 2 intr */ 444 #define CSIINT_TRPAGE1 (1<<5) /* DMA send page 1 intr */ 445 #define CSIINT_TREND (1<<4) /* send every data intr */ 446 #define CSIINT_TREMPTY (1<<3) /* send FIFO empty intr */ 447 #define CSIINT_RCPAGE2 (1<<2) /* DMA recv page 2 intr */ 448 #define CSIINT_RCPAGE1 (1<<1) /* DMA recv page 1 intr */ 449 #define CSIINT_RCOVER (1) /* recv FIFO overrun intr */ 450 451 452 /* BCUINT & MBCUINT */ 453 #define VR4102_BCUINT_REG_W ICU_NO_REG_W /* Level2 BCU intr reg */ 454 #define VR4102_MBCUINT_REG_W ICU_NO_REG_W /* Level2 BCU intr mask */ 455 #define VR4122_BCUINT_REG_W 0x38 /* Level2 BCU intr reg */ 456 #define VR4122_MBCUINT_REG_W 0x3a /* Level2 BCU intr mask */ 457 #define VR4181_BCUINT_REG_W ICU_NO_REG_W /* Level2 BCU intr reg */ 458 #define VR4181_MBCUINT_REG_W ICU_NO_REG_W /* Level2 BCU intr mask */ 459 #if defined SINGLE_VRIP_BASE 460 #if defined VRGROUP_4102_4121 461 #define BCUINT_REG_W VR4102_BCUINT_REG_W 462 #define MBCUINT_REG_W VR4102_MBCUINT_REG_W 463 #endif /* VRGROUP_4102_4121 */ 464 #if defined VRGROUP_4122_4131 465 #define BCUINT_REG_W VR4122_BCUINT_REG_W 466 #define MBCUINT_REG_W VR4122_MBCUINT_REG_W 467 #endif /* VRGROUP_4122_4131 */ 468 #if defined VRGROUP_4181 469 #define BCUINT_REG_W VR4181_BCUINT_REG_W 470 #define MBCUINT_REG_W VR4181_MBCUINT_REG_W 471 #endif /* VRGROUP_4181 */ 472 #endif 473 474 #define BCUINT_INT (1) /* BCU INT */ 475 476 /* END icureg.h */ 477
Indexes created Tue Sep 30 11:09:46 GMT 2025