rtc.c revision 1.28
1 /* $NetBSD: rtc.c,v 1.28 2011/03/16 14:23:19 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 Shin Takemura. All rights reserved. 5 * Copyright (c) 1999 SATO Kazumi. All rights reserved. 6 * Copyright (c) 1999 PocketBSD Project. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the PocketBSD project 19 * and its contributors. 20 * 4. Neither the name of the project nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: rtc.c,v 1.28 2011/03/16 14:23:19 tsutsui Exp $"); 40 41 #include "opt_vr41xx.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/timetc.h> 46 #include <sys/device.h> 47 #include <sys/cpu.h> 48 49 #include <machine/sysconf.h> 50 #include <machine/bus.h> 51 52 #include <dev/clock_subr.h> 53 54 #include <hpcmips/vr/vr.h> 55 #include <hpcmips/vr/vrcpudef.h> 56 #include <hpcmips/vr/vripif.h> 57 #include <hpcmips/vr/vripreg.h> 58 #include <hpcmips/vr/rtcreg.h> 59 60 /* 61 * for debugging definitions 62 * VRRTCDEBUG print rtc debugging information 63 */ 64 #ifdef VRRTCDEBUG 65 #ifndef VRRTCDEBUG_CONF 66 #define VRRTCDEBUG_CONF 0 67 #endif 68 int vrrtc_debug = VRRTCDEBUG_CONF; 69 #define DPRINTF(arg) if (vrrtc_debug) printf arg; 70 #define DDUMP_REGS(arg) if (vrrtc_debug) vrrtc_dump_regs(arg); 71 #else /* VRRTCDEBUG */ 72 #define DPRINTF(arg) 73 #define DDUMP_REGS(arg) 74 #endif /* VRRTCDEBUG */ 75 76 struct vrrtc_softc { 77 struct device sc_dev; 78 bus_space_tag_t sc_iot; 79 bus_space_handle_t sc_ioh; 80 void *sc_ih; 81 #ifndef SINGLE_VRIP_BASE 82 int sc_rtcint_reg; 83 int sc_tclk_h_reg, sc_tclk_l_reg; 84 int sc_tclk_cnt_h_reg, sc_tclk_cnt_l_reg; 85 #endif /* SINGLE_VRIP_BASE */ 86 int64_t sc_epoch; 87 struct todr_chip_handle sc_todr; 88 struct timecounter sc_tc; 89 }; 90 91 void vrrtc_init(struct device *); 92 int vrrtc_get(todr_chip_handle_t, struct timeval *); 93 int vrrtc_set(todr_chip_handle_t, struct timeval *); 94 uint32_t vrrtc_get_timecount(struct timecounter *); 95 96 struct platform_clock vr_clock = { 97 #define CLOCK_RATE 128 98 CLOCK_RATE, vrrtc_init, 99 }; 100 101 int vrrtc_match(struct device *, struct cfdata *, void *); 102 void vrrtc_attach(struct device *, struct device *, void *); 103 int vrrtc_intr(void*, u_int32_t, u_int32_t); 104 void vrrtc_dump_regs(struct vrrtc_softc *); 105 106 CFATTACH_DECL(vrrtc, sizeof(struct vrrtc_softc), 107 vrrtc_match, vrrtc_attach, NULL, NULL); 108 109 int 110 vrrtc_match(struct device *parent, struct cfdata *cf, void *aux) 111 { 112 113 return (1); 114 } 115 116 #ifndef SINGLE_VRIP_BASE 117 #define RTCINT_REG_W (sc->sc_rtcint_reg) 118 #define TCLK_H_REG_W (sc->sc_tclk_h_reg) 119 #define TCLK_L_REG_W (sc->sc_tclk_l_reg) 120 #define TCLK_CNT_H_REG_W (sc->sc_tclk_cnt_h_reg) 121 #define TCLK_CNT_L_REG_W (sc->sc_tclk_cnt_l_reg) 122 #endif /* SINGLE_VRIP_BASE */ 123 124 void 125 vrrtc_attach(struct device *parent, struct device *self, void *aux) 126 { 127 struct vrip_attach_args *va = aux; 128 struct vrrtc_softc *sc = (void *)self; 129 int year; 130 131 #ifndef SINGLE_VRIP_BASE 132 if (va->va_addr == VR4102_RTC_ADDR) { 133 sc->sc_rtcint_reg = VR4102_RTCINT_REG_W; 134 sc->sc_tclk_h_reg = VR4102_TCLK_H_REG_W; 135 sc->sc_tclk_l_reg = VR4102_TCLK_L_REG_W; 136 sc->sc_tclk_cnt_h_reg = VR4102_TCLK_CNT_H_REG_W; 137 sc->sc_tclk_cnt_l_reg = VR4102_TCLK_CNT_L_REG_W; 138 } else 139 if (va->va_addr == VR4122_RTC_ADDR) { 140 sc->sc_rtcint_reg = VR4122_RTCINT_REG_W; 141 sc->sc_tclk_h_reg = VR4122_TCLK_H_REG_W; 142 sc->sc_tclk_l_reg = VR4122_TCLK_L_REG_W; 143 sc->sc_tclk_cnt_h_reg = VR4122_TCLK_CNT_H_REG_W; 144 sc->sc_tclk_cnt_l_reg = VR4122_TCLK_CNT_L_REG_W; 145 } else 146 if (va->va_addr == VR4181_RTC_ADDR) { 147 sc->sc_rtcint_reg = VR4181_RTCINT_REG_W; 148 sc->sc_tclk_h_reg = RTC_NO_REG_W; 149 sc->sc_tclk_l_reg = RTC_NO_REG_W; 150 sc->sc_tclk_cnt_h_reg = RTC_NO_REG_W; 151 sc->sc_tclk_cnt_l_reg = RTC_NO_REG_W; 152 } else { 153 panic("%s: unknown base address 0x%lx", 154 sc->sc_dev.dv_xname, va->va_addr); 155 } 156 #endif /* SINGLE_VRIP_BASE */ 157 158 sc->sc_iot = va->va_iot; 159 if (bus_space_map(sc->sc_iot, va->va_addr, va->va_size, 160 0 /* no flags */, &sc->sc_ioh)) { 161 printf("vrrtc_attach: can't map i/o space\n"); 162 return; 163 } 164 /* RTC interrupt handler is directly dispatched from CPU intr */ 165 vr_intr_establish(VR_INTR1, vrrtc_intr, sc); 166 /* But need to set level 1 interrupt mask register, 167 * so regsiter fake interrurpt handler 168 */ 169 if (!(sc->sc_ih = vrip_intr_establish(va->va_vc, va->va_unit, 0, 170 IPL_CLOCK, 0, 0))) { 171 printf (":can't map interrupt.\n"); 172 return; 173 } 174 /* 175 * Rtc is attached to call this routine 176 * before cpu_initclock() calls clock_init(). 177 * So we must disable all interrupt for now. 178 */ 179 /* 180 * Disable all rtc interrupts 181 */ 182 /* Disable Elapse compare intr */ 183 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ECMP_H_REG_W, 0); 184 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ECMP_M_REG_W, 0); 185 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ECMP_L_REG_W, 0); 186 /* Disable RTC Long1 intr */ 187 bus_space_write_2(sc->sc_iot, sc->sc_ioh, RTCL1_H_REG_W, 0); 188 bus_space_write_2(sc->sc_iot, sc->sc_ioh, RTCL1_L_REG_W, 0); 189 /* Disable RTC Long2 intr */ 190 bus_space_write_2(sc->sc_iot, sc->sc_ioh, RTCL2_H_REG_W, 0); 191 bus_space_write_2(sc->sc_iot, sc->sc_ioh, RTCL2_L_REG_W, 0); 192 /* Disable RTC TCLK intr */ 193 if (TCLK_H_REG_W != RTC_NO_REG_W) { 194 bus_space_write_2(sc->sc_iot, sc->sc_ioh, TCLK_H_REG_W, 0); 195 bus_space_write_2(sc->sc_iot, sc->sc_ioh, TCLK_L_REG_W, 0); 196 } 197 /* 198 * Clear all rtc intrrupts. 199 */ 200 bus_space_write_2(sc->sc_iot, sc->sc_ioh, RTCINT_REG_W, RTCINT_ALL); 201 202 /* 203 * Figure out the epoch, which could be either forward or 204 * backwards in time. We assume that the start date will always 205 * be on Jan 1. 206 */ 207 for (year = EPOCHYEAR; year < POSIX_BASE_YEAR; year++) { 208 sc->sc_epoch += LEAPYEAR4(year) ? SECYR + SECDAY : SECYR; 209 } 210 for (year = POSIX_BASE_YEAR; year < EPOCHYEAR; year++) { 211 sc->sc_epoch -= LEAPYEAR4(year) ? SECYR + SECDAY : SECYR; 212 } 213 214 /* 215 * Initialize MI todr(9) 216 */ 217 sc->sc_todr.todr_settime = vrrtc_set; 218 sc->sc_todr.todr_gettime = vrrtc_get; 219 sc->sc_todr.cookie = sc; 220 todr_attach(&sc->sc_todr); 221 222 platform_clock_attach(sc, &vr_clock); 223 } 224 225 int 226 vrrtc_intr(void *arg, u_int32_t pc, u_int32_t statusReg) 227 { 228 struct vrrtc_softc *sc = arg; 229 struct clockframe cf; 230 231 bus_space_write_2(sc->sc_iot, sc->sc_ioh, RTCINT_REG_W, RTCINT_ALL); 232 cf.pc = pc; 233 cf.sr = statusReg; 234 cf.intr = (curcpu()->ci_idepth > 1); 235 hardclock(&cf); 236 237 return 0; 238 } 239 240 void 241 vrrtc_init(struct device *dev) 242 { 243 struct vrrtc_softc *sc = (struct vrrtc_softc *)dev; 244 245 DDUMP_REGS(sc); 246 /* 247 * Set tick (CLOCK_RATE) 248 */ 249 bus_space_write_2(sc->sc_iot, sc->sc_ioh, RTCL1_H_REG_W, 0); 250 bus_space_write_2(sc->sc_iot, sc->sc_ioh, RTCL1_L_REG_W, 251 RTCL1_L_HZ/CLOCK_RATE); 252 253 /* 254 * Initialize timecounter. 255 */ 256 sc->sc_tc.tc_get_timecount = vrrtc_get_timecount; 257 sc->sc_tc.tc_name = "vrrtc"; 258 sc->sc_tc.tc_counter_mask = 0xffff; 259 sc->sc_tc.tc_frequency = ETIME_L_HZ; 260 sc->sc_tc.tc_priv = sc; 261 sc->sc_tc.tc_quality = 100; 262 tc_init(&sc->sc_tc); 263 } 264 265 uint32_t 266 vrrtc_get_timecount(struct timecounter *tc) 267 { 268 struct vrrtc_softc *sc = (struct vrrtc_softc *)tc->tc_priv; 269 bus_space_tag_t iot = sc->sc_iot; 270 bus_space_handle_t ioh = sc->sc_ioh; 271 272 return (bus_space_read_2(iot, ioh, ETIME_L_REG_W)); 273 } 274 275 int 276 vrrtc_get(todr_chip_handle_t tch, struct timeval *tvp) 277 { 278 279 struct vrrtc_softc *sc = (struct vrrtc_softc *)tch->cookie; 280 bus_space_tag_t iot = sc->sc_iot; 281 bus_space_handle_t ioh = sc->sc_ioh; 282 u_int32_t timeh; /* elapse time (2*timeh sec) */ 283 u_int32_t timel; /* timel/32768 sec */ 284 u_int64_t sec, usec; 285 286 timeh = bus_space_read_2(iot, ioh, ETIME_H_REG_W); 287 timeh = (timeh << 16) | bus_space_read_2(iot, ioh, ETIME_M_REG_W); 288 timel = bus_space_read_2(iot, ioh, ETIME_L_REG_W); 289 290 DPRINTF(("clock_get: timeh %08x timel %08x\n", timeh, timel)); 291 292 timeh -= EPOCHOFF; 293 sec = (uint64_t)timeh * 2; 294 sec -= sc->sc_epoch; 295 tvp->tv_sec = sec; 296 tvp->tv_sec += timel / ETIME_L_HZ; 297 298 /* scale from 32kHz to 1MHz */ 299 usec = (timel % ETIME_L_HZ); 300 usec *= 1000000; 301 usec /= ETIME_L_HZ; 302 tvp->tv_usec = usec; 303 304 return 0; 305 } 306 307 int 308 vrrtc_set(todr_chip_handle_t tch, struct timeval *tvp) 309 { 310 struct vrrtc_softc *sc = (struct vrrtc_softc *)tch->cookie; 311 bus_space_tag_t iot = sc->sc_iot; 312 bus_space_handle_t ioh = sc->sc_ioh; 313 u_int32_t timeh; /* elapse time (2*timeh sec) */ 314 u_int32_t timel; /* timel/32768 sec */ 315 int64_t sec, cnt; 316 317 sec = tvp->tv_sec + sc->sc_epoch; 318 sec += sc->sc_epoch; 319 timeh = EPOCHOFF + (sec / 2); 320 timel = sec % 2; 321 322 cnt = tvp->tv_usec; 323 /* scale from 1MHz to 32kHz */ 324 cnt *= ETIME_L_HZ; 325 cnt /= 1000000; 326 timel += (uint32_t)cnt; 327 328 bus_space_write_2(iot, ioh, ETIME_H_REG_W, (timeh >> 16) & 0xffff); 329 bus_space_write_2(iot, ioh, ETIME_M_REG_W, timeh & 0xffff); 330 bus_space_write_2(iot, ioh, ETIME_L_REG_W, timel); 331 332 return 0; 333 } 334 335 void 336 vrrtc_dump_regs(struct vrrtc_softc *sc) 337 { 338 int timeh; 339 int timel; 340 341 timeh = bus_space_read_2(sc->sc_iot, sc->sc_ioh, ETIME_H_REG_W); 342 timel = bus_space_read_2(sc->sc_iot, sc->sc_ioh, ETIME_M_REG_W); 343 timel = (timel << 16) 344 | bus_space_read_2(sc->sc_iot, sc->sc_ioh, ETIME_L_REG_W); 345 printf("clock_init() Elapse Time %04x%04x\n", timeh, timel); 346 347 timeh = bus_space_read_2(sc->sc_iot, sc->sc_ioh, ECMP_H_REG_W); 348 timel = bus_space_read_2(sc->sc_iot, sc->sc_ioh, ECMP_M_REG_W); 349 timel = (timel << 16) 350 | bus_space_read_2(sc->sc_iot, sc->sc_ioh, ECMP_L_REG_W); 351 printf("clock_init() Elapse Compare %04x%04x\n", timeh, timel); 352 353 timeh = bus_space_read_2(sc->sc_iot, sc->sc_ioh, RTCL1_H_REG_W); 354 timel = bus_space_read_2(sc->sc_iot, sc->sc_ioh, RTCL1_L_REG_W); 355 printf("clock_init() LONG1 %04x%04x\n", timeh, timel); 356 357 timeh = bus_space_read_2(sc->sc_iot, sc->sc_ioh, RTCL1_CNT_H_REG_W); 358 timel = bus_space_read_2(sc->sc_iot, sc->sc_ioh, RTCL1_CNT_L_REG_W); 359 printf("clock_init() LONG1 CNTL %04x%04x\n", timeh, timel); 360 361 timeh = bus_space_read_2(sc->sc_iot, sc->sc_ioh, RTCL2_H_REG_W); 362 timel = bus_space_read_2(sc->sc_iot, sc->sc_ioh, RTCL2_L_REG_W); 363 printf("clock_init() LONG2 %04x%04x\n", timeh, timel); 364 365 timeh = bus_space_read_2(sc->sc_iot, sc->sc_ioh, RTCL2_CNT_H_REG_W); 366 timel = bus_space_read_2(sc->sc_iot, sc->sc_ioh, RTCL2_CNT_L_REG_W); 367 printf("clock_init() LONG2 CNTL %04x%04x\n", timeh, timel); 368 369 if (TCLK_H_REG_W != RTC_NO_REG_W) { 370 timeh = bus_space_read_2(sc->sc_iot, sc->sc_ioh, TCLK_H_REG_W); 371 timel = bus_space_read_2(sc->sc_iot, sc->sc_ioh, TCLK_L_REG_W); 372 printf("clock_init() TCLK %04x%04x\n", timeh, timel); 373 374 timeh = bus_space_read_2(sc->sc_iot, sc->sc_ioh, TCLK_CNT_H_REG_W); 375 timel = bus_space_read_2(sc->sc_iot, sc->sc_ioh, TCLK_CNT_L_REG_W); 376 printf("clock_init() TCLK CNTL %04x%04x\n", timeh, timel); 377 } 378 } 379
Indexes created Tue Sep 30 11:09:46 GMT 2025