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vr.c revision 1.31.4.3
      1  1.31.4.3  nathanw /*	$NetBSD: vr.c,v 1.31.4.3 2002/01/11 23:38:26 nathanw Exp $	*/
      2  1.31.4.2  nathanw 
      3  1.31.4.2  nathanw /*-
      4  1.31.4.3  nathanw  * Copyright (c) 1999-2002
      5  1.31.4.2  nathanw  *         Shin Takemura and PocketBSD Project. All rights reserved.
      6  1.31.4.2  nathanw  *
      7  1.31.4.2  nathanw  * Redistribution and use in source and binary forms, with or without
      8  1.31.4.2  nathanw  * modification, are permitted provided that the following conditions
      9  1.31.4.2  nathanw  * are met:
     10  1.31.4.2  nathanw  * 1. Redistributions of source code must retain the above copyright
     11  1.31.4.2  nathanw  *    notice, this list of conditions and the following disclaimer.
     12  1.31.4.2  nathanw  * 2. Redistributions in binary form must reproduce the above copyright
     13  1.31.4.2  nathanw  *    notice, this list of conditions and the following disclaimer in the
     14  1.31.4.2  nathanw  *    documentation and/or other materials provided with the distribution.
     15  1.31.4.2  nathanw  * 3. All advertising materials mentioning features or use of this software
     16  1.31.4.2  nathanw  *    must display the following acknowledgement:
     17  1.31.4.2  nathanw  *	This product includes software developed by the PocketBSD project
     18  1.31.4.2  nathanw  *	and its contributors.
     19  1.31.4.2  nathanw  * 4. Neither the name of the project nor the names of its contributors
     20  1.31.4.2  nathanw  *    may be used to endorse or promote products derived from this software
     21  1.31.4.2  nathanw  *    without specific prior written permission.
     22  1.31.4.2  nathanw  *
     23  1.31.4.2  nathanw  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
     24  1.31.4.2  nathanw  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     25  1.31.4.2  nathanw  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     26  1.31.4.2  nathanw  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
     27  1.31.4.2  nathanw  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     28  1.31.4.2  nathanw  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     29  1.31.4.2  nathanw  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     30  1.31.4.2  nathanw  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     31  1.31.4.2  nathanw  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     32  1.31.4.2  nathanw  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     33  1.31.4.2  nathanw  * SUCH DAMAGE.
     34  1.31.4.2  nathanw  *
     35  1.31.4.2  nathanw  */
     36  1.31.4.2  nathanw 
     37  1.31.4.2  nathanw #include "opt_vr41xx.h"
     38  1.31.4.2  nathanw #include "opt_tx39xx.h"
     39  1.31.4.2  nathanw #include "opt_kgdb.h"
     40  1.31.4.2  nathanw 
     41  1.31.4.2  nathanw #include <sys/param.h>
     42  1.31.4.2  nathanw #include <sys/systm.h>
     43  1.31.4.2  nathanw #include <sys/reboot.h>
     44  1.31.4.2  nathanw 
     45  1.31.4.2  nathanw #include <uvm/uvm_extern.h>
     46  1.31.4.2  nathanw 
     47  1.31.4.2  nathanw #include <machine/sysconf.h>
     48  1.31.4.2  nathanw #include <machine/bootinfo.h>
     49  1.31.4.2  nathanw #include <machine/bus.h>
     50  1.31.4.2  nathanw #include <machine/bus_space_hpcmips.h>
     51  1.31.4.3  nathanw #include <machine/platid.h>
     52  1.31.4.3  nathanw #include <machine/platid_mask.h>
     53  1.31.4.2  nathanw 
     54  1.31.4.2  nathanw #include <dev/hpc/hpckbdvar.h>
     55  1.31.4.2  nathanw 
     56  1.31.4.2  nathanw #include <hpcmips/hpcmips/machdep.h>	/* cpu_name, mem_cluster */
     57  1.31.4.2  nathanw 
     58  1.31.4.2  nathanw #include <hpcmips/vr/vr.h>
     59  1.31.4.2  nathanw #include <hpcmips/vr/vr_asm.h>
     60  1.31.4.2  nathanw #include <hpcmips/vr/vrcpudef.h>
     61  1.31.4.2  nathanw #include <hpcmips/vr/vripreg.h>
     62  1.31.4.2  nathanw #include <hpcmips/vr/rtcreg.h>
     63  1.31.4.2  nathanw 
     64  1.31.4.2  nathanw #include "vrip.h"
     65  1.31.4.2  nathanw #if NVRIP > 0
     66  1.31.4.2  nathanw #include <hpcmips/vr/vripvar.h>
     67  1.31.4.2  nathanw #endif
     68  1.31.4.2  nathanw 
     69  1.31.4.2  nathanw #include "vrbcu.h"
     70  1.31.4.2  nathanw #if NVRBCU > 0
     71  1.31.4.2  nathanw #include <hpcmips/vr/bcuvar.h>
     72  1.31.4.2  nathanw #endif
     73  1.31.4.2  nathanw 
     74  1.31.4.2  nathanw #include "vrdsu.h"
     75  1.31.4.2  nathanw #if NVRDSU > 0
     76  1.31.4.2  nathanw #include <hpcmips/vr/vrdsuvar.h>
     77  1.31.4.2  nathanw #endif
     78  1.31.4.2  nathanw 
     79  1.31.4.2  nathanw #include "com.h"
     80  1.31.4.3  nathanw #include "com_vrip.h"
     81  1.31.4.3  nathanw #include "com_hpcio.h"
     82  1.31.4.3  nathanw #if NCOM > 0
     83  1.31.4.2  nathanw #include <sys/termios.h>
     84  1.31.4.2  nathanw #include <sys/ttydefaults.h>
     85  1.31.4.2  nathanw #include <dev/ic/comreg.h>
     86  1.31.4.2  nathanw #include <dev/ic/comvar.h>
     87  1.31.4.3  nathanw #if NCOM_VRIP > 0
     88  1.31.4.2  nathanw #include <hpcmips/vr/siureg.h>
     89  1.31.4.2  nathanw #include <hpcmips/vr/com_vripvar.h>
     90  1.31.4.2  nathanw #endif
     91  1.31.4.3  nathanw #if NCOM_HPCIO > 0
     92  1.31.4.3  nathanw #include <hpcmips/dev/com_hpciovar.h>
     93  1.31.4.2  nathanw #endif
     94  1.31.4.2  nathanw #ifndef CONSPEED
     95  1.31.4.2  nathanw #define CONSPEED TTYDEF_SPEED
     96  1.31.4.2  nathanw #endif
     97  1.31.4.2  nathanw #endif
     98  1.31.4.2  nathanw 
     99  1.31.4.2  nathanw #include "hpcfb.h"
    100  1.31.4.2  nathanw #include "vrkiu.h"
    101  1.31.4.2  nathanw #if (NVRKIU > 0) || (NHPCFB > 0)
    102  1.31.4.2  nathanw #include <dev/wscons/wsdisplayvar.h>
    103  1.31.4.2  nathanw #include <dev/rasops/rasops.h>
    104  1.31.4.2  nathanw #endif
    105  1.31.4.2  nathanw 
    106  1.31.4.2  nathanw #if NHPCFB > 0
    107  1.31.4.2  nathanw #include <dev/hpc/hpcfbvar.h>
    108  1.31.4.2  nathanw #endif
    109  1.31.4.2  nathanw 
    110  1.31.4.2  nathanw #if NVRKIU > 0
    111  1.31.4.2  nathanw #include <arch/hpcmips/vr/vrkiureg.h>
    112  1.31.4.2  nathanw #include <arch/hpcmips/vr/vrkiuvar.h>
    113  1.31.4.2  nathanw #endif
    114  1.31.4.2  nathanw 
    115  1.31.4.2  nathanw #ifdef DEBUG
    116  1.31.4.2  nathanw #define STATIC
    117  1.31.4.2  nathanw #else
    118  1.31.4.2  nathanw #define STATIC	static
    119  1.31.4.2  nathanw #endif
    120  1.31.4.2  nathanw 
    121  1.31.4.2  nathanw /*
    122  1.31.4.2  nathanw  * This is a mask of bits to clear in the SR when we go to a
    123  1.31.4.2  nathanw  * given interrupt priority level.
    124  1.31.4.2  nathanw  */
    125  1.31.4.2  nathanw const u_int32_t __ipl_sr_bits_vr[_IPL_N] = {
    126  1.31.4.2  nathanw 	0,					/* IPL_NONE */
    127  1.31.4.2  nathanw 
    128  1.31.4.2  nathanw 	MIPS_SOFT_INT_MASK_0,			/* IPL_SOFT */
    129  1.31.4.2  nathanw 
    130  1.31.4.2  nathanw 	MIPS_SOFT_INT_MASK_0,			/* IPL_SOFTCLOCK */
    131  1.31.4.2  nathanw 
    132  1.31.4.2  nathanw 	MIPS_SOFT_INT_MASK_0|
    133  1.31.4.2  nathanw 		MIPS_SOFT_INT_MASK_1,		/* IPL_SOFTNET */
    134  1.31.4.2  nathanw 
    135  1.31.4.2  nathanw 	MIPS_SOFT_INT_MASK_0|
    136  1.31.4.2  nathanw 		MIPS_SOFT_INT_MASK_1,		/* IPL_SOFTSERIAL */
    137  1.31.4.2  nathanw 
    138  1.31.4.2  nathanw 	MIPS_SOFT_INT_MASK_0|
    139  1.31.4.2  nathanw 		MIPS_SOFT_INT_MASK_1|
    140  1.31.4.2  nathanw 		MIPS_INT_MASK_0,		/* IPL_BIO */
    141  1.31.4.2  nathanw 
    142  1.31.4.2  nathanw 	MIPS_SOFT_INT_MASK_0|
    143  1.31.4.2  nathanw 		MIPS_SOFT_INT_MASK_1|
    144  1.31.4.2  nathanw 		MIPS_INT_MASK_0,		/* IPL_NET */
    145  1.31.4.2  nathanw 
    146  1.31.4.2  nathanw 	MIPS_SOFT_INT_MASK_0|
    147  1.31.4.2  nathanw 		MIPS_SOFT_INT_MASK_1|
    148  1.31.4.2  nathanw 		MIPS_INT_MASK_0,		/* IPL_{TTY,SERIAL} */
    149  1.31.4.2  nathanw 
    150  1.31.4.2  nathanw 	MIPS_SOFT_INT_MASK_0|
    151  1.31.4.2  nathanw 		MIPS_SOFT_INT_MASK_1|
    152  1.31.4.2  nathanw 		MIPS_INT_MASK_0|
    153  1.31.4.2  nathanw 		MIPS_INT_MASK_1,		/* IPL_{CLOCK,HIGH} */
    154  1.31.4.2  nathanw };
    155  1.31.4.2  nathanw 
    156  1.31.4.2  nathanw #if defined(VR41XX) && defined(TX39XX)
    157  1.31.4.2  nathanw #define	VR_INTR	vr_intr
    158  1.31.4.2  nathanw #else
    159  1.31.4.2  nathanw #define	VR_INTR	cpu_intr	/* locore_mips3 directly call this */
    160  1.31.4.2  nathanw #endif
    161  1.31.4.2  nathanw 
    162  1.31.4.2  nathanw void vr_init(void);
    163  1.31.4.2  nathanw void VR_INTR(u_int32_t, u_int32_t, u_int32_t, u_int32_t);
    164  1.31.4.2  nathanw extern void vr_idle(void);
    165  1.31.4.2  nathanw STATIC void vr_cons_init(void);
    166  1.31.4.2  nathanw STATIC void vr_fb_init(caddr_t *);
    167  1.31.4.2  nathanw STATIC void vr_mem_init(paddr_t);
    168  1.31.4.2  nathanw STATIC void vr_find_dram(paddr_t, paddr_t);
    169  1.31.4.2  nathanw STATIC void vr_reboot(int, char *);
    170  1.31.4.2  nathanw 
    171  1.31.4.2  nathanw /*
    172  1.31.4.2  nathanw  * CPU interrupt dispatch table (HwInt[0:3])
    173  1.31.4.2  nathanw  */
    174  1.31.4.2  nathanw STATIC int vr_null_handler(void *, u_int32_t, u_int32_t);
    175  1.31.4.2  nathanw STATIC int (*vr_intr_handler[4])(void *, u_int32_t, u_int32_t) =
    176  1.31.4.2  nathanw {
    177  1.31.4.2  nathanw 	vr_null_handler,
    178  1.31.4.2  nathanw 	vr_null_handler,
    179  1.31.4.2  nathanw 	vr_null_handler,
    180  1.31.4.2  nathanw 	vr_null_handler
    181  1.31.4.2  nathanw };
    182  1.31.4.2  nathanw STATIC void *vr_intr_arg[4];
    183  1.31.4.2  nathanw 
    184  1.31.4.3  nathanw #if NCOM > 0
    185  1.31.4.3  nathanw /*
    186  1.31.4.3  nathanw  * machine dependent serial console info
    187  1.31.4.3  nathanw  */
    188  1.31.4.3  nathanw static struct vr_com_platdep {
    189  1.31.4.3  nathanw 	platid_mask_t *platidmask;
    190  1.31.4.3  nathanw 	int (*attach)(bus_space_tag_t, int, int, int, tcflag_t, int);
    191  1.31.4.3  nathanw 	int addr;
    192  1.31.4.3  nathanw 	int freq;
    193  1.31.4.3  nathanw } platdep_com_table[] = {
    194  1.31.4.3  nathanw #if NCOM_HPCIO > 0
    195  1.31.4.3  nathanw 	{
    196  1.31.4.3  nathanw 		&platid_mask_MACH_NEC_MCR_SIGMARION2,
    197  1.31.4.3  nathanw 		com_hpcio_cndb_attach,	/* attach proc */
    198  1.31.4.3  nathanw 		0x0b600000,		/* base address */
    199  1.31.4.3  nathanw 		COM_FREQ,		/* frequency */
    200  1.31.4.3  nathanw 	},
    201  1.31.4.3  nathanw #endif
    202  1.31.4.3  nathanw #if NCOM_VRIP > 0
    203  1.31.4.3  nathanw 	{
    204  1.31.4.3  nathanw 		&platid_wild,
    205  1.31.4.3  nathanw 		com_vrip_cndb_attach,	/* attach proc */
    206  1.31.4.3  nathanw 		VRIP_SIU_ADDR,		/* base address */
    207  1.31.4.3  nathanw 		VRCOM_FREQ,		/* frequency */
    208  1.31.4.3  nathanw 	},
    209  1.31.4.3  nathanw #else
    210  1.31.4.3  nathanw 	/* dummy */
    211  1.31.4.3  nathanw 	{
    212  1.31.4.3  nathanw 		&platid_wild,
    213  1.31.4.3  nathanw 		NULL,			/* attach proc */
    214  1.31.4.3  nathanw 		0,			/* base address */
    215  1.31.4.3  nathanw 		0,			/* frequency */
    216  1.31.4.3  nathanw 	},
    217  1.31.4.3  nathanw #endif
    218  1.31.4.3  nathanw };
    219  1.31.4.3  nathanw #endif /* NCOM > 0 */
    220  1.31.4.3  nathanw 
    221  1.31.4.2  nathanw void
    222  1.31.4.2  nathanw vr_init()
    223  1.31.4.2  nathanw {
    224  1.31.4.2  nathanw 	/*
    225  1.31.4.2  nathanw 	 * Platform Specific Function Hooks
    226  1.31.4.2  nathanw 	 */
    227  1.31.4.2  nathanw 	platform.cpu_idle	= vr_idle;
    228  1.31.4.2  nathanw 	platform.cpu_intr	= VR_INTR;
    229  1.31.4.2  nathanw 	platform.cons_init	= vr_cons_init;
    230  1.31.4.2  nathanw 	platform.fb_init	= vr_fb_init;
    231  1.31.4.2  nathanw 	platform.mem_init	= vr_mem_init;
    232  1.31.4.2  nathanw 	platform.reboot		= vr_reboot;
    233  1.31.4.2  nathanw 
    234  1.31.4.2  nathanw #if NVRBCU > 0
    235  1.31.4.2  nathanw 	sprintf(cpu_name, "NEC %s rev%d.%d %d.%03dMHz",
    236  1.31.4.2  nathanw 		vrbcu_vrip_getcpuname(),
    237  1.31.4.2  nathanw 		vrbcu_vrip_getcpumajor(),
    238  1.31.4.2  nathanw 		vrbcu_vrip_getcpuminor(),
    239  1.31.4.2  nathanw 		vrbcu_vrip_getcpuclock() / 1000000,
    240  1.31.4.2  nathanw 		(vrbcu_vrip_getcpuclock() % 1000000) / 1000);
    241  1.31.4.2  nathanw #else
    242  1.31.4.2  nathanw 	sprintf(cpu_name, "NEC VR41xx");
    243  1.31.4.2  nathanw #endif
    244  1.31.4.2  nathanw }
    245  1.31.4.2  nathanw 
    246  1.31.4.2  nathanw void
    247  1.31.4.2  nathanw vr_mem_init(paddr_t kernend)
    248  1.31.4.2  nathanw {
    249  1.31.4.2  nathanw 
    250  1.31.4.2  nathanw 	mem_clusters[0].start = 0;
    251  1.31.4.2  nathanw 	mem_clusters[0].size = kernend;
    252  1.31.4.2  nathanw 	mem_cluster_cnt = 1;
    253  1.31.4.2  nathanw 
    254  1.31.4.2  nathanw 	vr_find_dram(kernend, 0x02000000);
    255  1.31.4.2  nathanw 	vr_find_dram(0x02000000, 0x04000000);
    256  1.31.4.2  nathanw 	vr_find_dram(0x04000000, 0x06000000);
    257  1.31.4.2  nathanw 	vr_find_dram(0x06000000, 0x08000000);
    258  1.31.4.2  nathanw }
    259  1.31.4.2  nathanw 
    260  1.31.4.2  nathanw void
    261  1.31.4.2  nathanw vr_find_dram(paddr_t addr, paddr_t end)
    262  1.31.4.2  nathanw {
    263  1.31.4.2  nathanw 	int n;
    264  1.31.4.2  nathanw 	caddr_t page;
    265  1.31.4.2  nathanw #ifdef NARLY_MEMORY_PROBE
    266  1.31.4.2  nathanw 	int x, i;
    267  1.31.4.2  nathanw #endif
    268  1.31.4.2  nathanw 
    269  1.31.4.2  nathanw #ifdef VR_FIND_DRAMLIM
    270  1.31.4.2  nathanw 	if (VR_FIND_DRAMLIM < end)
    271  1.31.4.2  nathanw 		end = VR_FIND_DRAMLIM;
    272  1.31.4.2  nathanw #endif /* VR_FIND_DRAMLIM */
    273  1.31.4.2  nathanw 	n = mem_cluster_cnt;
    274  1.31.4.2  nathanw 	for (; addr < end; addr += NBPG) {
    275  1.31.4.2  nathanw 
    276  1.31.4.2  nathanw 		page = (void *)MIPS_PHYS_TO_KSEG1(addr);
    277  1.31.4.2  nathanw 		if (badaddr(page, 4))
    278  1.31.4.2  nathanw 			goto bad;
    279  1.31.4.2  nathanw 
    280  1.31.4.2  nathanw 		/* stop memory probing at first memory image */
    281  1.31.4.2  nathanw 		if (bcmp(page, (void *)MIPS_PHYS_TO_KSEG0(0), 128) == 0)
    282  1.31.4.2  nathanw 			return;
    283  1.31.4.2  nathanw 
    284  1.31.4.2  nathanw 		*(volatile int *)(page+0) = 0xa5a5a5a5;
    285  1.31.4.2  nathanw 		*(volatile int *)(page+4) = 0x5a5a5a5a;
    286  1.31.4.2  nathanw 		wbflush();
    287  1.31.4.2  nathanw 		if (*(volatile int *)(page+0) != 0xa5a5a5a5)
    288  1.31.4.2  nathanw 			goto bad;
    289  1.31.4.2  nathanw 
    290  1.31.4.2  nathanw 		*(volatile int *)(page+0) = 0x5a5a5a5a;
    291  1.31.4.2  nathanw 		*(volatile int *)(page+4) = 0xa5a5a5a5;
    292  1.31.4.2  nathanw 		wbflush();
    293  1.31.4.2  nathanw 		if (*(volatile int *)(page+0) != 0x5a5a5a5a)
    294  1.31.4.2  nathanw 			goto bad;
    295  1.31.4.2  nathanw 
    296  1.31.4.2  nathanw #ifdef NARLY_MEMORY_PROBE
    297  1.31.4.2  nathanw 		x = random();
    298  1.31.4.2  nathanw 		for (i = 0; i < NBPG; i += 4)
    299  1.31.4.2  nathanw 			*(volatile int *)(page+i) = (x ^ i);
    300  1.31.4.2  nathanw 		wbflush();
    301  1.31.4.2  nathanw 		for (i = 0; i < NBPG; i += 4)
    302  1.31.4.2  nathanw 			if (*(volatile int *)(page+i) != (x ^ i))
    303  1.31.4.2  nathanw 				goto bad;
    304  1.31.4.2  nathanw 
    305  1.31.4.2  nathanw 		x = random();
    306  1.31.4.2  nathanw 		for (i = 0; i < NBPG; i += 4)
    307  1.31.4.2  nathanw 			*(volatile int *)(page+i) = (x ^ i);
    308  1.31.4.2  nathanw 		wbflush();
    309  1.31.4.2  nathanw 		for (i = 0; i < NBPG; i += 4)
    310  1.31.4.2  nathanw 			if (*(volatile int *)(page+i) != (x ^ i))
    311  1.31.4.2  nathanw 				goto bad;
    312  1.31.4.2  nathanw #endif /* NARLY_MEMORY_PROBE */
    313  1.31.4.2  nathanw 
    314  1.31.4.2  nathanw 		if (!mem_clusters[n].size)
    315  1.31.4.2  nathanw 			mem_clusters[n].start = addr;
    316  1.31.4.2  nathanw 		mem_clusters[n].size += NBPG;
    317  1.31.4.2  nathanw 		continue;
    318  1.31.4.2  nathanw 
    319  1.31.4.2  nathanw 	bad:
    320  1.31.4.2  nathanw 		if (mem_clusters[n].size)
    321  1.31.4.2  nathanw 			++n;
    322  1.31.4.2  nathanw 		continue;
    323  1.31.4.2  nathanw 	}
    324  1.31.4.2  nathanw 	if (mem_clusters[n].size)
    325  1.31.4.2  nathanw 		++n;
    326  1.31.4.2  nathanw 	mem_cluster_cnt = n;
    327  1.31.4.2  nathanw }
    328  1.31.4.2  nathanw 
    329  1.31.4.2  nathanw void
    330  1.31.4.2  nathanw vr_fb_init(caddr_t *kernend)
    331  1.31.4.2  nathanw {
    332  1.31.4.2  nathanw 	/* Nothing to do */
    333  1.31.4.2  nathanw }
    334  1.31.4.2  nathanw 
    335  1.31.4.2  nathanw void
    336  1.31.4.2  nathanw vr_cons_init()
    337  1.31.4.2  nathanw {
    338  1.31.4.3  nathanw #if NCOM > 0 || NHPCFB > 0 || NVRKIU > 0
    339  1.31.4.2  nathanw 	bus_space_tag_t iot = hpcmips_system_bus_space();
    340  1.31.4.2  nathanw #endif
    341  1.31.4.3  nathanw #if NCOM > 0
    342  1.31.4.3  nathanw 	static struct vr_com_platdep *com_info;
    343  1.31.4.3  nathanw #endif
    344  1.31.4.2  nathanw 
    345  1.31.4.2  nathanw #if NCOM > 0
    346  1.31.4.3  nathanw 	com_info = platid_search(&platid, platdep_com_table,
    347  1.31.4.3  nathanw 	    sizeof(platdep_com_table)/sizeof(*platdep_com_table),
    348  1.31.4.3  nathanw 	    sizeof(*platdep_com_table));
    349  1.31.4.2  nathanw #ifdef KGDB
    350  1.31.4.3  nathanw 	if (com_info->attach != NULL) {
    351  1.31.4.3  nathanw 		/* if KGDB is defined, always use the serial port for KGDB */
    352  1.31.4.3  nathanw 		if ((*com_info->attach)(iot, com_info->addr, 9600,
    353  1.31.4.3  nathanw 		    com_info->freq,
    354  1.31.4.3  nathanw 		    (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8, 1)) {
    355  1.31.4.3  nathanw 			printf("%s(%d): can't init kgdb's serial port",
    356  1.31.4.2  nathanw 			    __FILE__, __LINE__);
    357  1.31.4.2  nathanw 		}
    358  1.31.4.2  nathanw #else /* KGDB */
    359  1.31.4.3  nathanw 	if (com_info->attach != NULL && (bootinfo->bi_cnuse&BI_CNUSE_SERIAL)) {
    360  1.31.4.2  nathanw 		/* Serial console */
    361  1.31.4.3  nathanw 		if ((*com_info->attach)(iot, com_info->addr, CONSPEED,
    362  1.31.4.3  nathanw 		    com_info->freq,
    363  1.31.4.3  nathanw 		    (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8, 0)) {
    364  1.31.4.2  nathanw 			printf("%s(%d): can't init serial console",
    365  1.31.4.2  nathanw 			    __FILE__, __LINE__);
    366  1.31.4.2  nathanw 		} else {
    367  1.31.4.2  nathanw 			return;
    368  1.31.4.2  nathanw 		}
    369  1.31.4.2  nathanw 	}
    370  1.31.4.2  nathanw #endif /* KGDB */
    371  1.31.4.3  nathanw #endif /* NCOM > 0 */
    372  1.31.4.2  nathanw 
    373  1.31.4.2  nathanw #if NHPCFB > 0
    374  1.31.4.2  nathanw 	if (hpcfb_cnattach(NULL)) {
    375  1.31.4.2  nathanw 		printf("%s(%d): can't init fb console", __FILE__, __LINE__);
    376  1.31.4.2  nathanw 	} else {
    377  1.31.4.2  nathanw 		goto find_keyboard;
    378  1.31.4.2  nathanw 	}
    379  1.31.4.2  nathanw  find_keyboard:
    380  1.31.4.2  nathanw #endif /* NHPCFB > 0 */
    381  1.31.4.2  nathanw 
    382  1.31.4.2  nathanw #if NVRKIU > 0 && VRIP_KIU_ADDR != VRIP_NO_ADDR
    383  1.31.4.2  nathanw 	if (vrkiu_cnattach(iot, VRIP_KIU_ADDR)) {
    384  1.31.4.2  nathanw 		printf("%s(%d): can't init vrkiu as console",
    385  1.31.4.2  nathanw 		       __FILE__, __LINE__);
    386  1.31.4.2  nathanw 	} else {
    387  1.31.4.2  nathanw 		return;
    388  1.31.4.2  nathanw 	}
    389  1.31.4.2  nathanw #endif /* NVRKIU > 0 && VRIP_KIU_ADDR != VRIP_NO_ADDR */
    390  1.31.4.2  nathanw }
    391  1.31.4.2  nathanw 
    392  1.31.4.2  nathanw void
    393  1.31.4.2  nathanw vr_reboot(int howto, char *bootstr)
    394  1.31.4.2  nathanw {
    395  1.31.4.2  nathanw 	/*
    396  1.31.4.2  nathanw 	 * power down
    397  1.31.4.2  nathanw 	 */
    398  1.31.4.2  nathanw 	if ((howto & RB_POWERDOWN) == RB_POWERDOWN) {
    399  1.31.4.2  nathanw 		printf("fake powerdown\n");
    400  1.31.4.2  nathanw 		__asm(__CONCAT(".word	",___STRING(VR_OPCODE_HIBERNATE)));
    401  1.31.4.2  nathanw 		__asm("nop");
    402  1.31.4.2  nathanw 		__asm("nop");
    403  1.31.4.2  nathanw 		__asm("nop");
    404  1.31.4.2  nathanw 		__asm("nop");
    405  1.31.4.2  nathanw 		__asm("nop");
    406  1.31.4.2  nathanw 		__asm(".set reorder");
    407  1.31.4.2  nathanw 		/* not reach */
    408  1.31.4.2  nathanw 		vr_reboot(howto&~RB_HALT, bootstr);
    409  1.31.4.2  nathanw 	}
    410  1.31.4.2  nathanw 	/*
    411  1.31.4.2  nathanw 	 * halt
    412  1.31.4.2  nathanw 	 */
    413  1.31.4.2  nathanw 	if (howto & RB_HALT) {
    414  1.31.4.2  nathanw #if NVRIP > 0
    415  1.31.4.2  nathanw 		_spllower(~MIPS_INT_MASK_0);
    416  1.31.4.2  nathanw 		vrip_intr_suspend();
    417  1.31.4.2  nathanw #else
    418  1.31.4.2  nathanw 		splhigh();
    419  1.31.4.2  nathanw #endif
    420  1.31.4.2  nathanw 		__asm(".set noreorder");
    421  1.31.4.2  nathanw 		__asm(__CONCAT(".word	",___STRING(VR_OPCODE_SUSPEND)));
    422  1.31.4.2  nathanw 		__asm("nop");
    423  1.31.4.2  nathanw 		__asm("nop");
    424  1.31.4.2  nathanw 		__asm("nop");
    425  1.31.4.2  nathanw 		__asm("nop");
    426  1.31.4.2  nathanw 		__asm("nop");
    427  1.31.4.2  nathanw 		__asm(".set reorder");
    428  1.31.4.2  nathanw #if NVRIP > 0
    429  1.31.4.2  nathanw 		vrip_intr_resume();
    430  1.31.4.2  nathanw #endif
    431  1.31.4.2  nathanw 	}
    432  1.31.4.2  nathanw 	/*
    433  1.31.4.2  nathanw 	 * reset
    434  1.31.4.2  nathanw 	 */
    435  1.31.4.2  nathanw #if NVRDSU
    436  1.31.4.2  nathanw 	vrdsu_reset();
    437  1.31.4.2  nathanw #else
    438  1.31.4.2  nathanw 	printf("%s(%d): There is no DSU.", __FILE__, __LINE__);
    439  1.31.4.2  nathanw #endif
    440  1.31.4.2  nathanw }
    441  1.31.4.2  nathanw 
    442  1.31.4.2  nathanw /*
    443  1.31.4.2  nathanw  * Handle interrupts.
    444  1.31.4.2  nathanw  */
    445  1.31.4.2  nathanw void
    446  1.31.4.2  nathanw VR_INTR(u_int32_t status, u_int32_t cause, u_int32_t pc, u_int32_t ipending)
    447  1.31.4.2  nathanw {
    448  1.31.4.2  nathanw 	uvmexp.intrs++;
    449  1.31.4.2  nathanw 
    450  1.31.4.2  nathanw 	if (ipending & MIPS_INT_MASK_5) {
    451  1.31.4.2  nathanw 		/*
    452  1.31.4.2  nathanw 		 * spl* uses MIPS_INT_MASK not MIPS3_INT_MASK. it causes
    453  1.31.4.2  nathanw 		 * INT5 interrupt.
    454  1.31.4.2  nathanw 		 */
    455  1.31.4.2  nathanw 		mips3_cp0_compare_write(mips3_cp0_count_read());
    456  1.31.4.2  nathanw 	}
    457  1.31.4.2  nathanw 
    458  1.31.4.2  nathanw 	/* for spllowersoftclock */
    459  1.31.4.2  nathanw 	_splset(((status & ~cause) & MIPS_HARD_INT_MASK) | MIPS_SR_INT_IE);
    460  1.31.4.2  nathanw 
    461  1.31.4.2  nathanw 	if (ipending & MIPS_INT_MASK_1) {
    462  1.31.4.2  nathanw 		(*vr_intr_handler[1])(vr_intr_arg[1], pc, status);
    463  1.31.4.2  nathanw 
    464  1.31.4.2  nathanw 		cause &= ~MIPS_INT_MASK_1;
    465  1.31.4.2  nathanw 		_splset(((status & ~cause) & MIPS_HARD_INT_MASK)
    466  1.31.4.2  nathanw 		    | MIPS_SR_INT_IE);
    467  1.31.4.2  nathanw 	}
    468  1.31.4.2  nathanw 
    469  1.31.4.2  nathanw 	if (ipending & MIPS_INT_MASK_0) {
    470  1.31.4.2  nathanw 		(*vr_intr_handler[0])(vr_intr_arg[0], pc, status);
    471  1.31.4.2  nathanw 
    472  1.31.4.2  nathanw 		cause &= ~MIPS_INT_MASK_0;
    473  1.31.4.2  nathanw 	}
    474  1.31.4.2  nathanw 	_splset(((status & ~cause) & MIPS_HARD_INT_MASK) | MIPS_SR_INT_IE);
    475  1.31.4.2  nathanw 
    476  1.31.4.2  nathanw 	softintr(ipending);
    477  1.31.4.2  nathanw }
    478  1.31.4.2  nathanw 
    479  1.31.4.2  nathanw void *
    480  1.31.4.2  nathanw vr_intr_establish(int line, int (*ih_fun)(void *, u_int32_t, u_int32_t),
    481  1.31.4.2  nathanw     void *ih_arg)
    482  1.31.4.2  nathanw {
    483  1.31.4.2  nathanw 
    484  1.31.4.2  nathanw 	KDASSERT(vr_intr_handler[line] == vr_null_handler);
    485  1.31.4.2  nathanw 
    486  1.31.4.2  nathanw 	vr_intr_handler[line] = ih_fun;
    487  1.31.4.2  nathanw 	vr_intr_arg[line] = ih_arg;
    488  1.31.4.2  nathanw 
    489  1.31.4.2  nathanw 	return ((void *)line);
    490  1.31.4.2  nathanw }
    491  1.31.4.2  nathanw 
    492  1.31.4.2  nathanw void
    493  1.31.4.2  nathanw vr_intr_disestablish(void *ih)
    494  1.31.4.2  nathanw {
    495  1.31.4.2  nathanw 	int line = (int)ih;
    496  1.31.4.2  nathanw 
    497  1.31.4.2  nathanw 	vr_intr_handler[line] = vr_null_handler;
    498  1.31.4.2  nathanw 	vr_intr_arg[line] = NULL;
    499  1.31.4.2  nathanw }
    500  1.31.4.2  nathanw 
    501  1.31.4.2  nathanw int
    502  1.31.4.2  nathanw vr_null_handler(void *arg, u_int32_t pc, u_int32_t status)
    503  1.31.4.2  nathanw {
    504  1.31.4.2  nathanw 
    505  1.31.4.2  nathanw 	printf("vr_null_handler\n");
    506  1.31.4.2  nathanw 
    507  1.31.4.2  nathanw 	return (0);
    508  1.31.4.2  nathanw }
    509  1.31.4.2  nathanw 
    510  1.31.4.2  nathanw /*
    511  1.31.4.2  nathanw int x4181 = VR4181;
    512  1.31.4.2  nathanw int x4101 = VR4101;
    513  1.31.4.2  nathanw int x4102 = VR4102;
    514  1.31.4.2  nathanw int x4111 = VR4111;
    515  1.31.4.2  nathanw int x4121 = VR4121;
    516  1.31.4.2  nathanw int x4122 = VR4122;
    517  1.31.4.2  nathanw int xo4181 = ONLY_VR4181;
    518  1.31.4.2  nathanw int xo4101 = ONLY_VR4101;
    519  1.31.4.2  nathanw int xo4102 = ONLY_VR4102;
    520  1.31.4.2  nathanw int xo4111_4121 = ONLY_VR4111_4121;
    521  1.31.4.2  nathanw int g4101=VRGROUP_4101;
    522  1.31.4.2  nathanw int g4102=VRGROUP_4102;
    523  1.31.4.2  nathanw int g4181=VRGROUP_4181;
    524  1.31.4.2  nathanw int g4102_4121=VRGROUP_4102_4121;
    525  1.31.4.2  nathanw int g4111_4121=VRGROUP_4111_4121;
    526  1.31.4.2  nathanw int g4102_4122=VRGROUP_4102_4122;
    527  1.31.4.2  nathanw int g4111_4122=VRGROUP_4111_4122;
    528  1.31.4.2  nathanw int single_vrip_base=SINGLE_VRIP_BASE;
    529  1.31.4.2  nathanw int vrip_base_addr=VRIP_BASE_ADDR;
    530  1.31.4.2  nathanw */
    531