vr.c revision 1.38
1 /* $NetBSD: vr.c,v 1.38 2002/02/11 09:21:47 takemura Exp $ */ 2 3 /*- 4 * Copyright (c) 1999-2002 5 * Shin Takemura and PocketBSD Project. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the PocketBSD project 18 * and its contributors. 19 * 4. Neither the name of the project nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 */ 36 37 #include "opt_vr41xx.h" 38 #include "opt_tx39xx.h" 39 #include "opt_kgdb.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/reboot.h> 44 45 #include <uvm/uvm_extern.h> 46 47 #include <machine/sysconf.h> 48 #include <machine/bootinfo.h> 49 #include <machine/bus.h> 50 #include <machine/bus_space_hpcmips.h> 51 #include <machine/platid.h> 52 #include <machine/platid_mask.h> 53 54 #include <dev/hpc/hpckbdvar.h> 55 56 #include <hpcmips/vr/vr.h> 57 #include <hpcmips/vr/vr_asm.h> 58 #include <hpcmips/vr/vrcpudef.h> 59 #include <hpcmips/vr/vripreg.h> 60 #include <hpcmips/vr/rtcreg.h> 61 62 #include "vrip_common.h" 63 #if NVRIP_COMMON > 0 64 #include <hpcmips/vr/vripvar.h> 65 #endif 66 67 #include "vrbcu.h" 68 #if NVRBCU > 0 69 #include <hpcmips/vr/bcuvar.h> 70 #endif 71 72 #include "vrdsu.h" 73 #if NVRDSU > 0 74 #include <hpcmips/vr/vrdsuvar.h> 75 #endif 76 77 #include "com.h" 78 #include "com_vrip.h" 79 #include "com_hpcio.h" 80 #if NCOM > 0 81 #include <sys/termios.h> 82 #include <sys/ttydefaults.h> 83 #include <dev/ic/comreg.h> 84 #include <dev/ic/comvar.h> 85 #if NCOM_VRIP > 0 86 #include <hpcmips/vr/siureg.h> 87 #include <hpcmips/vr/com_vripvar.h> 88 #endif 89 #if NCOM_HPCIO > 0 90 #include <hpcmips/dev/com_hpciovar.h> 91 #endif 92 #ifndef CONSPEED 93 #define CONSPEED TTYDEF_SPEED 94 #endif 95 #endif 96 97 #include "hpcfb.h" 98 #include "vrkiu.h" 99 #if (NVRKIU > 0) || (NHPCFB > 0) 100 #include <dev/wscons/wsdisplayvar.h> 101 #include <dev/rasops/rasops.h> 102 #endif 103 104 #if NHPCFB > 0 105 #include <dev/hpc/hpcfbvar.h> 106 #endif 107 108 #if NVRKIU > 0 109 #include <arch/hpcmips/vr/vrkiureg.h> 110 #include <arch/hpcmips/vr/vrkiuvar.h> 111 #endif 112 113 #ifdef DEBUG 114 #define STATIC 115 #else 116 #define STATIC static 117 #endif 118 119 /* 120 * This is a mask of bits to clear in the SR when we go to a 121 * given interrupt priority level. 122 */ 123 const u_int32_t __ipl_sr_bits_vr[_IPL_N] = { 124 0, /* IPL_NONE */ 125 126 MIPS_SOFT_INT_MASK_0, /* IPL_SOFT */ 127 128 MIPS_SOFT_INT_MASK_0, /* IPL_SOFTCLOCK */ 129 130 MIPS_SOFT_INT_MASK_0| 131 MIPS_SOFT_INT_MASK_1, /* IPL_SOFTNET */ 132 133 MIPS_SOFT_INT_MASK_0| 134 MIPS_SOFT_INT_MASK_1, /* IPL_SOFTSERIAL */ 135 136 MIPS_SOFT_INT_MASK_0| 137 MIPS_SOFT_INT_MASK_1| 138 MIPS_INT_MASK_0, /* IPL_BIO */ 139 140 MIPS_SOFT_INT_MASK_0| 141 MIPS_SOFT_INT_MASK_1| 142 MIPS_INT_MASK_0, /* IPL_NET */ 143 144 MIPS_SOFT_INT_MASK_0| 145 MIPS_SOFT_INT_MASK_1| 146 MIPS_INT_MASK_0, /* IPL_{TTY,SERIAL} */ 147 148 MIPS_SOFT_INT_MASK_0| 149 MIPS_SOFT_INT_MASK_1| 150 MIPS_INT_MASK_0| 151 MIPS_INT_MASK_1, /* IPL_{CLOCK,HIGH} */ 152 }; 153 154 #if defined(VR41XX) && defined(TX39XX) 155 #define VR_INTR vr_intr 156 #else 157 #define VR_INTR cpu_intr /* locore_mips3 directly call this */ 158 #endif 159 160 void vr_init(void); 161 void VR_INTR(u_int32_t, u_int32_t, u_int32_t, u_int32_t); 162 extern void vr_idle(void); 163 STATIC void vr_cons_init(void); 164 STATIC void vr_fb_init(caddr_t *); 165 STATIC void vr_mem_init(paddr_t); 166 STATIC void vr_find_dram(paddr_t, paddr_t); 167 STATIC void vr_reboot(int, char *); 168 169 /* 170 * CPU interrupt dispatch table (HwInt[0:3]) 171 */ 172 STATIC int vr_null_handler(void *, u_int32_t, u_int32_t); 173 STATIC int (*vr_intr_handler[4])(void *, u_int32_t, u_int32_t) = 174 { 175 vr_null_handler, 176 vr_null_handler, 177 vr_null_handler, 178 vr_null_handler 179 }; 180 STATIC void *vr_intr_arg[4]; 181 182 #if NCOM > 0 183 /* 184 * machine dependent serial console info 185 */ 186 static struct vr_com_platdep { 187 platid_mask_t *platidmask; 188 int (*attach)(bus_space_tag_t, int, int, int, tcflag_t, int); 189 int addr; 190 int freq; 191 } platdep_com_table[] = { 192 #if NCOM_HPCIO > 0 193 { 194 &platid_mask_MACH_NEC_MCR_SIGMARION2, 195 com_hpcio_cndb_attach, /* attach proc */ 196 0x0b600000, /* base address */ 197 COM_FREQ, /* frequency */ 198 }, 199 #endif 200 #if NCOM_VRIP > 0 201 #ifdef VR4102 202 { 203 &platid_mask_CPU_MIPS_VR_4102, 204 com_vrip_cndb_attach, /* attach proc */ 205 VR4102_SIU_ADDR, /* base address */ 206 VRCOM_FREQ, /* frequency */ 207 }, 208 #endif /* VR4102 */ 209 #ifdef VR4111 210 { 211 &platid_mask_CPU_MIPS_VR_4111, 212 com_vrip_cndb_attach, /* attach proc */ 213 VR4102_SIU_ADDR, /* base address */ 214 VRCOM_FREQ, /* frequency */ 215 }, 216 #endif /* VR4111 */ 217 #ifdef VR4121 218 { 219 &platid_mask_CPU_MIPS_VR_4121, 220 com_vrip_cndb_attach, /* attach proc */ 221 VR4102_SIU_ADDR, /* base address */ 222 VRCOM_FREQ, /* frequency */ 223 }, 224 #endif /* VR4121 */ 225 #ifdef VR4122 226 { 227 &platid_mask_CPU_MIPS_VR_4122, 228 com_vrip_cndb_attach, /* attach proc */ 229 VR4122_SIU_ADDR, /* base address */ 230 VRCOM_FREQ, /* frequency */ 231 }, 232 #endif /* VR4122 */ 233 #ifdef VR4131 234 { 235 &platid_mask_CPU_MIPS_VR_4122, 236 com_vrip_cndb_attach, /* attach proc */ 237 VR4122_SIU_ADDR, /* base address */ 238 VRCOM_FREQ, /* frequency */ 239 }, 240 #endif /* VR4131 */ 241 #ifdef SINGLE_VRIP_BASE 242 { 243 &platid_wild, 244 com_vrip_cndb_attach, /* attach proc */ 245 VRIP_SIU_ADDR, /* base address */ 246 VRCOM_FREQ, /* frequency */ 247 }, 248 #endif /* SINGLE_VRIP_BASE */ 249 #else /* NCOM_VRIP > 0 */ 250 /* dummy */ 251 { 252 &platid_wild, 253 NULL, /* attach proc */ 254 0, /* base address */ 255 0, /* frequency */ 256 }, 257 #endif /* NCOM_VRIP > 0 */ 258 }; 259 #endif /* NCOM > 0 */ 260 261 void 262 vr_init() 263 { 264 /* 265 * Platform Specific Function Hooks 266 */ 267 platform.cpu_idle = vr_idle; 268 platform.cpu_intr = VR_INTR; 269 platform.cons_init = vr_cons_init; 270 platform.fb_init = vr_fb_init; 271 platform.mem_init = vr_mem_init; 272 platform.reboot = vr_reboot; 273 274 #if NVRBCU > 0 275 sprintf(cpu_name, "NEC %s rev%d.%d %d.%03dMHz", 276 vrbcu_vrip_getcpuname(), 277 vrbcu_vrip_getcpumajor(), 278 vrbcu_vrip_getcpuminor(), 279 vrbcu_vrip_getcpuclock() / 1000000, 280 (vrbcu_vrip_getcpuclock() % 1000000) / 1000); 281 #else 282 sprintf(cpu_name, "NEC VR41xx"); 283 #endif 284 } 285 286 void 287 vr_mem_init(paddr_t kernend) 288 { 289 290 mem_clusters[0].start = 0; 291 mem_clusters[0].size = kernend; 292 mem_cluster_cnt = 1; 293 294 vr_find_dram(kernend, 0x02000000); 295 vr_find_dram(0x02000000, 0x04000000); 296 vr_find_dram(0x04000000, 0x06000000); 297 vr_find_dram(0x06000000, 0x08000000); 298 } 299 300 void 301 vr_find_dram(paddr_t addr, paddr_t end) 302 { 303 int n; 304 caddr_t page; 305 #ifdef NARLY_MEMORY_PROBE 306 int x, i; 307 #endif 308 309 #ifdef VR_FIND_DRAMLIM 310 if (VR_FIND_DRAMLIM < end) 311 end = VR_FIND_DRAMLIM; 312 #endif /* VR_FIND_DRAMLIM */ 313 n = mem_cluster_cnt; 314 for (; addr < end; addr += NBPG) { 315 316 page = (void *)MIPS_PHYS_TO_KSEG1(addr); 317 if (badaddr(page, 4)) 318 goto bad; 319 320 /* stop memory probing at first memory image */ 321 if (bcmp(page, (void *)MIPS_PHYS_TO_KSEG0(0), 128) == 0) 322 return; 323 324 *(volatile int *)(page+0) = 0xa5a5a5a5; 325 *(volatile int *)(page+4) = 0x5a5a5a5a; 326 wbflush(); 327 if (*(volatile int *)(page+0) != 0xa5a5a5a5) 328 goto bad; 329 330 *(volatile int *)(page+0) = 0x5a5a5a5a; 331 *(volatile int *)(page+4) = 0xa5a5a5a5; 332 wbflush(); 333 if (*(volatile int *)(page+0) != 0x5a5a5a5a) 334 goto bad; 335 336 #ifdef NARLY_MEMORY_PROBE 337 x = random(); 338 for (i = 0; i < NBPG; i += 4) 339 *(volatile int *)(page+i) = (x ^ i); 340 wbflush(); 341 for (i = 0; i < NBPG; i += 4) 342 if (*(volatile int *)(page+i) != (x ^ i)) 343 goto bad; 344 345 x = random(); 346 for (i = 0; i < NBPG; i += 4) 347 *(volatile int *)(page+i) = (x ^ i); 348 wbflush(); 349 for (i = 0; i < NBPG; i += 4) 350 if (*(volatile int *)(page+i) != (x ^ i)) 351 goto bad; 352 #endif /* NARLY_MEMORY_PROBE */ 353 354 if (!mem_clusters[n].size) 355 mem_clusters[n].start = addr; 356 mem_clusters[n].size += NBPG; 357 continue; 358 359 bad: 360 if (mem_clusters[n].size) 361 ++n; 362 continue; 363 } 364 if (mem_clusters[n].size) 365 ++n; 366 mem_cluster_cnt = n; 367 } 368 369 void 370 vr_fb_init(caddr_t *kernend) 371 { 372 /* Nothing to do */ 373 } 374 375 void 376 vr_cons_init() 377 { 378 #if NCOM > 0 || NHPCFB > 0 || NVRKIU > 0 379 bus_space_tag_t iot = hpcmips_system_bus_space(); 380 #endif 381 #if NCOM > 0 382 static struct vr_com_platdep *com_info; 383 #endif 384 385 #if NCOM > 0 386 com_info = platid_search(&platid, platdep_com_table, 387 sizeof(platdep_com_table)/sizeof(*platdep_com_table), 388 sizeof(*platdep_com_table)); 389 #ifdef KGDB 390 if (com_info->attach != NULL) { 391 /* if KGDB is defined, always use the serial port for KGDB */ 392 if ((*com_info->attach)(iot, com_info->addr, 9600, 393 com_info->freq, 394 (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8, 1)) { 395 printf("%s(%d): can't init kgdb's serial port", 396 __FILE__, __LINE__); 397 } 398 #else /* KGDB */ 399 if (com_info->attach != NULL && (bootinfo->bi_cnuse&BI_CNUSE_SERIAL)) { 400 /* Serial console */ 401 if ((*com_info->attach)(iot, com_info->addr, CONSPEED, 402 com_info->freq, 403 (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8, 0)) { 404 printf("%s(%d): can't init serial console", 405 __FILE__, __LINE__); 406 } else { 407 return; 408 } 409 } 410 #endif /* KGDB */ 411 #endif /* NCOM > 0 */ 412 413 #if NHPCFB > 0 414 if (hpcfb_cnattach(NULL)) { 415 printf("%s(%d): can't init fb console", __FILE__, __LINE__); 416 } else { 417 goto find_keyboard; 418 } 419 find_keyboard: 420 #endif /* NHPCFB > 0 */ 421 422 #if NVRKIU > 0 && VRIP_KIU_ADDR != VRIP_NO_ADDR 423 if (vrkiu_cnattach(iot, VRIP_KIU_ADDR)) { 424 printf("%s(%d): can't init vrkiu as console", 425 __FILE__, __LINE__); 426 } else { 427 return; 428 } 429 #endif /* NVRKIU > 0 && VRIP_KIU_ADDR != VRIP_NO_ADDR */ 430 } 431 432 void 433 vr_reboot(int howto, char *bootstr) 434 { 435 /* 436 * power down 437 */ 438 if ((howto & RB_POWERDOWN) == RB_POWERDOWN) { 439 printf("fake powerdown\n"); 440 __asm(__CONCAT(".word ",___STRING(VR_OPCODE_HIBERNATE))); 441 __asm("nop"); 442 __asm("nop"); 443 __asm("nop"); 444 __asm("nop"); 445 __asm("nop"); 446 __asm(".set reorder"); 447 /* not reach */ 448 vr_reboot(howto&~RB_HALT, bootstr); 449 } 450 /* 451 * halt 452 */ 453 if (howto & RB_HALT) { 454 #if NVRIP_COMMON > 0 455 _spllower(~MIPS_INT_MASK_0); 456 vrip_intr_suspend(); 457 #else 458 splhigh(); 459 #endif 460 __asm(".set noreorder"); 461 __asm(__CONCAT(".word ",___STRING(VR_OPCODE_SUSPEND))); 462 __asm("nop"); 463 __asm("nop"); 464 __asm("nop"); 465 __asm("nop"); 466 __asm("nop"); 467 __asm(".set reorder"); 468 #if NVRIP_COMMON > 0 469 vrip_intr_resume(); 470 #endif 471 } 472 /* 473 * reset 474 */ 475 #if NVRDSU 476 vrdsu_reset(); 477 #else 478 printf("%s(%d): There is no DSU.", __FILE__, __LINE__); 479 #endif 480 } 481 482 /* 483 * Handle interrupts. 484 */ 485 void 486 VR_INTR(u_int32_t status, u_int32_t cause, u_int32_t pc, u_int32_t ipending) 487 { 488 uvmexp.intrs++; 489 490 if (ipending & MIPS_INT_MASK_5) { 491 /* 492 * spl* uses MIPS_INT_MASK not MIPS3_INT_MASK. it causes 493 * INT5 interrupt. 494 */ 495 mips3_cp0_compare_write(mips3_cp0_count_read()); 496 } 497 498 /* for spllowersoftclock */ 499 _splset(((status & ~cause) & MIPS_HARD_INT_MASK) | MIPS_SR_INT_IE); 500 501 if (ipending & MIPS_INT_MASK_1) { 502 (*vr_intr_handler[1])(vr_intr_arg[1], pc, status); 503 504 cause &= ~MIPS_INT_MASK_1; 505 _splset(((status & ~cause) & MIPS_HARD_INT_MASK) 506 | MIPS_SR_INT_IE); 507 } 508 509 if (ipending & MIPS_INT_MASK_0) { 510 (*vr_intr_handler[0])(vr_intr_arg[0], pc, status); 511 512 cause &= ~MIPS_INT_MASK_0; 513 } 514 _splset(((status & ~cause) & MIPS_HARD_INT_MASK) | MIPS_SR_INT_IE); 515 516 softintr(ipending); 517 } 518 519 void * 520 vr_intr_establish(int line, int (*ih_fun)(void *, u_int32_t, u_int32_t), 521 void *ih_arg) 522 { 523 524 KDASSERT(vr_intr_handler[line] == vr_null_handler); 525 526 vr_intr_handler[line] = ih_fun; 527 vr_intr_arg[line] = ih_arg; 528 529 return ((void *)line); 530 } 531 532 void 533 vr_intr_disestablish(void *ih) 534 { 535 int line = (int)ih; 536 537 vr_intr_handler[line] = vr_null_handler; 538 vr_intr_arg[line] = NULL; 539 } 540 541 int 542 vr_null_handler(void *arg, u_int32_t pc, u_int32_t status) 543 { 544 545 printf("vr_null_handler\n"); 546 547 return (0); 548 } 549 550 /* 551 int x4181 = VR4181; 552 int x4101 = VR4101; 553 int x4102 = VR4102; 554 int x4111 = VR4111; 555 int x4121 = VR4121; 556 int x4122 = VR4122; 557 int xo4181 = ONLY_VR4181; 558 int xo4101 = ONLY_VR4101; 559 int xo4102 = ONLY_VR4102; 560 int xo4111_4121 = ONLY_VR4111_4121; 561 int g4101=VRGROUP_4101; 562 int g4102=VRGROUP_4102; 563 int g4181=VRGROUP_4181; 564 int g4102_4121=VRGROUP_4102_4121; 565 int g4111_4121=VRGROUP_4111_4121; 566 int g4102_4122=VRGROUP_4102_4122; 567 int g4111_4122=VRGROUP_4111_4122; 568 int single_vrip_base=SINGLE_VRIP_BASE; 569 int vrip_base_addr=VRIP_BASE_ADDR; 570 */ 571
Indexes created Tue Sep 30 11:09:46 GMT 2025