vr4181aiu.c revision 1.3.16.1
1 /* $NetBSD: vr4181aiu.c,v 1.3.16.1 2006/06/21 14:51:50 yamt Exp $ */ 2 3 /* 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Naoto Shimazaki of YOKOGAWA Electric Corporation. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: vr4181aiu.c,v 1.3.16.1 2006/06/21 14:51:50 yamt Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/conf.h> 44 #include <sys/device.h> 45 #include <sys/errno.h> 46 #include <sys/malloc.h> 47 #include <sys/proc.h> 48 #include <sys/systm.h> 49 50 #include <mips/cpuregs.h> 51 52 #include <machine/bus.h> 53 54 #include <hpcmips/vr/vripif.h> 55 #include <hpcmips/vr/vr4181aiureg.h> 56 #include <hpcmips/vr/vr4181dcureg.h> 57 58 #define INBUFLEN 1024 /* length in u_int16_t */ 59 #define INPUTLEN 1000 60 #define SAMPLEFREQ 1000 61 #define PICKUPFREQ 100 62 #define PICKUPCOUNT (SAMPLEFREQ / PICKUPFREQ) 63 64 #define ST_BUSY 0x01 65 #define ST_OVERRUN 0x02 66 67 #define INBUF_MASK 0x3ff /* 2Kbyte */ 68 #define INBUF_RAW_SIZE (INBUFLEN * 4 + (INBUF_MASK + 1)) 69 70 #ifdef VR4181AIU_DEBUG 71 int vr4181aiu_debug = 0; 72 #define DPRINTF(x) if (vr4181aiu_debug) printf x 73 #else 74 #define DPRINTF(x) 75 #endif 76 77 78 struct vr4181aiu_softc { 79 struct device sc_dev; 80 bus_space_tag_t sc_iot; 81 bus_space_handle_t sc_dcu1_ioh; 82 bus_space_handle_t sc_dcu2_ioh; 83 bus_space_handle_t sc_aiu_ioh; 84 u_int16_t *sc_inbuf_head; 85 u_int16_t *sc_inbuf_tail; 86 u_int16_t *sc_inbuf_which; 87 u_int16_t *sc_inbuf1; 88 u_int16_t *sc_inbuf2; 89 u_int16_t *sc_inbuf_raw; 90 int sc_status; 91 }; 92 93 static int vr4181aiu_match(struct device *, struct cfdata *, void *); 94 static void vr4181aiu_attach(struct device *, struct device *, void *); 95 static int vr4181aiu_intr(void *); 96 97 extern struct cfdriver vr4181aiu_cd; 98 99 CFATTACH_DECL(vr4181aiu, sizeof(struct vr4181aiu_softc), 100 vr4181aiu_match, vr4181aiu_attach, NULL, NULL); 101 102 dev_type_open(vr4181aiuopen); 103 dev_type_close(vr4181aiuclose); 104 dev_type_read(vr4181aiuread); 105 dev_type_write(vr4181aiuwrite); 106 107 const struct cdevsw vr4181aiu_cdevsw = { 108 vr4181aiuopen, vr4181aiuclose, vr4181aiuread, vr4181aiuwrite, noioctl, 109 nostop, notty, nopoll, nommap, nokqfilter, 110 }; 111 112 static int 113 vr4181aiu_match(struct device *parent, struct cfdata *cf, void *aux) 114 { 115 return 1; 116 } 117 118 static void 119 vr4181aiu_init_inbuf(struct vr4181aiu_softc *sc) 120 { 121 /* 122 * XXXXXXXXXXXXXXXXX 123 * 124 * this is just a quick and dirty hack to locate the buffer 125 * in KSEG0 space. the only reason is that i want the physical 126 * address of the buffer. 127 * 128 * bus_dma framework should be used. 129 */ 130 static char inbufbase[INBUF_RAW_SIZE]; 131 132 sc->sc_inbuf_raw = (u_int16_t *) inbufbase; 133 134 sc->sc_inbuf1 = (u_int16_t *) ((((u_int32_t) sc->sc_inbuf_raw) 135 + INBUF_MASK) 136 & ~INBUF_MASK); 137 sc->sc_inbuf2 = sc->sc_inbuf1 + INBUFLEN; 138 } 139 140 static void 141 vr4181aiu_disable(struct vr4181aiu_softc *sc) 142 { 143 /* irq clear */ 144 bus_space_write_2(sc->sc_iot, sc->sc_dcu2_ioh, 145 DCU_DMAITRQ_REG_W, DCU_MICEOP); 146 bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh, 147 VR4181AIU_INT_REG_W, 148 VR4181AIU_MIDLEINTR 149 | VR4181AIU_MSTINTR 150 | VR4181AIU_SIDLEINTR); 151 152 /* disable microphone */ 153 bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh, 154 VR4181AIU_SEQ_REG_W, 0); 155 156 /* disable ADC */ 157 bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh, 158 VR4181AIU_MCNT_REG_W, 0); 159 160 /* disable DMA */ 161 bus_space_write_2(sc->sc_iot, sc->sc_dcu1_ioh, 162 DCU_AIUDMAMSK_REG_W, 0); 163 bus_space_write_2(sc->sc_iot, sc->sc_dcu2_ioh, 164 DCU_DMAITMK_REG_W, 0); 165 166 sc->sc_status = 0; 167 } 168 169 static void 170 vr4181aiu_attach(struct device *parent, struct device *self, void *aux) 171 { 172 struct vrip_attach_args *va = aux; 173 struct vr4181aiu_softc *sc = (void *) self; 174 175 vr4181aiu_init_inbuf(sc); 176 memset(sc->sc_inbuf1, 0x55, INBUFLEN * 2); 177 memset(sc->sc_inbuf2, 0xaa, INBUFLEN * 2); 178 179 sc->sc_status = 0; 180 sc->sc_iot = va->va_iot; 181 182 if (bus_space_map(sc->sc_iot, 183 VR4181AIU_DCU1_BASE, VR4181AIU_DCU1_SIZE, 184 0, &sc->sc_dcu1_ioh)) 185 goto out_dcu1; 186 if (bus_space_map(sc->sc_iot, 187 VR4181AIU_DCU2_BASE, VR4181AIU_DCU2_SIZE, 188 0, &sc->sc_dcu2_ioh)) 189 goto out_dcu2; 190 if (bus_space_map(sc->sc_iot, 191 VR4181AIU_AIU_BASE, VR4181AIU_AIU_SIZE, 192 0, &sc->sc_aiu_ioh)) 193 goto out_aiu; 194 195 /* 196 * reset AIU 197 */ 198 bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh, 199 VR4181AIU_SEQ_REG_W, VR4181AIU_AIURST); 200 bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh, 201 VR4181AIU_SEQ_REG_W, 0); 202 203 /* 204 * set sample rate (1kHz fixed) 205 * XXXX 206 * assume to PCLK is 32.768MHz 207 */ 208 bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh, 209 VR4181AIU_MCNVC_END, 210 32768000 / SAMPLEFREQ); 211 212 /* 213 * XXXX 214 * assume to PCLK is 32.768MHz 215 * DAVREF_SETUP = 5usec * PCLK = 163.84 216 */ 217 bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh, 218 VR4181AIU_DAVREF_SETUP_REG_W, 164); 219 220 vr4181aiu_disable(sc); 221 222 if (vrip_intr_establish(va->va_vc, va->va_unit, 0, 223 IPL_BIO, vr4181aiu_intr, sc) == NULL) { 224 printf("%s: can't establish interrupt\n", 225 sc->sc_dev.dv_xname); 226 return; 227 } 228 229 printf("\n"); 230 return; 231 232 out_aiu: 233 bus_space_unmap(sc->sc_iot, sc->sc_dcu2_ioh, VR4181AIU_DCU2_SIZE); 234 out_dcu2: 235 bus_space_unmap(sc->sc_iot, sc->sc_dcu1_ioh, VR4181AIU_DCU1_SIZE); 236 out_dcu1: 237 printf(": can't map i/o space\n"); 238 } 239 240 int 241 vr4181aiuopen(dev_t dev, int flag, int mode, struct lwp *l) 242 { 243 struct vr4181aiu_softc *sc; 244 245 if ((sc = device_lookup(&vr4181aiu_cd, minor(dev))) == NULL) 246 return ENXIO; 247 248 if (sc->sc_status & ST_BUSY) 249 return EBUSY; 250 251 sc->sc_inbuf_head = sc->sc_inbuf_tail 252 = sc->sc_inbuf_which = sc->sc_inbuf1; 253 sc->sc_status &= ~ST_OVERRUN; 254 255 /* setup DMA */ 256 /* reset */ 257 bus_space_write_2(sc->sc_iot, sc->sc_dcu1_ioh, 258 DCU_DMARST_REG_W, 0); 259 bus_space_write_2(sc->sc_iot, sc->sc_dcu1_ioh, 260 DCU_DMARST_REG_W, DCU_DMARST); 261 /* dest1 <- sc_inbuf1 */ 262 bus_space_write_2(sc->sc_iot, sc->sc_dcu1_ioh, 263 DCU_MICDEST1REG1_W, 264 MIPS_KSEG0_TO_PHYS(sc->sc_inbuf1) & 0xffff); 265 bus_space_write_2(sc->sc_iot, sc->sc_dcu1_ioh, 266 DCU_MICDEST1REG2_W, 267 MIPS_KSEG0_TO_PHYS(sc->sc_inbuf1) >> 16); 268 /* dest2 <- sc_inbuf2 */ 269 bus_space_write_2(sc->sc_iot, sc->sc_dcu1_ioh, 270 DCU_MICDEST2REG1_W, 271 MIPS_KSEG0_TO_PHYS(sc->sc_inbuf2) & 0xffff); 272 bus_space_write_2(sc->sc_iot, sc->sc_dcu1_ioh, 273 DCU_MICDEST2REG2_W, 274 MIPS_KSEG0_TO_PHYS(sc->sc_inbuf2) >> 16); 275 /* record length <- INPUTLEN */ 276 bus_space_write_2(sc->sc_iot, sc->sc_dcu2_ioh, 277 DCU_MICRCLEN_REG_W, INPUTLEN); 278 /* config <- auto load */ 279 bus_space_write_2(sc->sc_iot, sc->sc_dcu2_ioh, 280 DCU_MICDMACFG_REG_W, DCU_MICLOAD); 281 /* irq <- irq clear */ 282 bus_space_write_2(sc->sc_iot, sc->sc_dcu2_ioh, 283 DCU_DMAITRQ_REG_W, DCU_MICEOP); 284 /* control <- INC */ 285 bus_space_write_2(sc->sc_iot, sc->sc_dcu2_ioh, 286 DCU_DMACTL_REG_W, DCU_MICCNT_INC); 287 /* irq mask <- microphone end of process */ 288 bus_space_write_2(sc->sc_iot, sc->sc_dcu2_ioh, 289 DCU_DMAITMK_REG_W, DCU_MICEOP_ENABLE); 290 291 /* enable DMA */ 292 bus_space_write_2(sc->sc_iot, sc->sc_dcu1_ioh, 293 DCU_AIUDMAMSK_REG_W, DCU_ENABLE_MIC); 294 295 /* enable ADC */ 296 bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh, 297 VR4181AIU_MCNT_REG_W, VR4181AIU_ADENAIU); 298 299 /* enable microphone */ 300 bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh, 301 VR4181AIU_SEQ_REG_W, VR4181AIU_AIUMEN); 302 303 sc->sc_status |= ST_BUSY; 304 305 return 0; 306 } 307 308 int 309 vr4181aiuclose(dev_t dev, int flag, int mode, struct lwp *l) 310 { 311 vr4181aiu_disable(device_lookup(&vr4181aiu_cd, minor(dev))); 312 return 0; 313 } 314 315 int 316 vr4181aiuread(dev_t dev, struct uio *uio, int flag) 317 { 318 struct vr4181aiu_softc *sc; 319 int s; 320 u_int16_t *fence; 321 int avail; 322 int count; 323 u_int8_t tmp[INPUTLEN / PICKUPCOUNT]; 324 u_int16_t *src; 325 u_int8_t *dst; 326 327 sc = device_lookup(&vr4181aiu_cd, minor(dev)); 328 329 src = sc->sc_inbuf_tail; 330 s = splbio(); 331 if (src == sc->sc_inbuf_head) { 332 /* wait for DMA to complete writing */ 333 tsleep(sc, PRIBIO, "aiu read", 0); 334 /* now sc_inbuf_head points alternate buffer */ 335 } 336 splx(s); 337 338 fence = sc->sc_inbuf_which == sc->sc_inbuf1 339 ? &sc->sc_inbuf1[INPUTLEN] 340 : &sc->sc_inbuf2[INPUTLEN]; 341 avail = (fence - src) / PICKUPCOUNT; 342 count = min(avail, uio->uio_resid); 343 dst = tmp; 344 while (count > 0) { 345 *dst++ = (u_int8_t) (*src >> 2); 346 src += PICKUPCOUNT; 347 count--; 348 } 349 350 if (src < fence) { 351 sc->sc_inbuf_tail = src; 352 } else { 353 /* alter the buffer */ 354 sc->sc_inbuf_tail 355 = sc->sc_inbuf_which 356 = sc->sc_inbuf_which == sc->sc_inbuf1 357 ? sc->sc_inbuf2 : sc->sc_inbuf1; 358 } 359 360 return uiomove(tmp, dst - tmp, uio); 361 } 362 363 int 364 vr4181aiuwrite(dev_t dev, struct uio *uio, int flag) 365 { 366 return 0; 367 } 368 369 /* 370 * interrupt handler 371 */ 372 static int 373 vr4181aiu_intr(void *arg) 374 { 375 struct vr4181aiu_softc *sc = arg; 376 377 if (!(sc->sc_status & ST_BUSY)) { 378 printf("vr4181aiu_intr: stray interrupt\n"); 379 vr4181aiu_disable(sc); 380 return 0; 381 } 382 383 /* irq clear */ 384 bus_space_write_2(sc->sc_iot, sc->sc_dcu2_ioh, 385 DCU_DMAITRQ_REG_W, DCU_MICEOP); 386 387 if (sc->sc_inbuf_head == sc->sc_inbuf1) { 388 if (sc->sc_inbuf_tail != sc->sc_inbuf1) 389 sc->sc_status |= ST_OVERRUN; 390 sc->sc_inbuf_head = sc->sc_inbuf2; 391 } else { 392 if (sc->sc_inbuf_tail != sc->sc_inbuf2) 393 sc->sc_status |= ST_OVERRUN; 394 sc->sc_inbuf_head = sc->sc_inbuf1; 395 } 396 397 if (sc->sc_status & ST_OVERRUN) { 398 printf("vr4181aiu_intr: overrun\n"); 399 } 400 401 DPRINTF(("vr4181aiu_intr: sc_inbuf1 = %04x, sc_inbuf2 = %04x\n", 402 sc->sc_inbuf1[0], sc->sc_inbuf2[0])); 403 404 wakeup(sc); 405 406 return 0; 407 } 408
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