vr4181aiu.c revision 1.5
1 /* $NetBSD: vr4181aiu.c,v 1.5 2008/04/28 20:23:22 martin Exp $ */ 2 3 /* 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Naoto Shimazaki of YOKOGAWA Electric Corporation. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: vr4181aiu.c,v 1.5 2008/04/28 20:23:22 martin Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/conf.h> 37 #include <sys/device.h> 38 #include <sys/errno.h> 39 #include <sys/malloc.h> 40 #include <sys/proc.h> 41 #include <sys/systm.h> 42 43 #include <mips/cpuregs.h> 44 45 #include <machine/bus.h> 46 47 #include <hpcmips/vr/vripif.h> 48 #include <hpcmips/vr/vr4181aiureg.h> 49 #include <hpcmips/vr/vr4181dcureg.h> 50 51 #define INBUFLEN 1024 /* length in u_int16_t */ 52 #define INPUTLEN 1000 53 #define SAMPLEFREQ 1000 54 #define PICKUPFREQ 100 55 #define PICKUPCOUNT (SAMPLEFREQ / PICKUPFREQ) 56 57 #define ST_BUSY 0x01 58 #define ST_OVERRUN 0x02 59 60 #define INBUF_MASK 0x3ff /* 2Kbyte */ 61 #define INBUF_RAW_SIZE (INBUFLEN * 4 + (INBUF_MASK + 1)) 62 63 #ifdef VR4181AIU_DEBUG 64 int vr4181aiu_debug = 0; 65 #define DPRINTF(x) if (vr4181aiu_debug) printf x 66 #else 67 #define DPRINTF(x) 68 #endif 69 70 71 struct vr4181aiu_softc { 72 struct device sc_dev; 73 bus_space_tag_t sc_iot; 74 bus_space_handle_t sc_dcu1_ioh; 75 bus_space_handle_t sc_dcu2_ioh; 76 bus_space_handle_t sc_aiu_ioh; 77 u_int16_t *sc_inbuf_head; 78 u_int16_t *sc_inbuf_tail; 79 u_int16_t *sc_inbuf_which; 80 u_int16_t *sc_inbuf1; 81 u_int16_t *sc_inbuf2; 82 u_int16_t *sc_inbuf_raw; 83 int sc_status; 84 }; 85 86 static int vr4181aiu_match(struct device *, struct cfdata *, void *); 87 static void vr4181aiu_attach(struct device *, struct device *, void *); 88 static int vr4181aiu_intr(void *); 89 90 extern struct cfdriver vr4181aiu_cd; 91 92 CFATTACH_DECL(vr4181aiu, sizeof(struct vr4181aiu_softc), 93 vr4181aiu_match, vr4181aiu_attach, NULL, NULL); 94 95 dev_type_open(vr4181aiuopen); 96 dev_type_close(vr4181aiuclose); 97 dev_type_read(vr4181aiuread); 98 dev_type_write(vr4181aiuwrite); 99 100 const struct cdevsw vr4181aiu_cdevsw = { 101 vr4181aiuopen, vr4181aiuclose, vr4181aiuread, vr4181aiuwrite, noioctl, 102 nostop, notty, nopoll, nommap, nokqfilter, 103 }; 104 105 static int 106 vr4181aiu_match(struct device *parent, struct cfdata *cf, void *aux) 107 { 108 return 1; 109 } 110 111 static void 112 vr4181aiu_init_inbuf(struct vr4181aiu_softc *sc) 113 { 114 /* 115 * XXXXXXXXXXXXXXXXX 116 * 117 * this is just a quick and dirty hack to locate the buffer 118 * in KSEG0 space. the only reason is that i want the physical 119 * address of the buffer. 120 * 121 * bus_dma framework should be used. 122 */ 123 static char inbufbase[INBUF_RAW_SIZE]; 124 125 sc->sc_inbuf_raw = (u_int16_t *) inbufbase; 126 127 sc->sc_inbuf1 = (u_int16_t *) ((((u_int32_t) sc->sc_inbuf_raw) 128 + INBUF_MASK) 129 & ~INBUF_MASK); 130 sc->sc_inbuf2 = sc->sc_inbuf1 + INBUFLEN; 131 } 132 133 static void 134 vr4181aiu_disable(struct vr4181aiu_softc *sc) 135 { 136 /* irq clear */ 137 bus_space_write_2(sc->sc_iot, sc->sc_dcu2_ioh, 138 DCU_DMAITRQ_REG_W, DCU_MICEOP); 139 bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh, 140 VR4181AIU_INT_REG_W, 141 VR4181AIU_MIDLEINTR 142 | VR4181AIU_MSTINTR 143 | VR4181AIU_SIDLEINTR); 144 145 /* disable microphone */ 146 bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh, 147 VR4181AIU_SEQ_REG_W, 0); 148 149 /* disable ADC */ 150 bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh, 151 VR4181AIU_MCNT_REG_W, 0); 152 153 /* disable DMA */ 154 bus_space_write_2(sc->sc_iot, sc->sc_dcu1_ioh, 155 DCU_AIUDMAMSK_REG_W, 0); 156 bus_space_write_2(sc->sc_iot, sc->sc_dcu2_ioh, 157 DCU_DMAITMK_REG_W, 0); 158 159 sc->sc_status = 0; 160 } 161 162 static void 163 vr4181aiu_attach(struct device *parent, struct device *self, void *aux) 164 { 165 struct vrip_attach_args *va = aux; 166 struct vr4181aiu_softc *sc = (void *) self; 167 168 vr4181aiu_init_inbuf(sc); 169 memset(sc->sc_inbuf1, 0x55, INBUFLEN * 2); 170 memset(sc->sc_inbuf2, 0xaa, INBUFLEN * 2); 171 172 sc->sc_status = 0; 173 sc->sc_iot = va->va_iot; 174 175 if (bus_space_map(sc->sc_iot, 176 VR4181AIU_DCU1_BASE, VR4181AIU_DCU1_SIZE, 177 0, &sc->sc_dcu1_ioh)) 178 goto out_dcu1; 179 if (bus_space_map(sc->sc_iot, 180 VR4181AIU_DCU2_BASE, VR4181AIU_DCU2_SIZE, 181 0, &sc->sc_dcu2_ioh)) 182 goto out_dcu2; 183 if (bus_space_map(sc->sc_iot, 184 VR4181AIU_AIU_BASE, VR4181AIU_AIU_SIZE, 185 0, &sc->sc_aiu_ioh)) 186 goto out_aiu; 187 188 /* 189 * reset AIU 190 */ 191 bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh, 192 VR4181AIU_SEQ_REG_W, VR4181AIU_AIURST); 193 bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh, 194 VR4181AIU_SEQ_REG_W, 0); 195 196 /* 197 * set sample rate (1kHz fixed) 198 * XXXX 199 * assume to PCLK is 32.768MHz 200 */ 201 bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh, 202 VR4181AIU_MCNVC_END, 203 32768000 / SAMPLEFREQ); 204 205 /* 206 * XXXX 207 * assume to PCLK is 32.768MHz 208 * DAVREF_SETUP = 5usec * PCLK = 163.84 209 */ 210 bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh, 211 VR4181AIU_DAVREF_SETUP_REG_W, 164); 212 213 vr4181aiu_disable(sc); 214 215 if (vrip_intr_establish(va->va_vc, va->va_unit, 0, 216 IPL_BIO, vr4181aiu_intr, sc) == NULL) { 217 printf("%s: can't establish interrupt\n", 218 sc->sc_dev.dv_xname); 219 return; 220 } 221 222 printf("\n"); 223 return; 224 225 out_aiu: 226 bus_space_unmap(sc->sc_iot, sc->sc_dcu2_ioh, VR4181AIU_DCU2_SIZE); 227 out_dcu2: 228 bus_space_unmap(sc->sc_iot, sc->sc_dcu1_ioh, VR4181AIU_DCU1_SIZE); 229 out_dcu1: 230 printf(": can't map i/o space\n"); 231 } 232 233 int 234 vr4181aiuopen(dev_t dev, int flag, int mode, struct lwp *l) 235 { 236 struct vr4181aiu_softc *sc; 237 238 if ((sc = device_lookup(&vr4181aiu_cd, minor(dev))) == NULL) 239 return ENXIO; 240 241 if (sc->sc_status & ST_BUSY) 242 return EBUSY; 243 244 sc->sc_inbuf_head = sc->sc_inbuf_tail 245 = sc->sc_inbuf_which = sc->sc_inbuf1; 246 sc->sc_status &= ~ST_OVERRUN; 247 248 /* setup DMA */ 249 /* reset */ 250 bus_space_write_2(sc->sc_iot, sc->sc_dcu1_ioh, 251 DCU_DMARST_REG_W, 0); 252 bus_space_write_2(sc->sc_iot, sc->sc_dcu1_ioh, 253 DCU_DMARST_REG_W, DCU_DMARST); 254 /* dest1 <- sc_inbuf1 */ 255 bus_space_write_2(sc->sc_iot, sc->sc_dcu1_ioh, 256 DCU_MICDEST1REG1_W, 257 MIPS_KSEG0_TO_PHYS(sc->sc_inbuf1) & 0xffff); 258 bus_space_write_2(sc->sc_iot, sc->sc_dcu1_ioh, 259 DCU_MICDEST1REG2_W, 260 MIPS_KSEG0_TO_PHYS(sc->sc_inbuf1) >> 16); 261 /* dest2 <- sc_inbuf2 */ 262 bus_space_write_2(sc->sc_iot, sc->sc_dcu1_ioh, 263 DCU_MICDEST2REG1_W, 264 MIPS_KSEG0_TO_PHYS(sc->sc_inbuf2) & 0xffff); 265 bus_space_write_2(sc->sc_iot, sc->sc_dcu1_ioh, 266 DCU_MICDEST2REG2_W, 267 MIPS_KSEG0_TO_PHYS(sc->sc_inbuf2) >> 16); 268 /* record length <- INPUTLEN */ 269 bus_space_write_2(sc->sc_iot, sc->sc_dcu2_ioh, 270 DCU_MICRCLEN_REG_W, INPUTLEN); 271 /* config <- auto load */ 272 bus_space_write_2(sc->sc_iot, sc->sc_dcu2_ioh, 273 DCU_MICDMACFG_REG_W, DCU_MICLOAD); 274 /* irq <- irq clear */ 275 bus_space_write_2(sc->sc_iot, sc->sc_dcu2_ioh, 276 DCU_DMAITRQ_REG_W, DCU_MICEOP); 277 /* control <- INC */ 278 bus_space_write_2(sc->sc_iot, sc->sc_dcu2_ioh, 279 DCU_DMACTL_REG_W, DCU_MICCNT_INC); 280 /* irq mask <- microphone end of process */ 281 bus_space_write_2(sc->sc_iot, sc->sc_dcu2_ioh, 282 DCU_DMAITMK_REG_W, DCU_MICEOP_ENABLE); 283 284 /* enable DMA */ 285 bus_space_write_2(sc->sc_iot, sc->sc_dcu1_ioh, 286 DCU_AIUDMAMSK_REG_W, DCU_ENABLE_MIC); 287 288 /* enable ADC */ 289 bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh, 290 VR4181AIU_MCNT_REG_W, VR4181AIU_ADENAIU); 291 292 /* enable microphone */ 293 bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh, 294 VR4181AIU_SEQ_REG_W, VR4181AIU_AIUMEN); 295 296 sc->sc_status |= ST_BUSY; 297 298 return 0; 299 } 300 301 int 302 vr4181aiuclose(dev_t dev, int flag, int mode, struct lwp *l) 303 { 304 vr4181aiu_disable(device_lookup(&vr4181aiu_cd, minor(dev))); 305 return 0; 306 } 307 308 int 309 vr4181aiuread(dev_t dev, struct uio *uio, int flag) 310 { 311 struct vr4181aiu_softc *sc; 312 int s; 313 u_int16_t *fence; 314 int avail; 315 int count; 316 u_int8_t tmp[INPUTLEN / PICKUPCOUNT]; 317 u_int16_t *src; 318 u_int8_t *dst; 319 320 sc = device_lookup(&vr4181aiu_cd, minor(dev)); 321 322 src = sc->sc_inbuf_tail; 323 s = splbio(); 324 if (src == sc->sc_inbuf_head) { 325 /* wait for DMA to complete writing */ 326 tsleep(sc, PRIBIO, "aiu read", 0); 327 /* now sc_inbuf_head points alternate buffer */ 328 } 329 splx(s); 330 331 fence = sc->sc_inbuf_which == sc->sc_inbuf1 332 ? &sc->sc_inbuf1[INPUTLEN] 333 : &sc->sc_inbuf2[INPUTLEN]; 334 avail = (fence - src) / PICKUPCOUNT; 335 count = min(avail, uio->uio_resid); 336 dst = tmp; 337 while (count > 0) { 338 *dst++ = (u_int8_t) (*src >> 2); 339 src += PICKUPCOUNT; 340 count--; 341 } 342 343 if (src < fence) { 344 sc->sc_inbuf_tail = src; 345 } else { 346 /* alter the buffer */ 347 sc->sc_inbuf_tail 348 = sc->sc_inbuf_which 349 = sc->sc_inbuf_which == sc->sc_inbuf1 350 ? sc->sc_inbuf2 : sc->sc_inbuf1; 351 } 352 353 return uiomove(tmp, dst - tmp, uio); 354 } 355 356 int 357 vr4181aiuwrite(dev_t dev, struct uio *uio, int flag) 358 { 359 return 0; 360 } 361 362 /* 363 * interrupt handler 364 */ 365 static int 366 vr4181aiu_intr(void *arg) 367 { 368 struct vr4181aiu_softc *sc = arg; 369 370 if (!(sc->sc_status & ST_BUSY)) { 371 printf("vr4181aiu_intr: stray interrupt\n"); 372 vr4181aiu_disable(sc); 373 return 0; 374 } 375 376 /* irq clear */ 377 bus_space_write_2(sc->sc_iot, sc->sc_dcu2_ioh, 378 DCU_DMAITRQ_REG_W, DCU_MICEOP); 379 380 if (sc->sc_inbuf_head == sc->sc_inbuf1) { 381 if (sc->sc_inbuf_tail != sc->sc_inbuf1) 382 sc->sc_status |= ST_OVERRUN; 383 sc->sc_inbuf_head = sc->sc_inbuf2; 384 } else { 385 if (sc->sc_inbuf_tail != sc->sc_inbuf2) 386 sc->sc_status |= ST_OVERRUN; 387 sc->sc_inbuf_head = sc->sc_inbuf1; 388 } 389 390 if (sc->sc_status & ST_OVERRUN) { 391 printf("vr4181aiu_intr: overrun\n"); 392 } 393 394 DPRINTF(("vr4181aiu_intr: sc_inbuf1 = %04x, sc_inbuf2 = %04x\n", 395 sc->sc_inbuf1[0], sc->sc_inbuf2[0])); 396 397 wakeup(sc); 398 399 return 0; 400 } 401
Indexes created Sat Oct 25 16:10:12 GMT 2025