vr4181aiu.c revision 1.7.8.1
1 /* $NetBSD: vr4181aiu.c,v 1.7.8.1 2012/10/30 17:19:45 yamt Exp $ */ 2 3 /* 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Naoto Shimazaki of YOKOGAWA Electric Corporation. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: vr4181aiu.c,v 1.7.8.1 2012/10/30 17:19:45 yamt Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/conf.h> 37 #include <sys/device.h> 38 #include <sys/errno.h> 39 #include <sys/malloc.h> 40 #include <sys/proc.h> 41 #include <sys/systm.h> 42 43 #include <mips/cpuregs.h> 44 45 #include <machine/bus.h> 46 47 #include <hpcmips/vr/vripif.h> 48 #include <hpcmips/vr/vr4181aiureg.h> 49 #include <hpcmips/vr/vr4181dcureg.h> 50 51 #define INBUFLEN 1024 /* length in u_int16_t */ 52 #define INPUTLEN 1000 53 #define SAMPLEFREQ 1000 54 #define PICKUPFREQ 100 55 #define PICKUPCOUNT (SAMPLEFREQ / PICKUPFREQ) 56 57 #define ST_BUSY 0x01 58 #define ST_OVERRUN 0x02 59 60 #define INBUF_MASK 0x3ff /* 2Kbyte */ 61 #define INBUF_RAW_SIZE (INBUFLEN * 4 + (INBUF_MASK + 1)) 62 63 #ifdef VR4181AIU_DEBUG 64 int vr4181aiu_debug = 0; 65 #define DPRINTF(x) if (vr4181aiu_debug) printf x 66 #else 67 #define DPRINTF(x) 68 #endif 69 70 71 struct vr4181aiu_softc { 72 bus_space_tag_t sc_iot; 73 bus_space_handle_t sc_dcu1_ioh; 74 bus_space_handle_t sc_dcu2_ioh; 75 bus_space_handle_t sc_aiu_ioh; 76 u_int16_t *sc_inbuf_head; 77 u_int16_t *sc_inbuf_tail; 78 u_int16_t *sc_inbuf_which; 79 u_int16_t *sc_inbuf1; 80 u_int16_t *sc_inbuf2; 81 u_int16_t *sc_inbuf_raw; 82 int sc_status; 83 }; 84 85 static int vr4181aiu_match(device_t, cfdata_t, void *); 86 static void vr4181aiu_attach(device_t, device_t, void *); 87 static int vr4181aiu_intr(void *); 88 89 extern struct cfdriver vr4181aiu_cd; 90 91 CFATTACH_DECL_NEW(vr4181aiu, sizeof(struct vr4181aiu_softc), 92 vr4181aiu_match, vr4181aiu_attach, NULL, NULL); 93 94 dev_type_open(vr4181aiuopen); 95 dev_type_close(vr4181aiuclose); 96 dev_type_read(vr4181aiuread); 97 dev_type_write(vr4181aiuwrite); 98 99 const struct cdevsw vr4181aiu_cdevsw = { 100 vr4181aiuopen, vr4181aiuclose, vr4181aiuread, vr4181aiuwrite, noioctl, 101 nostop, notty, nopoll, nommap, nokqfilter, 102 }; 103 104 static int 105 vr4181aiu_match(device_t parent, cfdata_t cf, void *aux) 106 { 107 return 1; 108 } 109 110 static void 111 vr4181aiu_init_inbuf(struct vr4181aiu_softc *sc) 112 { 113 /* 114 * XXXXXXXXXXXXXXXXX 115 * 116 * this is just a quick and dirty hack to locate the buffer 117 * in KSEG0 space. the only reason is that i want the physical 118 * address of the buffer. 119 * 120 * bus_dma framework should be used. 121 */ 122 static char inbufbase[INBUF_RAW_SIZE]; 123 124 sc->sc_inbuf_raw = (u_int16_t *) inbufbase; 125 126 sc->sc_inbuf1 = (u_int16_t *) ((((u_int32_t) sc->sc_inbuf_raw) 127 + INBUF_MASK) 128 & ~INBUF_MASK); 129 sc->sc_inbuf2 = sc->sc_inbuf1 + INBUFLEN; 130 } 131 132 static void 133 vr4181aiu_disable(struct vr4181aiu_softc *sc) 134 { 135 /* irq clear */ 136 bus_space_write_2(sc->sc_iot, sc->sc_dcu2_ioh, 137 DCU_DMAITRQ_REG_W, DCU_MICEOP); 138 bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh, 139 VR4181AIU_INT_REG_W, 140 VR4181AIU_MIDLEINTR 141 | VR4181AIU_MSTINTR 142 | VR4181AIU_SIDLEINTR); 143 144 /* disable microphone */ 145 bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh, 146 VR4181AIU_SEQ_REG_W, 0); 147 148 /* disable ADC */ 149 bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh, 150 VR4181AIU_MCNT_REG_W, 0); 151 152 /* disable DMA */ 153 bus_space_write_2(sc->sc_iot, sc->sc_dcu1_ioh, 154 DCU_AIUDMAMSK_REG_W, 0); 155 bus_space_write_2(sc->sc_iot, sc->sc_dcu2_ioh, 156 DCU_DMAITMK_REG_W, 0); 157 158 sc->sc_status = 0; 159 } 160 161 static void 162 vr4181aiu_attach(device_t parent, device_t self, void *aux) 163 { 164 struct vrip_attach_args *va = aux; 165 struct vr4181aiu_softc *sc = device_private(self); 166 167 vr4181aiu_init_inbuf(sc); 168 memset(sc->sc_inbuf1, 0x55, INBUFLEN * 2); 169 memset(sc->sc_inbuf2, 0xaa, INBUFLEN * 2); 170 171 sc->sc_status = 0; 172 sc->sc_iot = va->va_iot; 173 174 if (bus_space_map(sc->sc_iot, 175 VR4181AIU_DCU1_BASE, VR4181AIU_DCU1_SIZE, 176 0, &sc->sc_dcu1_ioh)) 177 goto out_dcu1; 178 if (bus_space_map(sc->sc_iot, 179 VR4181AIU_DCU2_BASE, VR4181AIU_DCU2_SIZE, 180 0, &sc->sc_dcu2_ioh)) 181 goto out_dcu2; 182 if (bus_space_map(sc->sc_iot, 183 VR4181AIU_AIU_BASE, VR4181AIU_AIU_SIZE, 184 0, &sc->sc_aiu_ioh)) 185 goto out_aiu; 186 187 /* 188 * reset AIU 189 */ 190 bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh, 191 VR4181AIU_SEQ_REG_W, VR4181AIU_AIURST); 192 bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh, 193 VR4181AIU_SEQ_REG_W, 0); 194 195 /* 196 * set sample rate (1kHz fixed) 197 * XXXX 198 * assume to PCLK is 32.768MHz 199 */ 200 bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh, 201 VR4181AIU_MCNVC_END, 202 32768000 / SAMPLEFREQ); 203 204 /* 205 * XXXX 206 * assume to PCLK is 32.768MHz 207 * DAVREF_SETUP = 5usec * PCLK = 163.84 208 */ 209 bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh, 210 VR4181AIU_DAVREF_SETUP_REG_W, 164); 211 212 vr4181aiu_disable(sc); 213 214 if (vrip_intr_establish(va->va_vc, va->va_unit, 0, 215 IPL_BIO, vr4181aiu_intr, sc) == NULL) { 216 printf("%s: can't establish interrupt\n", 217 device_xname(self)); 218 return; 219 } 220 221 printf("\n"); 222 return; 223 224 out_aiu: 225 bus_space_unmap(sc->sc_iot, sc->sc_dcu2_ioh, VR4181AIU_DCU2_SIZE); 226 out_dcu2: 227 bus_space_unmap(sc->sc_iot, sc->sc_dcu1_ioh, VR4181AIU_DCU1_SIZE); 228 out_dcu1: 229 printf(": can't map i/o space\n"); 230 } 231 232 int 233 vr4181aiuopen(dev_t dev, int flag, int mode, struct lwp *l) 234 { 235 struct vr4181aiu_softc *sc; 236 237 sc = device_lookup_private(&vr4181aiu_cd, minor(dev)); 238 if (sc == NULL) 239 return ENXIO; 240 241 if (sc->sc_status & ST_BUSY) 242 return EBUSY; 243 244 sc->sc_inbuf_head = sc->sc_inbuf_tail 245 = sc->sc_inbuf_which = sc->sc_inbuf1; 246 sc->sc_status &= ~ST_OVERRUN; 247 248 /* setup DMA */ 249 /* reset */ 250 bus_space_write_2(sc->sc_iot, sc->sc_dcu1_ioh, 251 DCU_DMARST_REG_W, 0); 252 bus_space_write_2(sc->sc_iot, sc->sc_dcu1_ioh, 253 DCU_DMARST_REG_W, DCU_DMARST); 254 /* dest1 <- sc_inbuf1 */ 255 bus_space_write_2(sc->sc_iot, sc->sc_dcu1_ioh, 256 DCU_MICDEST1REG1_W, 257 MIPS_KSEG0_TO_PHYS(sc->sc_inbuf1) & 0xffff); 258 bus_space_write_2(sc->sc_iot, sc->sc_dcu1_ioh, 259 DCU_MICDEST1REG2_W, 260 MIPS_KSEG0_TO_PHYS(sc->sc_inbuf1) >> 16); 261 /* dest2 <- sc_inbuf2 */ 262 bus_space_write_2(sc->sc_iot, sc->sc_dcu1_ioh, 263 DCU_MICDEST2REG1_W, 264 MIPS_KSEG0_TO_PHYS(sc->sc_inbuf2) & 0xffff); 265 bus_space_write_2(sc->sc_iot, sc->sc_dcu1_ioh, 266 DCU_MICDEST2REG2_W, 267 MIPS_KSEG0_TO_PHYS(sc->sc_inbuf2) >> 16); 268 /* record length <- INPUTLEN */ 269 bus_space_write_2(sc->sc_iot, sc->sc_dcu2_ioh, 270 DCU_MICRCLEN_REG_W, INPUTLEN); 271 /* config <- auto load */ 272 bus_space_write_2(sc->sc_iot, sc->sc_dcu2_ioh, 273 DCU_MICDMACFG_REG_W, DCU_MICLOAD); 274 /* irq <- irq clear */ 275 bus_space_write_2(sc->sc_iot, sc->sc_dcu2_ioh, 276 DCU_DMAITRQ_REG_W, DCU_MICEOP); 277 /* control <- INC */ 278 bus_space_write_2(sc->sc_iot, sc->sc_dcu2_ioh, 279 DCU_DMACTL_REG_W, DCU_MICCNT_INC); 280 /* irq mask <- microphone end of process */ 281 bus_space_write_2(sc->sc_iot, sc->sc_dcu2_ioh, 282 DCU_DMAITMK_REG_W, DCU_MICEOP_ENABLE); 283 284 /* enable DMA */ 285 bus_space_write_2(sc->sc_iot, sc->sc_dcu1_ioh, 286 DCU_AIUDMAMSK_REG_W, DCU_ENABLE_MIC); 287 288 /* enable ADC */ 289 bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh, 290 VR4181AIU_MCNT_REG_W, VR4181AIU_ADENAIU); 291 292 /* enable microphone */ 293 bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh, 294 VR4181AIU_SEQ_REG_W, VR4181AIU_AIUMEN); 295 296 sc->sc_status |= ST_BUSY; 297 298 return 0; 299 } 300 301 int 302 vr4181aiuclose(dev_t dev, int flag, int mode, struct lwp *l) 303 { 304 vr4181aiu_disable(device_lookup_private(&vr4181aiu_cd, minor(dev))); 305 return 0; 306 } 307 308 int 309 vr4181aiuread(dev_t dev, struct uio *uio, int flag) 310 { 311 struct vr4181aiu_softc *sc; 312 int s; 313 u_int16_t *fence; 314 int avail; 315 int count; 316 u_int8_t tmp[INPUTLEN / PICKUPCOUNT]; 317 u_int16_t *src; 318 u_int8_t *dst; 319 320 sc = device_lookup_private(&vr4181aiu_cd, minor(dev)); 321 322 src = sc->sc_inbuf_tail; 323 s = splbio(); 324 if (src == sc->sc_inbuf_head) { 325 /* wait for DMA to complete writing */ 326 tsleep(sc, PRIBIO, "aiu read", 0); 327 /* now sc_inbuf_head points alternate buffer */ 328 } 329 splx(s); 330 331 fence = sc->sc_inbuf_which == sc->sc_inbuf1 332 ? &sc->sc_inbuf1[INPUTLEN] 333 : &sc->sc_inbuf2[INPUTLEN]; 334 avail = (fence - src) / PICKUPCOUNT; 335 count = min(avail, uio->uio_resid); 336 dst = tmp; 337 while (count > 0) { 338 *dst++ = (u_int8_t) (*src >> 2); 339 src += PICKUPCOUNT; 340 count--; 341 } 342 343 if (src < fence) { 344 sc->sc_inbuf_tail = src; 345 } else { 346 /* alter the buffer */ 347 sc->sc_inbuf_tail 348 = sc->sc_inbuf_which 349 = sc->sc_inbuf_which == sc->sc_inbuf1 350 ? sc->sc_inbuf2 : sc->sc_inbuf1; 351 } 352 353 return uiomove(tmp, dst - tmp, uio); 354 } 355 356 int 357 vr4181aiuwrite(dev_t dev, struct uio *uio, int flag) 358 { 359 return 0; 360 } 361 362 /* 363 * interrupt handler 364 */ 365 static int 366 vr4181aiu_intr(void *arg) 367 { 368 struct vr4181aiu_softc *sc = arg; 369 370 if (!(sc->sc_status & ST_BUSY)) { 371 printf("vr4181aiu_intr: stray interrupt\n"); 372 vr4181aiu_disable(sc); 373 return 0; 374 } 375 376 /* irq clear */ 377 bus_space_write_2(sc->sc_iot, sc->sc_dcu2_ioh, 378 DCU_DMAITRQ_REG_W, DCU_MICEOP); 379 380 if (sc->sc_inbuf_head == sc->sc_inbuf1) { 381 if (sc->sc_inbuf_tail != sc->sc_inbuf1) 382 sc->sc_status |= ST_OVERRUN; 383 sc->sc_inbuf_head = sc->sc_inbuf2; 384 } else { 385 if (sc->sc_inbuf_tail != sc->sc_inbuf2) 386 sc->sc_status |= ST_OVERRUN; 387 sc->sc_inbuf_head = sc->sc_inbuf1; 388 } 389 390 if (sc->sc_status & ST_OVERRUN) { 391 printf("vr4181aiu_intr: overrun\n"); 392 } 393 394 DPRINTF(("vr4181aiu_intr: sc_inbuf1 = %04x, sc_inbuf2 = %04x\n", 395 sc->sc_inbuf1[0], sc->sc_inbuf2[0])); 396 397 wakeup(sc); 398 399 return 0; 400 } 401
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