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vr4181dcureg.h revision 1.1
      1 /* $NetBSD: vr4181dcureg.h,v 1.1 2003/05/01 07:02:04 igy Exp $ */
      2 
      3 /*
      4  * Copyright (c) 2002 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Naoto Shimazaki of YOKOGAWA Electric Corporation.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  * 3. All advertising materials mentioning features or use of this software
     19  *    must display the following acknowledgement:
     20  *        This product includes software developed by the NetBSD
     21  *        Foundation, Inc. and its contributors.
     22  * 4. Neither the name of The NetBSD Foundation nor the names of its
     23  *    contributors may be used to endorse or promote products derived
     24  *    from this software without specific prior written permission.
     25  *
     26  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     27  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     28  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     29  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     30  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     31  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     32  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     33  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     34  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     35  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     36  * POSSIBILITY OF SUCH DAMAGE.
     37  */
     38 
     39 /*
     40  *	VR4181 DCU (DMA Control Unit) Registers definitions.
     41  *		dcu1 at 0x0a000020-0x0a000047
     42  *		dcu2 at 0x0a000650-0x0a000667
     43  *
     44  */
     45 
     46 /* dcu1 registers */
     47 #define DCU_MICDEST1REG1_W	0x00	/* microphone destination 1 low */
     48 #define DCU_MICDEST1REG2_W	0x02	/* microphone destination 1 high */
     49 #define DCU_MICDEST2REG1_W	0x04	/* microphone destination 2 low */
     50 #define DCU_MICDEST2REG2_W	0x06	/* microphone destination 2 high */
     51 #define DCU_SPKRSRC1REG1_W	0x08	/* speaker destination 1 low */
     52 #define DCU_SPKRSRC1REG2_W	0x0a	/* speaker destination 1 high */
     53 #define DCU_SPKRSRC2REG1_W	0x0c	/* speaker destination 2 low */
     54 #define DCU_SPKRSRC2REG2_W	0x0e	/* speaker destination 2 high */
     55 #define DCU_DMARST_REG_W	0x20	/* DMA reset */
     56 #define  DCU_DMARST		0x0001	/* DMA reset */
     57 #define DCU_AIUDMAMSK_REG_W	0x26	/* audio DMA mask */
     58 #define  DCU_ENABLE_MIC		0x0008	/* enable microphone */
     59 #define  DCU_ENABLE_SPK		0x0004	/* enable speaker */
     60 
     61 /* dcu2 registers */
     62 #define DCU_MICRCLEN_REG_W	0x08	/* microphone record length */
     63 #define DCU_SPKRCLEN_REG_W	0x0a	/* speaker record length */
     64 #define DCU_MICDMACFG_REG_W	0x0e	/* microphone DMA configuration */
     65 #define  DCU_MICLOAD		0x0100
     66 #define DCU_SPKDMACFG_REG_W	0x10	/* speaker DMA configuration */
     67 #define  DCU_SPKLOAD		0x0001
     68 #define DCU_DMAITRQ_REG_W	0x12	/* DMA interrupt request */
     69 #define  DCU_SPKEOP		0x20
     70 #define  DCU_MICEOP		0x10
     71 #define DCU_DMACTL_REG_W	0x14	/* DMA control */
     72 #define  DCU_SPKCNT_MSK		0xc000
     73 #define  DCU_SPKCNT_INC		0x0000
     74 #define  DCU_SPKCNT_DEC		0x4000
     75 #define  DCU_MICCNT_MSK		0x3000
     76 #define  DCU_MICCNT_INC		0x0000
     77 #define  DCU_MICCNT_DEC		0x1000
     78 #define DCU_DMAITMK_REG_W	0x16	/* DMA interrupt mask */
     79 #define  DCU_SPKEOP_ENABLE	0x0020
     80 #define  DCU_MICEOP_ENABLE	0x0010
     81