1 1.2 igy /* $NetBSD: vr4181giureg.h,v 1.2 2003/05/01 07:02:05 igy Exp $ */ 2 1.1 sato 3 1.1 sato /*- 4 1.1 sato * Copyright (c) 2002 SATO Kazumi. All rights reserved. 5 1.1 sato * 6 1.1 sato * Redistribution and use in source and binary forms, with or without 7 1.1 sato * modification, are permitted provided that the following conditions 8 1.1 sato * are met: 9 1.1 sato * 1. Redistributions of source code must retain the above copyright 10 1.1 sato * notice, this list of conditions and the following disclaimer. 11 1.1 sato * 2. Redistributions in binary form must reproduce the above copyright 12 1.1 sato * notice, this list of conditions and the following disclaimer in the 13 1.1 sato * documentation and/or other materials provided with the distribution. 14 1.1 sato * 3. Neither the name of the project nor the names of its contributors 15 1.1 sato * may be used to endorse or promote products derived from this software 16 1.1 sato * without specific prior written permission. 17 1.1 sato * 18 1.1 sato * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 19 1.1 sato * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 1.1 sato * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 1.1 sato * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 22 1.1 sato * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 1.1 sato * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 1.1 sato * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 1.1 sato * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 1.1 sato * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 1.1 sato * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 1.1 sato * SUCH DAMAGE. 29 1.1 sato * 30 1.1 sato */ 31 1.1 sato 32 1.1 sato /* 33 1.1 sato * VR4181 GIU (General Purpose I/O Unit) Registers. 34 1.1 sato */ 35 1.1 sato #define VR4181GIU_NO_REG_W 0xffffffff /* no register */ 36 1.1 sato 37 1.1 sato #define VR4181GIU_MODE0_REG 0x00 38 1.1 sato #define VR4181GIU_MODE0_REG_W 0x00 39 1.1 sato #define VR4181GIU_MODE1_REG_W 0x02 40 1.1 sato #define VR4181GIU_MODE2_REG_W 0x04 41 1.1 sato #define VR4181GIU_MODE3_REG_W 0x06 42 1.1 sato 43 1.1 sato #define VR4181GIU_MODE_GPIO 0x0 44 1.1 sato #define VR4181GIU_MODE_ALT 0x1 45 1.1 sato /* VR4181GIU_MODE_GPIO */ 46 1.1 sato #define VR4181GIU_MODE_IN 0x0 47 1.1 sato #define VR4181GIU_MODE_OUT 0x2 48 1.1 sato /* VR4181GIU_MODE_ALT */ 49 1.1 sato #define VR4181GIU_MODE_ALT1 0x0 50 1.1 sato #define VR4181GIU_MODE_ALT2 0x2 51 1.1 sato 52 1.2 igy #define GP0_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 0) 53 1.2 igy #define GP0_CSISI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_ALT ) << 0) 54 1.2 igy #define GP0_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 0) 55 1.2 igy #define GP1_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 2) 56 1.2 igy #define GP1_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 2) 57 1.2 igy #define GP1_CSISO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_ALT ) << 2) 58 1.2 igy #define GP2_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 4) 59 1.2 igy #define GP2_CSICK ((VR4181GIU_MODE_IN | VR4181GIU_MODE_ALT ) << 4) 60 1.2 igy #define GP2_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 4) 61 1.2 igy #define GP3_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 6) 62 1.2 igy #define GP3_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 6) 63 1.2 igy #define GP3_PCS0 ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_ALT ) << 6) 64 1.2 igy #define GP4_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 8) 65 1.2 igy #define GP4_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 8) 66 1.2 igy #define GP5_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 10) 67 1.2 igy #define GP5_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 10) 68 1.2 igy #define GP5_DCD2 ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_ALT ) << 10) 69 1.2 igy #define GP6_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 12) 70 1.2 igy #define GP6_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 12) 71 1.2 igy #define GP6_RTS2 ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_ALT ) << 12) 72 1.2 igy #define GP7_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 14) 73 1.2 igy #define GP7_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 14) 74 1.2 igy #define GP7_DTR2 ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_ALT ) << 14) 75 1.2 igy #define GP8_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 0) 76 1.2 igy #define GP8_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 0) 77 1.2 igy #define GP8_DSR2 ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_ALT ) << 0) 78 1.2 igy #define GP9_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 2) 79 1.2 igy #define GP9_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 2) 80 1.2 igy #define GP9_CTS2 ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_ALT ) << 2) 81 1.2 igy #define GP10_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 4) 82 1.2 igy #define GP10_CSIFRM ((VR4181GIU_MODE_IN | VR4181GIU_MODE_ALT ) << 4) 83 1.2 igy #define GP10_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 4) 84 1.2 igy #define GP10_SYSCLK ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_ALT ) << 4) 85 1.2 igy #define GP11_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 6) 86 1.2 igy #define GP11_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 6) 87 1.2 igy #define GP11_PCS1 ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_ALT ) << 6) 88 1.2 igy #define GP12_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 8) 89 1.2 igy #define GP12_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 8) 90 1.2 igy #define GP12_LCDFPD4 ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_ALT ) << 8) 91 1.2 igy #define GP13_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 10) 92 1.2 igy #define GP13_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 10) 93 1.2 igy #define GP13_LCDPFD5 ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_ALT ) << 10) 94 1.2 igy #define GP14_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 12) 95 1.2 igy #define GP14_CD1 ((VR4181GIU_MODE_IN | VR4181GIU_MODE_ALT ) << 12) 96 1.2 igy #define GP14_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 12) 97 1.2 igy #define GP14_LCDPFD6 ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_ALT ) << 12) 98 1.2 igy #define GP15_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 14) 99 1.2 igy #define GP15_CD2 ((VR4181GIU_MODE_IN | VR4181GIU_MODE_ALT ) << 14) 100 1.2 igy #define GP15_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 14) 101 1.2 igy #define GP15_LCDFPD7 ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_ALT ) << 14) 102 1.2 igy #define GP16_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 0) 103 1.2 igy #define GP16_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 0) 104 1.2 igy #define GP16_IORD ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_ALT ) << 0) 105 1.2 igy #define GP17_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 2) 106 1.2 igy #define GP17_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 2) 107 1.2 igy #define GP17_IOWR ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_ALT ) << 2) 108 1.2 igy #define GP18_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 4) 109 1.2 igy #define GP18_IORDY ((VR4181GIU_MODE_IN | VR4181GIU_MODE_ALT ) << 4) 110 1.2 igy #define GP18_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 4) 111 1.2 igy #define GP19_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 6) 112 1.2 igy #define GP19_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 6) 113 1.2 igy #define GP19_IOCS16 ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_ALT ) << 6) 114 1.2 igy #define GP20_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 8) 115 1.2 igy #define GP20_LCDM ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 8) 116 1.2 igy #define GP20_UBE ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_ALT ) << 8) 117 1.2 igy #define GP21_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 10) 118 1.2 igy #define GP21_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 10) 119 1.2 igy #define GP21_RESET ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_ALT ) << 10) 120 1.2 igy #define GP22_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 12) 121 1.2 igy #define GP22_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 12) 122 1.2 igy #define GP22_ROMCS0 ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_ALT ) << 12) 123 1.2 igy #define GP23_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 14) 124 1.2 igy #define GP23_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 14) 125 1.2 igy #define GP23_ROMCS1 ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_ALT ) << 14) 126 1.2 igy #define GP24_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 0) 127 1.2 igy #define GP24_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 0) 128 1.2 igy #define GP24_ROMCS2 ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_ALT ) << 0) 129 1.2 igy #define GP25_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 2) 130 1.2 igy #define GP25_RxD1 ((VR4181GIU_MODE_IN | VR4181GIU_MODE_ALT ) << 2) 131 1.2 igy #define GP25_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 2) 132 1.2 igy #define GP26_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 4) 133 1.2 igy #define GP26_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 4) 134 1.2 igy #define GP26_TxD1 ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_ALT ) << 4) 135 1.2 igy #define GP27_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 6) 136 1.2 igy #define GP27_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 6) 137 1.2 igy #define GP27_RTS1 ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_ALT ) << 6) 138 1.2 igy #define GP28_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 8) 139 1.2 igy #define GP28_CTS1 ((VR4181GIU_MODE_IN | VR4181GIU_MODE_ALT ) << 8) 140 1.2 igy #define GP28_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 8) 141 1.2 igy #define GP29_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 10) 142 1.2 igy #define GP29_DCD1 ((VR4181GIU_MODE_IN | VR4181GIU_MODE_ALT ) << 10) 143 1.2 igy #define GP29_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 10) 144 1.2 igy #define GP30_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 12) 145 1.2 igy #define GP30_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 12) 146 1.2 igy #define GP30_DTR1 ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_ALT ) << 12) 147 1.2 igy #define GP31_GPI ((VR4181GIU_MODE_IN | VR4181GIU_MODE_GPIO) << 14) 148 1.2 igy #define GP31_DSR1 ((VR4181GIU_MODE_IN | VR4181GIU_MODE_ALT ) << 14) 149 1.2 igy #define GP31_GPO ((VR4181GIU_MODE_OUT | VR4181GIU_MODE_GPIO) << 14) 150 1.2 igy 151 1.2 igy 152 1.1 sato #define VR4181GIU_PIOD_REG 0x08 153 1.2 igy #define VR4181GIU_PIOD_H_REG_W 0x08 154 1.2 igy #define VR4181GIU_PIOD_L_REG_W 0x0a 155 1.1 sato 156 1.1 sato #define VR4181GIU_INTEN_REG_W 0x0c 157 1.2 igy #define GIEN0 (1U << 0) 158 1.2 igy #define GIEN1 (1U << 1) 159 1.2 igy #define GIEN2 (1U << 2) 160 1.2 igy #define GIEN3 (1U << 3) 161 1.2 igy #define GIEN4 (1U << 4) 162 1.2 igy #define GIEN5 (1U << 5) 163 1.2 igy #define GIEN6 (1U << 6) 164 1.2 igy #define GIEN7 (1U << 7) 165 1.2 igy #define GIEN8 (1U << 8) 166 1.2 igy #define GIEN9 (1U << 9) 167 1.2 igy #define GIEN10 (1U << 10) 168 1.2 igy #define GIEN11 (1U << 11) 169 1.2 igy #define GIEN12 (1U << 12) 170 1.2 igy #define GIEN13 (1U << 13) 171 1.2 igy #define GIEN14 (1U << 14) 172 1.2 igy #define GIEN15 (1U << 15) 173 1.2 igy 174 1.2 igy #define VR4181GIU_INTMASK_REG_W 0x0e 175 1.2 igy #define GIMSK0 (1U << 0) 176 1.2 igy #define GIMSK1 (1U << 1) 177 1.2 igy #define GIMSK2 (1U << 2) 178 1.2 igy #define GIMSK3 (1U << 3) 179 1.2 igy #define GIMSK4 (1U << 4) 180 1.2 igy #define GIMSK5 (1U << 5) 181 1.2 igy #define GIMSK6 (1U << 6) 182 1.2 igy #define GIMSK7 (1U << 7) 183 1.2 igy #define GIMSK8 (1U << 8) 184 1.2 igy #define GIMSK9 (1U << 9) 185 1.2 igy #define GIMSK10 (1U << 10) 186 1.2 igy #define GIMSK11 (1U << 11) 187 1.2 igy #define GIMSK12 (1U << 12) 188 1.2 igy #define GIMSK13 (1U << 13) 189 1.2 igy #define GIMSK14 (1U << 14) 190 1.2 igy #define GIMSK15 (1U << 15) 191 1.1 sato 192 1.2 igy #define VR4181GIU_INTTYP_REG 0x10 193 1.2 igy #define VR4181GIU_INTTYP_H_REG_W 0x10 194 1.2 igy #define VR4181GIU_INTTYP_L_REG_W 0x12 195 1.1 sato 196 1.2 igy #define VR4181GIU_INTTYP_HIGH_LEVEL 0x3 197 1.2 igy #define VR4181GIU_INTTYP_LOW_LEVEL 0x2 198 1.2 igy #define VR4181GIU_INTTYP_RISING_EDGE 0x1 199 1.2 igy #define VR4181GIU_INTTYP_FALLING_EDGE 0x0 200 1.2 igy #define VR4181GIU_INTTYP_INVALID (-1) /* for validation check */ 201 1.2 igy 202 1.2 igy #define I0TYP_HIGH_LEVEL (VR4181GIU_INTTYP_HIGH_LEVEL << 0) 203 1.2 igy #define I0TYP_LOW_LEVEL (VR4181GIU_INTTYP_LOW_LEVEL << 0) 204 1.2 igy #define I0TYP_RISING_EDGE (VR4181GIU_INTTYP_RISING_EDGE << 0) 205 1.2 igy #define I0TYP_FALLING_EDGE (VR4181GIU_INTTYP_FALLING_EDGE << 0) 206 1.2 igy 207 1.2 igy #define I1TYP_HIGH_LEVEL (VR4181GIU_INTTYP_HIGH_LEVEL << 2) 208 1.2 igy #define I1TYP_LOW_LEVEL (VR4181GIU_INTTYP_LOW_LEVEL << 2) 209 1.2 igy #define I1TYP_RISING_EDGE (VR4181GIU_INTTYP_RISING_EDGE << 2) 210 1.2 igy #define I1TYP_FALLING_EDGE (VR4181GIU_INTTYP_FALLING_EDGE << 2) 211 1.2 igy 212 1.2 igy #define I2TYP_HIGH_LEVEL (VR4181GIU_INTTYP_HIGH_LEVEL << 4) 213 1.2 igy #define I2TYP_LOW_LEVEL (VR4181GIU_INTTYP_LOW_LEVEL << 4) 214 1.2 igy #define I2TYP_RISING_EDGE (VR4181GIU_INTTYP_RISING_EDGE << 4) 215 1.2 igy #define I2TYP_FALLING_EDGE (VR4181GIU_INTTYP_FALLING_EDGE << 4) 216 1.2 igy 217 1.2 igy #define I3TYP_HIGH_LEVEL (VR4181GIU_INTTYP_HIGH_LEVEL << 6) 218 1.2 igy #define I3TYP_LOW_LEVEL (VR4181GIU_INTTYP_LOW_LEVEL << 6) 219 1.2 igy #define I3TYP_RISING_EDGE (VR4181GIU_INTTYP_RISING_EDGE << 6) 220 1.2 igy #define I3TYP_FALLING_EDGE (VR4181GIU_INTTYP_FALLING_EDGE << 6) 221 1.2 igy 222 1.2 igy #define I4TYP_HIGH_LEVEL (VR4181GIU_INTTYP_HIGH_LEVEL << 8) 223 1.2 igy #define I4TYP_LOW_LEVEL (VR4181GIU_INTTYP_LOW_LEVEL << 8) 224 1.2 igy #define I4TYP_RISING_EDGE (VR4181GIU_INTTYP_RISING_EDGE << 8) 225 1.2 igy #define I4TYP_FALLING_EDGE (VR4181GIU_INTTYP_FALLING_EDGE << 8) 226 1.2 igy 227 1.2 igy #define I5TYP_HIGH_LEVEL (VR4181GIU_INTTYP_HIGH_LEVEL << 10) 228 1.2 igy #define I5TYP_LOW_LEVEL (VR4181GIU_INTTYP_LOW_LEVEL << 10) 229 1.2 igy #define I5TYP_RISING_EDGE (VR4181GIU_INTTYP_RISING_EDGE << 10) 230 1.2 igy #define I5TYP_FALLING_EDGE (VR4181GIU_INTTYP_FALLING_EDGE << 10) 231 1.2 igy 232 1.2 igy #define I6TYP_HIGH_LEVEL (VR4181GIU_INTTYP_HIGH_LEVEL << 12) 233 1.2 igy #define I6TYP_LOW_LEVEL (VR4181GIU_INTTYP_LOW_LEVEL << 12) 234 1.2 igy #define I6TYP_RISING_EDGE (VR4181GIU_INTTYP_RISING_EDGE << 12) 235 1.2 igy #define I6TYP_FALLING_EDGE (VR4181GIU_INTTYP_FALLING_EDGE << 12) 236 1.2 igy 237 1.2 igy #define I7TYP_HIGH_LEVEL (VR4181GIU_INTTYP_HIGH_LEVEL << 14) 238 1.2 igy #define I7TYP_LOW_LEVEL (VR4181GIU_INTTYP_LOW_LEVEL << 14) 239 1.2 igy #define I7TYP_RISING_EDGE (VR4181GIU_INTTYP_RISING_EDGE << 14) 240 1.2 igy #define I7TYP_FALLING_EDGE (VR4181GIU_INTTYP_FALLING_EDGE << 14) 241 1.2 igy 242 1.2 igy #define I8TYP_HIGH_LEVEL (VR4181GIU_INTTYP_HIGH_LEVEL << 0) 243 1.2 igy #define I8TYP_LOW_LEVEL (VR4181GIU_INTTYP_LOW_LEVEL << 0) 244 1.2 igy #define I8TYP_RISING_EDGE (VR4181GIU_INTTYP_RISING_EDGE << 0) 245 1.2 igy #define I8TYP_FALLING_EDGE (VR4181GIU_INTTYP_FALLING_EDGE << 0) 246 1.2 igy 247 1.2 igy #define I9TYP_HIGH_LEVEL (VR4181GIU_INTTYP_HIGH_LEVEL << 2) 248 1.2 igy #define I9TYP_LOW_LEVEL (VR4181GIU_INTTYP_LOW_LEVEL << 2) 249 1.2 igy #define I9TYP_RISING_EDGE (VR4181GIU_INTTYP_RISING_EDGE << 2) 250 1.2 igy #define I9TYP_FALLING_EDGE (VR4181GIU_INTTYP_FALLING_EDGE << 2) 251 1.2 igy 252 1.2 igy #define I10TYP_HIGH_LEVEL (VR4181GIU_INTTYP_HIGH_LEVEL << 4) 253 1.2 igy #define I10TYP_LOW_LEVEL (VR4181GIU_INTTYP_LOW_LEVEL << 4) 254 1.2 igy #define I10TYP_RISING_EDGE (VR4181GIU_INTTYP_RISING_EDGE << 4) 255 1.2 igy #define I10TYP_FALLING_EDGE (VR4181GIU_INTTYP_FALLING_EDGE << 4) 256 1.2 igy 257 1.2 igy #define I11TYP_HIGH_LEVEL (VR4181GIU_INTTYP_HIGH_LEVEL << 6) 258 1.2 igy #define I11TYP_LOW_LEVEL (VR4181GIU_INTTYP_LOW_LEVEL << 6) 259 1.2 igy #define I11TYP_RISING_EDGE (VR4181GIU_INTTYP_RISING_EDGE << 6) 260 1.2 igy #define I11TYP_FALLING_EDGE (VR4181GIU_INTTYP_FALLING_EDGE << 6) 261 1.2 igy 262 1.2 igy #define I12TYP_HIGH_LEVEL (VR4181GIU_INTTYP_HIGH_LEVEL << 8) 263 1.2 igy #define I12TYP_LOW_LEVEL (VR4181GIU_INTTYP_LOW_LEVEL << 8) 264 1.2 igy #define I12TYP_RISING_EDGE (VR4181GIU_INTTYP_RISING_EDGE << 8) 265 1.2 igy #define I12TYP_FALLING_EDGE (VR4181GIU_INTTYP_FALLING_EDGE << 8) 266 1.2 igy 267 1.2 igy #define I13TYP_HIGH_LEVEL (VR4181GIU_INTTYP_HIGH_LEVEL << 10) 268 1.2 igy #define I13TYP_LOW_LEVEL (VR4181GIU_INTTYP_LOW_LEVEL << 10) 269 1.2 igy #define I13TYP_RISING_EDGE (VR4181GIU_INTTYP_RISING_EDGE << 10) 270 1.2 igy #define I13TYP_FALLING_EDGE (VR4181GIU_INTTYP_FALLING_EDGE << 10) 271 1.2 igy 272 1.2 igy #define I14TYP_HIGH_LEVEL (VR4181GIU_INTTYP_HIGH_LEVEL << 12) 273 1.2 igy #define I14TYP_LOW_LEVEL (VR4181GIU_INTTYP_LOW_LEVEL << 12) 274 1.2 igy #define I14TYP_RISING_EDGE (VR4181GIU_INTTYP_RISING_EDGE << 12) 275 1.2 igy #define I14TYP_FALLING_EDGE (VR4181GIU_INTTYP_FALLING_EDGE << 12) 276 1.2 igy 277 1.2 igy #define I15TYP_HIGH_LEVEL (VR4181GIU_INTTYP_HIGH_LEVEL << 14) 278 1.2 igy #define I15TYP_LOW_LEVEL (VR4181GIU_INTTYP_LOW_LEVEL << 14) 279 1.2 igy #define I15TYP_RISING_EDGE (VR4181GIU_INTTYP_RISING_EDGE << 14) 280 1.2 igy #define I15TYP_FALLING_EDGE (VR4181GIU_INTTYP_FALLING_EDGE << 14) 281 1.1 sato 282 1.1 sato #define VR4181GIU_INTSTAT_REG_W 0x14 283 1.1 sato 284 1.1 sato #define VR4181GIU_HIBST_REG 0x16 285 1.1 sato #define VR4181GIU_HIBST_L_REG_W 0x16 286 1.1 sato #define VR4181GIU_HIBST_H_REG_W 0x18 287 1.1 sato 288 1.1 sato #define VR4181GIU_SICTL_REG_W 0x1a 289 1.1 sato 290 1.1 sato #define VR4181GIU_KEYEN_REG_W 0x1c 291 1.1 sato 292 1.2 igy #define VR4181GIU_PCS0STRA_REG_W 0x20 293 1.2 igy #define VR4181GIU_PCS0STPA_REG_W 0x22 294 1.2 igy #define VR4181GIU_PCS0HIA_REG_W 0x24 295 1.2 igy #define VR4181GIU_PCS1STRA_REG_W 0x26 296 1.2 igy #define VR4181GIU_PCS1STPA_REG_W 0x28 297 1.2 igy #define VR4181GIU_PCS1HIA_REG_W 0x2a 298 1.2 igy 299 1.2 igy #define VR4181GIU_PCSMODE_REG_W 0x2c 300 1.2 igy 301 1.2 igy #define PCS0MD_DISABLE (0x0 << 0) 302 1.2 igy #define PCS0MD_READ (0x1 << 0) 303 1.2 igy #define PCS0MD_WRITE (0x2 << 0) 304 1.2 igy #define PCS0MD_READWRITE (0x3 << 0) 305 1.2 igy #define PCS0DSIZE_8BIT (0x0 << 2) 306 1.2 igy #define PCS0DSIZE_16BIT (0x1 << 2) 307 1.2 igy #define PCS0MIOB_IO (0x0 << 3) 308 1.2 igy #define PCS0MIOB_MEM (0x1 << 3) 309 1.2 igy #define PCS1MD_DISABLE (0x0 << 4) 310 1.2 igy #define PCS1MD_READ (0x1 << 4) 311 1.2 igy #define PCS1MD_WRITE (0x2 << 4) 312 1.2 igy #define PCS1MD_READWRITE (0x3 << 4) 313 1.2 igy #define PCS1DSIZE_8BIT (0x0 << 6) 314 1.2 igy #define PCS1DSIZE_16BIT (0x1 << 6) 315 1.2 igy #define PCS1MIOB_IO (0x0 << 7) 316 1.2 igy #define PCS1MIOB_MEM (0x1 << 7) 317 1.2 igy 318 1.1 sato 319 1.1 sato /* END vr4181giu.h */ 320
Indexes created Mon Sep 29 21:09:56 GMT 2025