vrc4172gpio.c revision 1.2.10.3
1 1.2.10.3 nathanw /* $NetBSD: vrc4172gpio.c,v 1.2.10.3 2002/10/18 02:37:17 nathanw Exp $ */ 2 1.2.10.2 nathanw /*- 3 1.2.10.2 nathanw * Copyright (c) 2001 TAKEMRUA Shin. All rights reserved. 4 1.2.10.2 nathanw * 5 1.2.10.2 nathanw * Redistribution and use in source and binary forms, with or without 6 1.2.10.2 nathanw * modification, are permitted provided that the following conditions 7 1.2.10.2 nathanw * are met: 8 1.2.10.2 nathanw * 1. Redistributions of source code must retain the above copyright 9 1.2.10.2 nathanw * notice, this list of conditions and the following disclaimer. 10 1.2.10.2 nathanw * 2. Redistributions in binary form must reproduce the above copyright 11 1.2.10.2 nathanw * notice, this list of conditions and the following disclaimer in the 12 1.2.10.2 nathanw * documentation and/or other materials provided with the distribution. 13 1.2.10.2 nathanw * 3. Neither the name of the project nor the names of its contributors 14 1.2.10.2 nathanw * may be used to endorse or promote products derived from this software 15 1.2.10.2 nathanw * without specific prior written permission. 16 1.2.10.2 nathanw * 17 1.2.10.2 nathanw * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 18 1.2.10.2 nathanw * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 1.2.10.2 nathanw * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 1.2.10.2 nathanw * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 21 1.2.10.2 nathanw * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 1.2.10.2 nathanw * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 1.2.10.2 nathanw * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 1.2.10.2 nathanw * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 1.2.10.2 nathanw * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 1.2.10.2 nathanw * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 1.2.10.2 nathanw * SUCH DAMAGE. 28 1.2.10.2 nathanw * 29 1.2.10.2 nathanw */ 30 1.2.10.2 nathanw 31 1.2.10.2 nathanw #include <sys/param.h> 32 1.2.10.2 nathanw #include <sys/systm.h> 33 1.2.10.2 nathanw #include <sys/device.h> 34 1.2.10.2 nathanw #include <sys/malloc.h> 35 1.2.10.2 nathanw #include <sys/queue.h> 36 1.2.10.2 nathanw #include <sys/reboot.h> 37 1.2.10.2 nathanw #include <machine/bus.h> 38 1.2.10.2 nathanw #include <machine/platid.h> 39 1.2.10.2 nathanw #include <machine/platid_mask.h> 40 1.2.10.2 nathanw 41 1.2.10.2 nathanw #include <dev/hpc/hpciovar.h> 42 1.2.10.2 nathanw 43 1.2.10.2 nathanw #include <hpcmips/vr/vripif.h> 44 1.2.10.2 nathanw #include <hpcmips/vr/vripvar.h> 45 1.2.10.2 nathanw #include <hpcmips/vr/vrc4172gpioreg.h> 46 1.2.10.2 nathanw 47 1.2.10.2 nathanw #include "locators.h" 48 1.2.10.2 nathanw 49 1.2.10.2 nathanw #define VRC2GPIODEBUG 50 1.2.10.2 nathanw #ifdef VRC2GPIODEBUG 51 1.2.10.2 nathanw #define DBG_IO (1<<0) 52 1.2.10.2 nathanw #define DBG_INTR (1<<1) 53 1.2.10.2 nathanw #define DBG_INFO (1<<2) 54 1.2.10.2 nathanw #ifndef VRC2GPIODEBUG_CONF 55 1.2.10.2 nathanw #define VRC2GPIODEBUG_CONF 0 56 1.2.10.2 nathanw #endif /* VRC2GPIODEBUG_CONF */ 57 1.2.10.2 nathanw int vrc4172gpio_debug = VRC2GPIODEBUG_CONF; 58 1.2.10.2 nathanw #define DBG(flag) (vrc4172gpio_debug & (flag)) 59 1.2.10.2 nathanw #define DPRINTF(flag, arg...) do { \ 60 1.2.10.2 nathanw if (DBG(flag)) \ 61 1.2.10.2 nathanw printf(##arg); \ 62 1.2.10.2 nathanw } while (0) 63 1.2.10.2 nathanw #else 64 1.2.10.2 nathanw #define DBG(flag) (0) 65 1.2.10.2 nathanw #define DPRINTF(flag, arg...) do {} while(0) 66 1.2.10.2 nathanw #endif 67 1.2.10.2 nathanw #define VPRINTF(arg...) do { \ 68 1.2.10.2 nathanw if (bootverbose) \ 69 1.2.10.2 nathanw printf(##arg); \ 70 1.2.10.2 nathanw } while (0) 71 1.2.10.2 nathanw 72 1.2.10.2 nathanw #define CHECK_PORT(x) (0 <= (x) && (x) < VRC2_EXGP_NPORTS) 73 1.2.10.2 nathanw 74 1.2.10.2 nathanw struct vrc4172gpio_intr_entry { 75 1.2.10.2 nathanw int ih_port; 76 1.2.10.2 nathanw int (*ih_fun)(void*); 77 1.2.10.2 nathanw void *ih_arg; 78 1.2.10.2 nathanw TAILQ_ENTRY(vrc4172gpio_intr_entry) ih_link; 79 1.2.10.2 nathanw }; 80 1.2.10.2 nathanw 81 1.2.10.2 nathanw struct vrc4172gpio_softc { 82 1.2.10.2 nathanw struct device sc_dev; 83 1.2.10.2 nathanw bus_space_tag_t sc_iot; 84 1.2.10.2 nathanw bus_space_handle_t sc_ioh; 85 1.2.10.2 nathanw struct hpcio_attach_args sc_args; 86 1.2.10.2 nathanw struct hpcio_chip *sc_hc; 87 1.2.10.2 nathanw 88 1.2.10.2 nathanw void *sc_intr_handle; 89 1.2.10.2 nathanw u_int32_t sc_intr_mask; 90 1.2.10.2 nathanw u_int32_t sc_data; 91 1.2.10.2 nathanw u_int32_t sc_intr_mode[VRC2_EXGP_NPORTS]; 92 1.2.10.2 nathanw TAILQ_HEAD(, vrc4172gpio_intr_entry) sc_intr_head[VRC2_EXGP_NPORTS]; 93 1.2.10.2 nathanw struct hpcio_chip sc_iochip; 94 1.2.10.2 nathanw struct hpcio_attach_args sc_haa; 95 1.2.10.2 nathanw }; 96 1.2.10.2 nathanw 97 1.2.10.2 nathanw int vrc4172gpio_match(struct device*, struct cfdata*, void*); 98 1.2.10.2 nathanw void vrc4172gpio_attach(struct device*, struct device*, void*); 99 1.2.10.2 nathanw void vrc4172gpio_callback(struct device *self); 100 1.2.10.2 nathanw int vrc4172gpio_intr(void*); 101 1.2.10.2 nathanw int vrc4172gpio_print(void*, const char*); 102 1.2.10.2 nathanw 103 1.2.10.2 nathanw int vrc4172gpio_port_read(hpcio_chip_t, int); 104 1.2.10.2 nathanw void vrc4172gpio_port_write(hpcio_chip_t, int, int); 105 1.2.10.2 nathanw void *vrc4172gpio_intr_establish(hpcio_chip_t, int, int, int (*)(void *), void*); 106 1.2.10.2 nathanw void vrc4172gpio_intr_disestablish(hpcio_chip_t, void*); 107 1.2.10.2 nathanw void vrc4172gpio_intr_clear(hpcio_chip_t, void*); 108 1.2.10.2 nathanw void vrc4172gpio_register_iochip(hpcio_chip_t, hpcio_chip_t); 109 1.2.10.2 nathanw void vrc4172gpio_update(hpcio_chip_t); 110 1.2.10.2 nathanw void vrc4172gpio_dump(hpcio_chip_t); 111 1.2.10.2 nathanw void vrc4172gpio_intr_dump(struct vrc4172gpio_softc *, int); 112 1.2.10.2 nathanw hpcio_chip_t vrc4172gpio_getchip(void*, int); 113 1.2.10.2 nathanw static void vrc4172gpio_diffport(struct vrc4172gpio_softc *sc); 114 1.2.10.2 nathanw 115 1.2.10.2 nathanw static u_int16_t read_2(struct vrc4172gpio_softc *, bus_addr_t); 116 1.2.10.2 nathanw static void write_2(struct vrc4172gpio_softc *, bus_addr_t, u_int16_t); 117 1.2.10.2 nathanw static u_int32_t read_4(struct vrc4172gpio_softc *, bus_addr_t); 118 1.2.10.2 nathanw static void write_4(struct vrc4172gpio_softc *, bus_addr_t, u_int32_t); 119 1.2.10.2 nathanw static void dumpbits(u_int32_t*, int, int, int, const char[2]); 120 1.2.10.2 nathanw 121 1.2.10.2 nathanw static struct hpcio_chip vrc4172gpio_iochip = { 122 1.2.10.2 nathanw .hc_portread = vrc4172gpio_port_read, 123 1.2.10.2 nathanw .hc_portwrite = vrc4172gpio_port_write, 124 1.2.10.2 nathanw .hc_intr_establish = vrc4172gpio_intr_establish, 125 1.2.10.2 nathanw .hc_intr_disestablish = vrc4172gpio_intr_disestablish, 126 1.2.10.2 nathanw .hc_intr_clear = vrc4172gpio_intr_clear, 127 1.2.10.2 nathanw .hc_register_iochip = vrc4172gpio_register_iochip, 128 1.2.10.2 nathanw .hc_update = vrc4172gpio_update, 129 1.2.10.2 nathanw .hc_dump = vrc4172gpio_dump, 130 1.2.10.2 nathanw }; 131 1.2.10.2 nathanw 132 1.2.10.2 nathanw static int intlv_regs[] = { 133 1.2.10.2 nathanw VRC2_EXGPINTLV0L, 134 1.2.10.2 nathanw VRC2_EXGPINTLV0H, 135 1.2.10.2 nathanw VRC2_EXGPINTLV1L 136 1.2.10.2 nathanw }; 137 1.2.10.2 nathanw 138 1.2.10.3 nathanw CFATTACH_DECL(vrc4172gpio, sizeof(struct vrc4172gpio_softc), 139 1.2.10.3 nathanw vrc4172gpio_match, vrc4172gpio_attach, NULL, NULL); 140 1.2.10.2 nathanw 141 1.2.10.2 nathanw /* 142 1.2.10.2 nathanw * regster access method 143 1.2.10.2 nathanw */ 144 1.2.10.2 nathanw static inline u_int16_t 145 1.2.10.2 nathanw read_2(struct vrc4172gpio_softc *sc, bus_addr_t off) 146 1.2.10.2 nathanw { 147 1.2.10.2 nathanw return bus_space_read_2(sc->sc_iot, sc->sc_ioh, off); 148 1.2.10.2 nathanw } 149 1.2.10.2 nathanw 150 1.2.10.2 nathanw static inline void 151 1.2.10.2 nathanw write_2(struct vrc4172gpio_softc *sc, bus_addr_t off, u_int16_t data) 152 1.2.10.2 nathanw { 153 1.2.10.2 nathanw bus_space_write_2(sc->sc_iot, sc->sc_ioh, off, data); 154 1.2.10.2 nathanw } 155 1.2.10.2 nathanw 156 1.2.10.2 nathanw static u_int32_t 157 1.2.10.2 nathanw read_4(struct vrc4172gpio_softc *sc, bus_addr_t off) 158 1.2.10.2 nathanw { 159 1.2.10.2 nathanw u_int16_t reg0, reg1; 160 1.2.10.2 nathanw 161 1.2.10.2 nathanw reg0 = read_2(sc, off); 162 1.2.10.2 nathanw reg1 = read_2(sc, off + VRC2_EXGP_OFFSET); 163 1.2.10.2 nathanw 164 1.2.10.2 nathanw return (reg0|(reg1<<16)); 165 1.2.10.2 nathanw } 166 1.2.10.2 nathanw 167 1.2.10.2 nathanw static void 168 1.2.10.2 nathanw write_4(struct vrc4172gpio_softc *sc, bus_addr_t off, u_int32_t data) 169 1.2.10.2 nathanw { 170 1.2.10.2 nathanw write_2(sc, off, data & 0xffff); 171 1.2.10.2 nathanw write_2(sc, off + VRC2_EXGP_OFFSET, (data>>16)&0xffff); 172 1.2.10.2 nathanw } 173 1.2.10.2 nathanw 174 1.2.10.2 nathanw int 175 1.2.10.2 nathanw vrc4172gpio_match(struct device *parent, struct cfdata *cf, void *aux) 176 1.2.10.2 nathanw { 177 1.2.10.2 nathanw struct hpcio_attach_args *haa = aux; 178 1.2.10.2 nathanw platid_mask_t mask; 179 1.2.10.2 nathanw 180 1.2.10.2 nathanw if (strcmp(haa->haa_busname, HPCIO_BUSNAME)) 181 1.2.10.2 nathanw return (0); 182 1.2.10.2 nathanw if (cf->cf_loc[HPCIOIFCF_PLATFORM] == 0) 183 1.2.10.2 nathanw return (0); 184 1.2.10.2 nathanw mask = PLATID_DEREF(cf->cf_loc[HPCIOIFCF_PLATFORM]); 185 1.2.10.2 nathanw 186 1.2.10.2 nathanw return platid_match(&platid, &mask); 187 1.2.10.2 nathanw } 188 1.2.10.2 nathanw 189 1.2.10.2 nathanw void 190 1.2.10.2 nathanw vrc4172gpio_attach(struct device *parent, struct device *self, void *aux) 191 1.2.10.2 nathanw { 192 1.2.10.2 nathanw struct hpcio_attach_args *args = aux; 193 1.2.10.2 nathanw struct vrc4172gpio_softc *sc = (void*)self; 194 1.2.10.2 nathanw int i, *loc, port, mode; 195 1.2.10.2 nathanw u_int32_t regs[6], t0, t1, t2; 196 1.2.10.2 nathanw 197 1.2.10.2 nathanw printf("\n"); 198 1.2.10.2 nathanw loc = sc->sc_dev.dv_cfdata->cf_loc; 199 1.2.10.2 nathanw 200 1.2.10.2 nathanw /* 201 1.2.10.2 nathanw * map bus space 202 1.2.10.2 nathanw */ 203 1.2.10.2 nathanw sc->sc_iot = args->haa_iot; 204 1.2.10.2 nathanw sc->sc_hc = (*args->haa_getchip)(args->haa_sc, loc[HPCIOIFCF_IOCHIP]); 205 1.2.10.2 nathanw sc->sc_args = *args; /* structure copy */ 206 1.2.10.2 nathanw bus_space_map(sc->sc_iot, loc[HPCIOIFCF_ADDR], loc[HPCIOIFCF_SIZE], 207 1.2.10.2 nathanw 0 /* no cache */, &sc->sc_ioh); 208 1.2.10.2 nathanw if (sc->sc_ioh == NULL) { 209 1.2.10.2 nathanw printf("%s: can't map bus space\n", sc->sc_dev.dv_xname); 210 1.2.10.2 nathanw return; 211 1.2.10.2 nathanw } 212 1.2.10.2 nathanw 213 1.2.10.2 nathanw /* 214 1.2.10.2 nathanw * dump Windows CE register setting 215 1.2.10.2 nathanw */ 216 1.2.10.2 nathanw regs[0] = read_4(sc, VRC2_EXGPDATA); 217 1.2.10.2 nathanw regs[1] = read_4(sc, VRC2_EXGPDIR); 218 1.2.10.2 nathanw regs[2] = read_4(sc, VRC2_EXGPINTEN); 219 1.2.10.2 nathanw regs[3] = read_4(sc, VRC2_EXGPINTTYP); 220 1.2.10.2 nathanw t0 = read_2(sc, VRC2_EXGPINTLV0L); 221 1.2.10.2 nathanw t1 = read_2(sc, VRC2_EXGPINTLV0H); 222 1.2.10.2 nathanw t2 = read_2(sc, VRC2_EXGPINTLV1L); 223 1.2.10.2 nathanw regs[4] = ((t2&0xff00)<<8) | (t1&0xff00) | ((t0&0xff00)>>8); 224 1.2.10.2 nathanw regs[5] = ((t2&0xff)<<16) | ((t1&0xff)<<8) | (t0&0xff); 225 1.2.10.2 nathanw 226 1.2.10.2 nathanw if (bootverbose || DBG(DBG_INFO)) { 227 1.2.10.2 nathanw /* 228 1.2.10.2 nathanw * o: output 229 1.2.10.2 nathanw * i: input (no interrupt) 230 1.2.10.2 nathanw * H: level sense interrupt (active high) 231 1.2.10.2 nathanw * L: level sense interrupt (active low) 232 1.2.10.2 nathanw * B: both edge trigger interrupt 233 1.2.10.2 nathanw * P: positive edge trigger interrupt 234 1.2.10.2 nathanw * N: negative edge trigger interrupt 235 1.2.10.2 nathanw */ 236 1.2.10.2 nathanw printf(" port#:321098765432109876543210\n"); 237 1.2.10.2 nathanw printf(" EXGPDATA :"); 238 1.2.10.2 nathanw dumpbits(®s[0], 1, 23, 0, "10\n"); 239 1.2.10.2 nathanw printf("WIN setting:"); 240 1.2.10.2 nathanw dumpbits(®s[1], 5, 23, 0, 241 1.2.10.2 nathanw "oooo" /* dir=1 en=1 typ=1 */ 242 1.2.10.2 nathanw "oooo" /* dir=1 en=1 typ=0 */ 243 1.2.10.2 nathanw "oooo" /* dir=1 en=0 typ=1 */ 244 1.2.10.2 nathanw "oooo" /* dir=1 en=0 typ=0 */ 245 1.2.10.2 nathanw "BBPN" /* dir=0 en=1 typ=1 */ 246 1.2.10.2 nathanw "HLHL" /* dir=0 en=1 typ=0 */ 247 1.2.10.2 nathanw "iiii" /* dir=0 en=0 typ=1 */ 248 1.2.10.2 nathanw "iiii" /* dir=0 en=0 typ=0 */ 249 1.2.10.2 nathanw ); 250 1.2.10.2 nathanw printf("\n"); 251 1.2.10.2 nathanw } 252 1.2.10.2 nathanw #ifdef VRC2GPIODEBUG 253 1.2.10.2 nathanw if (DBG(DBG_INFO)) { 254 1.2.10.2 nathanw printf(" EXGPDIR :"); 255 1.2.10.2 nathanw dumpbits(®s[1], 1, 23, 0, "oi\n"); 256 1.2.10.2 nathanw 257 1.2.10.2 nathanw printf(" EXGPINTEN :"); 258 1.2.10.2 nathanw dumpbits(®s[2], 1, 23, 0, "I-\n"); 259 1.2.10.2 nathanw 260 1.2.10.2 nathanw printf(" EXGPINTTYP:"); 261 1.2.10.2 nathanw dumpbits(®s[3], 1, 23, 0, "EL\n"); 262 1.2.10.2 nathanw 263 1.2.10.2 nathanw printf(" EXPIB :"); 264 1.2.10.2 nathanw dumpbits(®s[4], 1, 23, 0, "10\n"); 265 1.2.10.2 nathanw 266 1.2.10.2 nathanw printf(" EXPIL :"); 267 1.2.10.2 nathanw dumpbits(®s[5], 1, 23, 0, "10\n"); 268 1.2.10.2 nathanw 269 1.2.10.2 nathanw printf(" EXGPINTLV :%04x %04x %04x\n", t2, t1, t0); 270 1.2.10.2 nathanw } 271 1.2.10.2 nathanw #endif /* VRC2GPIODEBUG */ 272 1.2.10.2 nathanw 273 1.2.10.2 nathanw /* 274 1.2.10.2 nathanw * initialize register and internal data 275 1.2.10.2 nathanw */ 276 1.2.10.2 nathanw sc->sc_intr_mask = 0; 277 1.2.10.2 nathanw write_2(sc, VRC2_EXGPINTEN, sc->sc_intr_mask); 278 1.2.10.2 nathanw for (i = 0; i < VRC2_EXGP_NPORTS; i++) 279 1.2.10.2 nathanw TAILQ_INIT(&sc->sc_intr_head[i]); 280 1.2.10.2 nathanw sc->sc_data = read_4(sc, VRC2_EXGPDATA); 281 1.2.10.2 nathanw if (bootverbose || DBG(DBG_INFO)) { 282 1.2.10.2 nathanw u_int32_t data; 283 1.2.10.2 nathanw 284 1.2.10.2 nathanw sc->sc_intr_mask = (~read_4(sc, VRC2_EXGPDIR) & 0xffffff); 285 1.2.10.2 nathanw write_4(sc, VRC2_EXGPINTTYP, 0); /* level sence interrupt */ 286 1.2.10.2 nathanw data = ~read_4(sc, VRC2_EXGPDATA); 287 1.2.10.2 nathanw write_2(sc, VRC2_EXGPINTLV0L, (data >> 0) & 0xff); 288 1.2.10.2 nathanw write_2(sc, VRC2_EXGPINTLV0H, (data >> 8) & 0xff); 289 1.2.10.2 nathanw write_2(sc, VRC2_EXGPINTLV1L, (data >> 16) & 0xff); 290 1.2.10.2 nathanw } 291 1.2.10.2 nathanw 292 1.2.10.2 nathanw /* 293 1.2.10.2 nathanw * install interrupt handler 294 1.2.10.2 nathanw */ 295 1.2.10.2 nathanw port = loc[HPCIOIFCF_PORT]; 296 1.2.10.2 nathanw mode = HPCIO_INTR_LEVEL | HPCIO_INTR_HIGH; 297 1.2.10.2 nathanw sc->sc_intr_handle = 298 1.2.10.2 nathanw hpcio_intr_establish(sc->sc_hc, port, mode, vrc4172gpio_intr, sc); 299 1.2.10.2 nathanw if (sc->sc_intr_handle == NULL) { 300 1.2.10.2 nathanw printf("%s: can't establish interrupt\n", sc->sc_dev.dv_xname); 301 1.2.10.2 nathanw return; 302 1.2.10.2 nathanw } 303 1.2.10.2 nathanw 304 1.2.10.2 nathanw /* 305 1.2.10.2 nathanw * fill hpcio_chip structure 306 1.2.10.2 nathanw */ 307 1.2.10.2 nathanw sc->sc_iochip = vrc4172gpio_iochip; /* structure copy */ 308 1.2.10.2 nathanw sc->sc_iochip.hc_chipid = VRIP_IOCHIP_VRC4172GPIO; 309 1.2.10.2 nathanw sc->sc_iochip.hc_name = sc->sc_dev.dv_xname; 310 1.2.10.2 nathanw sc->sc_iochip.hc_sc = sc; 311 1.2.10.2 nathanw /* Register functions to upper interface */ 312 1.2.10.2 nathanw hpcio_register_iochip(sc->sc_hc, &sc->sc_iochip); 313 1.2.10.2 nathanw 314 1.2.10.2 nathanw /* 315 1.2.10.2 nathanw * hpcio I/F 316 1.2.10.2 nathanw */ 317 1.2.10.2 nathanw sc->sc_haa.haa_busname = HPCIO_BUSNAME; 318 1.2.10.2 nathanw sc->sc_haa.haa_sc = sc; 319 1.2.10.2 nathanw sc->sc_haa.haa_getchip = vrc4172gpio_getchip; 320 1.2.10.2 nathanw sc->sc_haa.haa_iot = sc->sc_iot; 321 1.2.10.2 nathanw while (config_found(self, &sc->sc_haa, vrc4172gpio_print)) ; 322 1.2.10.2 nathanw /* 323 1.2.10.2 nathanw * GIU-ISA bridge 324 1.2.10.2 nathanw */ 325 1.2.10.2 nathanw #if 1 /* XXX Sometimes mounting root device failed. Why? XXX*/ 326 1.2.10.2 nathanw config_defer(self, vrc4172gpio_callback); 327 1.2.10.2 nathanw #else 328 1.2.10.2 nathanw vrc4172gpio_callback(self); 329 1.2.10.2 nathanw #endif 330 1.2.10.2 nathanw } 331 1.2.10.2 nathanw 332 1.2.10.2 nathanw void 333 1.2.10.2 nathanw vrc4172gpio_callback(struct device *self) 334 1.2.10.2 nathanw { 335 1.2.10.2 nathanw struct vrc4172gpio_softc *sc = (void*)self; 336 1.2.10.2 nathanw 337 1.2.10.2 nathanw sc->sc_haa.haa_busname = "vrisab"; 338 1.2.10.2 nathanw config_found(self, &sc->sc_haa, vrc4172gpio_print); 339 1.2.10.2 nathanw } 340 1.2.10.2 nathanw 341 1.2.10.2 nathanw int 342 1.2.10.2 nathanw vrc4172gpio_print(void *aux, const char *pnp) 343 1.2.10.2 nathanw { 344 1.2.10.2 nathanw if (pnp) 345 1.2.10.2 nathanw return (QUIET); 346 1.2.10.2 nathanw return (UNCONF); 347 1.2.10.2 nathanw } 348 1.2.10.2 nathanw 349 1.2.10.2 nathanw /* 350 1.2.10.2 nathanw * PORT 351 1.2.10.2 nathanw */ 352 1.2.10.2 nathanw int 353 1.2.10.2 nathanw vrc4172gpio_port_read(hpcio_chip_t hc, int port) 354 1.2.10.2 nathanw { 355 1.2.10.2 nathanw struct vrc4172gpio_softc *sc = hc->hc_sc; 356 1.2.10.2 nathanw int on; 357 1.2.10.2 nathanw 358 1.2.10.2 nathanw if (!CHECK_PORT(port)) 359 1.2.10.2 nathanw panic("%s: illegal gpio port", __FUNCTION__); 360 1.2.10.2 nathanw 361 1.2.10.2 nathanw on = (read_4(sc, VRC2_EXGPDATA) & (1 << port)); 362 1.2.10.2 nathanw 363 1.2.10.2 nathanw return (on ? 1 : 0); 364 1.2.10.2 nathanw } 365 1.2.10.2 nathanw 366 1.2.10.2 nathanw void 367 1.2.10.2 nathanw vrc4172gpio_port_write(hpcio_chip_t hc, int port, int onoff) 368 1.2.10.2 nathanw { 369 1.2.10.2 nathanw struct vrc4172gpio_softc *sc = hc->hc_sc; 370 1.2.10.2 nathanw u_int32_t data; 371 1.2.10.2 nathanw 372 1.2.10.2 nathanw if (!CHECK_PORT(port)) 373 1.2.10.2 nathanw panic("%s: illegal gpio port", __FUNCTION__); 374 1.2.10.2 nathanw data = read_4(sc, VRC2_EXGPDATA); 375 1.2.10.2 nathanw if (onoff) 376 1.2.10.2 nathanw data |= (1<<port); 377 1.2.10.2 nathanw else 378 1.2.10.2 nathanw data &= ~(1<<port); 379 1.2.10.2 nathanw write_4(sc, VRC2_EXGPDATA, data); 380 1.2.10.2 nathanw } 381 1.2.10.2 nathanw 382 1.2.10.2 nathanw void 383 1.2.10.2 nathanw vrc4172gpio_update(hpcio_chip_t hc) 384 1.2.10.2 nathanw { 385 1.2.10.2 nathanw } 386 1.2.10.2 nathanw 387 1.2.10.2 nathanw void 388 1.2.10.2 nathanw vrc4172gpio_intr_dump(struct vrc4172gpio_softc *sc, int port) 389 1.2.10.2 nathanw { 390 1.2.10.2 nathanw u_int32_t mask, mask2; 391 1.2.10.2 nathanw int intlv_reg; 392 1.2.10.2 nathanw 393 1.2.10.2 nathanw mask = (1 << port); 394 1.2.10.2 nathanw mask2 = (1 << (port % 8)); 395 1.2.10.2 nathanw intlv_reg = intlv_regs[port/8]; 396 1.2.10.2 nathanw 397 1.2.10.2 nathanw if (read_4(sc, VRC2_EXGPDIR) & mask) { 398 1.2.10.2 nathanw printf(" output"); 399 1.2.10.2 nathanw return; 400 1.2.10.2 nathanw } 401 1.2.10.2 nathanw printf(" input"); 402 1.2.10.2 nathanw 403 1.2.10.2 nathanw if (read_4(sc, VRC2_EXGPINTTYP) & mask) { 404 1.2.10.2 nathanw if (read_4(sc, intlv_reg) & (mask2 << 8)) { 405 1.2.10.2 nathanw printf(", both edge"); 406 1.2.10.2 nathanw } else { 407 1.2.10.2 nathanw if (read_4(sc, intlv_reg) & mask2) 408 1.2.10.2 nathanw printf(", positive edge"); 409 1.2.10.2 nathanw else 410 1.2.10.2 nathanw printf(", negative edge"); 411 1.2.10.2 nathanw } 412 1.2.10.2 nathanw } else { 413 1.2.10.2 nathanw if (read_4(sc, intlv_reg) & mask2) 414 1.2.10.2 nathanw printf(", high level"); 415 1.2.10.2 nathanw else 416 1.2.10.2 nathanw printf(", low level"); 417 1.2.10.2 nathanw } 418 1.2.10.2 nathanw } 419 1.2.10.2 nathanw 420 1.2.10.2 nathanw static void 421 1.2.10.2 nathanw vrc4172gpio_diffport(struct vrc4172gpio_softc *sc) 422 1.2.10.2 nathanw { 423 1.2.10.2 nathanw u_int32_t data; 424 1.2.10.2 nathanw data = read_4(sc, VRC2_EXGPDATA); 425 1.2.10.2 nathanw if (sc->sc_data != data) { 426 1.2.10.2 nathanw printf(" port# 321098765432109876543210\n"); 427 1.2.10.2 nathanw printf("vrc4172data:"); 428 1.2.10.2 nathanw dumpbits(&data, 1, 23, 0, "10\n"); 429 1.2.10.2 nathanw /* bits which changed */ 430 1.2.10.2 nathanw data = (data & ~sc->sc_data)|(~data & sc->sc_data); 431 1.2.10.2 nathanw printf(" "); 432 1.2.10.2 nathanw dumpbits(&data, 1, 23, 0, "^ \n"); 433 1.2.10.2 nathanw sc->sc_data = data; 434 1.2.10.2 nathanw } 435 1.2.10.2 nathanw } 436 1.2.10.2 nathanw 437 1.2.10.2 nathanw static void 438 1.2.10.2 nathanw dumpbits(u_int32_t *data, int ndata, int start, int end, const char *sym) 439 1.2.10.2 nathanw { 440 1.2.10.2 nathanw int i, j; 441 1.2.10.2 nathanw 442 1.2.10.2 nathanw if (start <= end) 443 1.2.10.2 nathanw panic("%s(%d): %s", __FILE__, __LINE__, __FUNCTION__); 444 1.2.10.2 nathanw 445 1.2.10.2 nathanw for (i = start; end <= i; i--) { 446 1.2.10.2 nathanw int d = 0; 447 1.2.10.2 nathanw for (j = 0; j < ndata; j++) 448 1.2.10.2 nathanw d = (d << 1) | ((data[j] & (1 << i)) ? 1 : 0); 449 1.2.10.2 nathanw printf("%c", sym[(1 << ndata) - d - 1]); 450 1.2.10.2 nathanw 451 1.2.10.2 nathanw } 452 1.2.10.2 nathanw if (sym[1<<ndata]) 453 1.2.10.2 nathanw printf("%c", sym[1<<ndata]); 454 1.2.10.2 nathanw } 455 1.2.10.2 nathanw 456 1.2.10.2 nathanw void 457 1.2.10.2 nathanw vrc4172gpio_dump(hpcio_chip_t hc) 458 1.2.10.2 nathanw { 459 1.2.10.2 nathanw } 460 1.2.10.2 nathanw 461 1.2.10.2 nathanw hpcio_chip_t 462 1.2.10.2 nathanw vrc4172gpio_getchip(void* scx, int chipid) 463 1.2.10.2 nathanw { 464 1.2.10.2 nathanw struct vrc4172gpio_softc *sc = scx; 465 1.2.10.2 nathanw 466 1.2.10.2 nathanw return (&sc->sc_iochip); 467 1.2.10.2 nathanw } 468 1.2.10.2 nathanw 469 1.2.10.2 nathanw /* 470 1.2.10.2 nathanw * Interrupt staff 471 1.2.10.2 nathanw */ 472 1.2.10.2 nathanw void * 473 1.2.10.2 nathanw vrc4172gpio_intr_establish( 474 1.2.10.2 nathanw hpcio_chip_t hc, 475 1.2.10.2 nathanw int port, /* GPIO pin # */ 476 1.2.10.2 nathanw int mode, /* GIU trigger setting */ 477 1.2.10.2 nathanw int (*ih_fun)(void*), 478 1.2.10.2 nathanw void *ih_arg) 479 1.2.10.2 nathanw { 480 1.2.10.2 nathanw struct vrc4172gpio_softc *sc = hc->hc_sc; 481 1.2.10.2 nathanw int s; 482 1.2.10.2 nathanw u_int32_t reg, mask, mask2; 483 1.2.10.2 nathanw struct vrc4172gpio_intr_entry *ih; 484 1.2.10.2 nathanw int intlv_reg; 485 1.2.10.2 nathanw 486 1.2.10.2 nathanw s = splhigh(); 487 1.2.10.2 nathanw 488 1.2.10.2 nathanw if (!CHECK_PORT(port)) 489 1.2.10.2 nathanw panic (__FUNCTION__": bogus interrupt line"); 490 1.2.10.2 nathanw if (sc->sc_intr_mode[port] && mode != sc->sc_intr_mode[port]) 491 1.2.10.2 nathanw panic (__FUNCTION__": bogus interrupt type"); 492 1.2.10.2 nathanw else 493 1.2.10.2 nathanw sc->sc_intr_mode[port] = mode; 494 1.2.10.2 nathanw 495 1.2.10.2 nathanw mask = (1 << port); 496 1.2.10.2 nathanw mask2 = (1 << (port % 8)); 497 1.2.10.2 nathanw intlv_reg = intlv_regs[port/8]; 498 1.2.10.2 nathanw 499 1.2.10.2 nathanw ih = malloc(sizeof(struct vrc4172gpio_intr_entry), M_DEVBUF, M_NOWAIT); 500 1.2.10.2 nathanw if (ih == NULL) 501 1.2.10.2 nathanw panic(__FUNCTION__": no memory"); 502 1.2.10.2 nathanw 503 1.2.10.2 nathanw ih->ih_port = port; 504 1.2.10.2 nathanw ih->ih_fun = ih_fun; 505 1.2.10.2 nathanw ih->ih_arg = ih_arg; 506 1.2.10.2 nathanw TAILQ_INSERT_TAIL(&sc->sc_intr_head[port], ih, ih_link); 507 1.2.10.2 nathanw 508 1.2.10.2 nathanw #ifdef VRC2GPIODEBUG 509 1.2.10.2 nathanw if (DBG(DBG_INFO)) { 510 1.2.10.2 nathanw printf("port %2d:", port); 511 1.2.10.2 nathanw vrc4172gpio_intr_dump(sc, port); 512 1.2.10.2 nathanw printf("->"); 513 1.2.10.2 nathanw } 514 1.2.10.2 nathanw #endif 515 1.2.10.2 nathanw 516 1.2.10.2 nathanw /* 517 1.2.10.2 nathanw * Setup registers 518 1.2.10.2 nathanw */ 519 1.2.10.2 nathanw /* I/O direction */ 520 1.2.10.2 nathanw reg = read_4(sc, VRC2_EXGPDIR); 521 1.2.10.2 nathanw reg &= ~mask; 522 1.2.10.2 nathanw write_4(sc, VRC2_EXGPDIR, reg); 523 1.2.10.2 nathanw 524 1.2.10.2 nathanw /* interrupt triger (level/edge) */ 525 1.2.10.2 nathanw reg = read_4(sc, VRC2_EXGPINTTYP); 526 1.2.10.2 nathanw if (mode & HPCIO_INTR_EDGE) 527 1.2.10.2 nathanw reg |= mask; /* edge */ 528 1.2.10.2 nathanw else 529 1.2.10.2 nathanw reg &= ~mask; /* level */ 530 1.2.10.2 nathanw write_4(sc, VRC2_EXGPINTTYP, reg); 531 1.2.10.2 nathanw 532 1.2.10.2 nathanw /* interrupt trigger option */ 533 1.2.10.2 nathanw reg = read_4(sc, intlv_reg); 534 1.2.10.2 nathanw if (mode & HPCIO_INTR_EDGE) { 535 1.2.10.2 nathanw switch (mode & (HPCIO_INTR_POSEDGE | HPCIO_INTR_NEGEDGE)) { 536 1.2.10.2 nathanw case HPCIO_INTR_POSEDGE: 537 1.2.10.2 nathanw reg &= ~(mask2 << 8); 538 1.2.10.2 nathanw reg |= mask2; 539 1.2.10.2 nathanw break; 540 1.2.10.2 nathanw case HPCIO_INTR_NEGEDGE: 541 1.2.10.2 nathanw reg &= ~(mask2 << 8); 542 1.2.10.2 nathanw reg &= ~mask2; 543 1.2.10.2 nathanw break; 544 1.2.10.2 nathanw case HPCIO_INTR_POSEDGE | HPCIO_INTR_NEGEDGE: 545 1.2.10.2 nathanw default: 546 1.2.10.2 nathanw reg |= (mask2 << 8); 547 1.2.10.2 nathanw break; 548 1.2.10.2 nathanw } 549 1.2.10.2 nathanw } else { 550 1.2.10.2 nathanw if (mode & HPCIO_INTR_HIGH) 551 1.2.10.2 nathanw reg |= mask2; /* high */ 552 1.2.10.2 nathanw else 553 1.2.10.2 nathanw reg &= ~mask2; /* low */ 554 1.2.10.2 nathanw } 555 1.2.10.2 nathanw write_4(sc, intlv_reg, reg); 556 1.2.10.2 nathanw 557 1.2.10.2 nathanw #ifdef VRC2GPIODEBUG 558 1.2.10.2 nathanw if (DBG(DBG_INFO)) { 559 1.2.10.2 nathanw vrc4172gpio_intr_dump(sc, port); 560 1.2.10.2 nathanw printf("\n"); 561 1.2.10.2 nathanw } 562 1.2.10.2 nathanw #endif 563 1.2.10.2 nathanw 564 1.2.10.2 nathanw /* XXX, Vrc4172 doesn't have register to set hold or through */ 565 1.2.10.2 nathanw 566 1.2.10.2 nathanw /* 567 1.2.10.2 nathanw * clear interrupt status and enable interrupt 568 1.2.10.2 nathanw */ 569 1.2.10.2 nathanw vrc4172gpio_intr_clear(&sc->sc_iochip, ih); 570 1.2.10.2 nathanw sc->sc_intr_mask |= mask; 571 1.2.10.2 nathanw write_4(sc, VRC2_EXGPINTEN, sc->sc_intr_mask); 572 1.2.10.2 nathanw 573 1.2.10.2 nathanw splx(s); 574 1.2.10.2 nathanw 575 1.2.10.2 nathanw DPRINTF(DBG_INFO, "\n"); 576 1.2.10.2 nathanw 577 1.2.10.2 nathanw return (ih); 578 1.2.10.2 nathanw } 579 1.2.10.2 nathanw 580 1.2.10.2 nathanw void 581 1.2.10.2 nathanw vrc4172gpio_intr_disestablish(hpcio_chip_t hc, void *arg) 582 1.2.10.2 nathanw { 583 1.2.10.2 nathanw struct vrc4172gpio_intr_entry *ihe = arg; 584 1.2.10.2 nathanw struct vrc4172gpio_softc *sc = hc->hc_sc; 585 1.2.10.2 nathanw int port = ihe->ih_port; 586 1.2.10.2 nathanw struct vrc4172gpio_intr_entry *ih; 587 1.2.10.2 nathanw int s; 588 1.2.10.2 nathanw 589 1.2.10.2 nathanw s = splhigh(); 590 1.2.10.2 nathanw TAILQ_FOREACH(ih, &sc->sc_intr_head[port], ih_link) { 591 1.2.10.2 nathanw if (ih == ihe) { 592 1.2.10.2 nathanw TAILQ_REMOVE(&sc->sc_intr_head[port], ih, ih_link); 593 1.2.10.2 nathanw free(ih, M_DEVBUF); 594 1.2.10.2 nathanw if (TAILQ_EMPTY(&sc->sc_intr_head[port])) { 595 1.2.10.2 nathanw /* disable interrupt */ 596 1.2.10.2 nathanw sc->sc_intr_mask &= ~(1<<port); 597 1.2.10.2 nathanw write_4(sc, VRC2_EXGPINTEN, 598 1.2.10.2 nathanw sc->sc_intr_mask); 599 1.2.10.2 nathanw } 600 1.2.10.2 nathanw splx(s); 601 1.2.10.2 nathanw return; 602 1.2.10.2 nathanw } 603 1.2.10.2 nathanw } 604 1.2.10.2 nathanw panic(__FUNCTION__": no such a handle."); 605 1.2.10.2 nathanw /* NOTREACHED */ 606 1.2.10.2 nathanw } 607 1.2.10.2 nathanw 608 1.2.10.2 nathanw /* Clear interrupt */ 609 1.2.10.2 nathanw void 610 1.2.10.2 nathanw vrc4172gpio_intr_clear(hpcio_chip_t hc, void *arg) 611 1.2.10.2 nathanw { 612 1.2.10.2 nathanw struct vrc4172gpio_softc *sc = hc->hc_sc; 613 1.2.10.2 nathanw struct vrc4172gpio_intr_entry *ihe = arg; 614 1.2.10.2 nathanw 615 1.2.10.2 nathanw write_4(sc, VRC2_EXGPINTST, 1 << ihe->ih_port); 616 1.2.10.2 nathanw write_4(sc, VRC2_EXGPINTST, 0); 617 1.2.10.2 nathanw } 618 1.2.10.2 nathanw 619 1.2.10.2 nathanw void 620 1.2.10.2 nathanw vrc4172gpio_register_iochip(hpcio_chip_t hc, hpcio_chip_t iochip) 621 1.2.10.2 nathanw { 622 1.2.10.2 nathanw struct vrc4172gpio_softc *sc = hc->hc_sc; 623 1.2.10.2 nathanw 624 1.2.10.2 nathanw hpcio_register_iochip(sc->sc_hc, iochip); 625 1.2.10.2 nathanw } 626 1.2.10.2 nathanw 627 1.2.10.2 nathanw /* interrupt handler */ 628 1.2.10.2 nathanw int 629 1.2.10.2 nathanw vrc4172gpio_intr(void *arg) 630 1.2.10.2 nathanw { 631 1.2.10.2 nathanw struct vrc4172gpio_softc *sc = arg; 632 1.2.10.2 nathanw int i; 633 1.2.10.2 nathanw u_int32_t reg; 634 1.2.10.2 nathanw 635 1.2.10.2 nathanw /* dispatch handler */ 636 1.2.10.2 nathanw reg = read_4(sc, VRC2_EXGPINTST); 637 1.2.10.2 nathanw DPRINTF(DBG_INTR, "%s: EXGPINTST=%06x\n", __FUNCTION__, reg); 638 1.2.10.2 nathanw for (i = 0; i < VRC2_EXGP_NPORTS; i++) { 639 1.2.10.2 nathanw if (reg & (1 << i)) { 640 1.2.10.2 nathanw register struct vrc4172gpio_intr_entry *ih; 641 1.2.10.2 nathanw 642 1.2.10.2 nathanw /* 643 1.2.10.2 nathanw * call interrupt handler 644 1.2.10.2 nathanw */ 645 1.2.10.2 nathanw TAILQ_FOREACH(ih, &sc->sc_intr_head[i], ih_link) { 646 1.2.10.2 nathanw ih->ih_fun(ih->ih_arg); 647 1.2.10.2 nathanw } 648 1.2.10.2 nathanw 649 1.2.10.2 nathanw /* 650 1.2.10.2 nathanw * disable interrupt if no handler is installed 651 1.2.10.2 nathanw */ 652 1.2.10.2 nathanw if (TAILQ_EMPTY(&sc->sc_intr_head[i])) { 653 1.2.10.2 nathanw sc->sc_intr_mask &= ~(1 << i); 654 1.2.10.2 nathanw write_2(sc, VRC2_EXGPINTEN, sc->sc_intr_mask); 655 1.2.10.2 nathanw 656 1.2.10.2 nathanw /* dump EXGPDATA bits which changed */ 657 1.2.10.2 nathanw if (bootverbose || DBG(DBG_INFO)) 658 1.2.10.2 nathanw vrc4172gpio_diffport(sc); 659 1.2.10.2 nathanw } 660 1.2.10.2 nathanw } 661 1.2.10.2 nathanw } 662 1.2.10.2 nathanw 663 1.2.10.2 nathanw return (0); 664 1.2.10.2 nathanw } 665
Indexes created Mon Oct 20 08:09:54 GMT 2025