vrc4172gpio.c revision 1.3
1 /* $NetBSD: vrc4172gpio.c,v 1.3 2002/01/27 14:18:12 takemura Exp $ */ 2 /*- 3 * Copyright (c) 2001 TAKEMRUA Shin. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. Neither the name of the project nor the names of its contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 */ 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/device.h> 34 #include <sys/malloc.h> 35 #include <sys/queue.h> 36 #include <sys/reboot.h> 37 #include <machine/bus.h> 38 #include <machine/platid.h> 39 #include <machine/platid_mask.h> 40 41 #include <dev/hpc/hpciovar.h> 42 43 #include <hpcmips/vr/vripif.h> 44 #include <hpcmips/vr/vripvar.h> 45 #include <hpcmips/vr/vrc4172gpioreg.h> 46 47 #include "locators.h" 48 49 #define VRC2GPIODEBUG 50 #ifdef VRC2GPIODEBUG 51 #define DBG_IO (1<<0) 52 #define DBG_INTR (1<<1) 53 #define DBG_INFO (1<<2) 54 #ifndef VRC2GPIODEBUG_CONF 55 #define VRC2GPIODEBUG_CONF 0 56 #endif /* VRC2GPIODEBUG_CONF */ 57 int vrc4172gpio_debug = VRC2GPIODEBUG_CONF; 58 #define DBG(flag) (vrc4172gpio_debug & (flag)) 59 #define DPRINTF(flag, arg...) do { \ 60 if (DBG(flag)) \ 61 printf(##arg); \ 62 } while (0) 63 #else 64 #define DBG(flag) (0) 65 #define DPRINTF(flag, arg...) do {} while(0) 66 #endif 67 #define VPRINTF(arg...) do { \ 68 if (bootverbose) \ 69 printf(##arg); \ 70 } while (0) 71 72 #define CHECK_PORT(x) (0 <= (x) && (x) < VRC2_EXGP_NPORTS) 73 74 struct vrc4172gpio_intr_entry { 75 int ih_port; 76 int (*ih_fun)(void*); 77 void *ih_arg; 78 TAILQ_ENTRY(vrc4172gpio_intr_entry) ih_link; 79 }; 80 81 struct vrc4172gpio_softc { 82 struct device sc_dev; 83 bus_space_tag_t sc_iot; 84 bus_space_handle_t sc_ioh; 85 struct hpcio_attach_args sc_args; 86 struct hpcio_chip *sc_hc; 87 88 void *sc_intr_handle; 89 u_int32_t sc_intr_mask; 90 u_int32_t sc_data; 91 u_int32_t sc_intr_mode[VRC2_EXGP_NPORTS]; 92 TAILQ_HEAD(, vrc4172gpio_intr_entry) sc_intr_head[VRC2_EXGP_NPORTS]; 93 struct hpcio_chip sc_iochip; 94 struct hpcio_attach_args sc_haa; 95 }; 96 97 int vrc4172gpio_match(struct device*, struct cfdata*, void*); 98 void vrc4172gpio_attach(struct device*, struct device*, void*); 99 void vrc4172gpio_callback(struct device *self); 100 int vrc4172gpio_intr(void*); 101 int vrc4172gpio_print(void*, const char*); 102 103 int vrc4172gpio_port_read(hpcio_chip_t, int); 104 void vrc4172gpio_port_write(hpcio_chip_t, int, int); 105 void *vrc4172gpio_intr_establish(hpcio_chip_t, int, int, int (*)(void *), void*); 106 void vrc4172gpio_intr_disestablish(hpcio_chip_t, void*); 107 void vrc4172gpio_intr_clear(hpcio_chip_t, void*); 108 void vrc4172gpio_register_iochip(hpcio_chip_t, hpcio_chip_t); 109 void vrc4172gpio_update(hpcio_chip_t); 110 void vrc4172gpio_dump(hpcio_chip_t); 111 void vrc4172gpio_intr_dump(struct vrc4172gpio_softc *, int); 112 hpcio_chip_t vrc4172gpio_getchip(void*, int); 113 static void vrc4172gpio_diffport(struct vrc4172gpio_softc *sc); 114 115 static u_int16_t read_2(struct vrc4172gpio_softc *, bus_addr_t); 116 static void write_2(struct vrc4172gpio_softc *, bus_addr_t, u_int16_t); 117 static u_int32_t read_4(struct vrc4172gpio_softc *, bus_addr_t); 118 static void write_4(struct vrc4172gpio_softc *, bus_addr_t, u_int32_t); 119 static void dumpbits(u_int32_t*, int, int, int, const char[2]); 120 121 static struct hpcio_chip vrc4172gpio_iochip = { 122 .hc_portread = vrc4172gpio_port_read, 123 .hc_portwrite = vrc4172gpio_port_write, 124 .hc_intr_establish = vrc4172gpio_intr_establish, 125 .hc_intr_disestablish = vrc4172gpio_intr_disestablish, 126 .hc_intr_clear = vrc4172gpio_intr_clear, 127 .hc_register_iochip = vrc4172gpio_register_iochip, 128 .hc_update = vrc4172gpio_update, 129 .hc_dump = vrc4172gpio_dump, 130 }; 131 132 static int intlv_regs[] = { 133 VRC2_EXGPINTLV0L, 134 VRC2_EXGPINTLV0H, 135 VRC2_EXGPINTLV1L 136 }; 137 138 struct cfattach vrc4172gpio_ca = { 139 sizeof(struct vrc4172gpio_softc), vrc4172gpio_match, vrc4172gpio_attach 140 }; 141 142 /* 143 * regster access method 144 */ 145 static inline u_int16_t 146 read_2(struct vrc4172gpio_softc *sc, bus_addr_t off) 147 { 148 return bus_space_read_2(sc->sc_iot, sc->sc_ioh, off); 149 } 150 151 static inline void 152 write_2(struct vrc4172gpio_softc *sc, bus_addr_t off, u_int16_t data) 153 { 154 bus_space_write_2(sc->sc_iot, sc->sc_ioh, off, data); 155 } 156 157 static u_int32_t 158 read_4(struct vrc4172gpio_softc *sc, bus_addr_t off) 159 { 160 u_int16_t reg0, reg1; 161 162 reg0 = read_2(sc, off); 163 reg1 = read_2(sc, off + VRC2_EXGP_OFFSET); 164 165 return (reg0|(reg1<<16)); 166 } 167 168 static void 169 write_4(struct vrc4172gpio_softc *sc, bus_addr_t off, u_int32_t data) 170 { 171 write_2(sc, off, data & 0xffff); 172 write_2(sc, off + VRC2_EXGP_OFFSET, (data>>16)&0xffff); 173 } 174 175 int 176 vrc4172gpio_match(struct device *parent, struct cfdata *cf, void *aux) 177 { 178 struct hpcio_attach_args *haa = aux; 179 platid_mask_t mask; 180 181 if (strcmp(haa->haa_busname, HPCIO_BUSNAME)) 182 return (0); 183 if (cf->cf_loc[HPCIOIFCF_PLATFORM] == 0) 184 return (0); 185 mask = PLATID_DEREF(cf->cf_loc[HPCIOIFCF_PLATFORM]); 186 187 return platid_match(&platid, &mask); 188 } 189 190 void 191 vrc4172gpio_attach(struct device *parent, struct device *self, void *aux) 192 { 193 struct hpcio_attach_args *args = aux; 194 struct vrc4172gpio_softc *sc = (void*)self; 195 int i, *loc, port, mode; 196 u_int32_t regs[6], t0, t1, t2; 197 198 printf("\n"); 199 loc = sc->sc_dev.dv_cfdata->cf_loc; 200 201 /* 202 * map bus space 203 */ 204 sc->sc_iot = args->haa_iot; 205 sc->sc_hc = (*args->haa_getchip)(args->haa_sc, loc[HPCIOIFCF_IOCHIP]); 206 sc->sc_args = *args; /* structure copy */ 207 bus_space_map(sc->sc_iot, loc[HPCIOIFCF_ADDR], loc[HPCIOIFCF_SIZE], 208 0 /* no cache */, &sc->sc_ioh); 209 if (sc->sc_ioh == NULL) { 210 printf("%s: can't map bus space\n", sc->sc_dev.dv_xname); 211 return; 212 } 213 214 /* 215 * dump Windows CE register setting 216 */ 217 regs[0] = read_4(sc, VRC2_EXGPDATA); 218 regs[1] = read_4(sc, VRC2_EXGPDIR); 219 regs[2] = read_4(sc, VRC2_EXGPINTEN); 220 regs[3] = read_4(sc, VRC2_EXGPINTTYP); 221 t0 = read_2(sc, VRC2_EXGPINTLV0L); 222 t1 = read_2(sc, VRC2_EXGPINTLV0H); 223 t2 = read_2(sc, VRC2_EXGPINTLV1L); 224 regs[4] = ((t2&0xff00)<<8) | (t1&0xff00) | ((t0&0xff00)>>8); 225 regs[5] = ((t2&0xff)<<16) | ((t1&0xff)<<8) | (t0&0xff); 226 227 if (bootverbose || DBG(DBG_INFO)) { 228 /* 229 * o: output 230 * i: input (no interrupt) 231 * H: level sense interrupt (active high) 232 * L: level sense interrupt (active low) 233 * B: both edge trigger interrupt 234 * P: positive edge trigger interrupt 235 * N: negative edge trigger interrupt 236 */ 237 printf(" port#:321098765432109876543210\n"); 238 printf(" EXGPDATA :"); 239 dumpbits(®s[0], 1, 23, 0, "10\n"); 240 printf("WIN setting:"); 241 dumpbits(®s[1], 5, 23, 0, 242 "oooo" /* dir=1 en=1 typ=1 */ 243 "oooo" /* dir=1 en=1 typ=0 */ 244 "oooo" /* dir=1 en=0 typ=1 */ 245 "oooo" /* dir=1 en=0 typ=0 */ 246 "BBPN" /* dir=0 en=1 typ=1 */ 247 "HLHL" /* dir=0 en=1 typ=0 */ 248 "iiii" /* dir=0 en=0 typ=1 */ 249 "iiii" /* dir=0 en=0 typ=0 */ 250 ); 251 printf("\n"); 252 } 253 #ifdef VRC2GPIODEBUG 254 if (DBG(DBG_INFO)) { 255 printf(" EXGPDIR :"); 256 dumpbits(®s[1], 1, 23, 0, "oi\n"); 257 258 printf(" EXGPINTEN :"); 259 dumpbits(®s[2], 1, 23, 0, "I-\n"); 260 261 printf(" EXGPINTTYP:"); 262 dumpbits(®s[3], 1, 23, 0, "EL\n"); 263 264 printf(" EXPIB :"); 265 dumpbits(®s[4], 1, 23, 0, "10\n"); 266 267 printf(" EXPIL :"); 268 dumpbits(®s[5], 1, 23, 0, "10\n"); 269 270 printf(" EXGPINTLV :%04x %04x %04x\n", t2, t1, t0); 271 } 272 #endif /* VRC2GPIODEBUG */ 273 274 /* 275 * initialize register and internal data 276 */ 277 sc->sc_intr_mask = 0; 278 write_2(sc, VRC2_EXGPINTEN, sc->sc_intr_mask); 279 for (i = 0; i < VRC2_EXGP_NPORTS; i++) 280 TAILQ_INIT(&sc->sc_intr_head[i]); 281 sc->sc_data = read_4(sc, VRC2_EXGPDATA); 282 if (bootverbose || DBG(DBG_INFO)) { 283 u_int32_t data; 284 285 sc->sc_intr_mask = (~read_4(sc, VRC2_EXGPDIR) & 0xffffff); 286 write_4(sc, VRC2_EXGPINTTYP, 0); /* level sence interrupt */ 287 data = ~read_4(sc, VRC2_EXGPDATA); 288 write_2(sc, VRC2_EXGPINTLV0L, (data >> 0) & 0xff); 289 write_2(sc, VRC2_EXGPINTLV0H, (data >> 8) & 0xff); 290 write_2(sc, VRC2_EXGPINTLV1L, (data >> 16) & 0xff); 291 } 292 293 /* 294 * install interrupt handler 295 */ 296 port = loc[HPCIOIFCF_PORT]; 297 mode = HPCIO_INTR_LEVEL | HPCIO_INTR_HIGH; 298 sc->sc_intr_handle = 299 hpcio_intr_establish(sc->sc_hc, port, mode, vrc4172gpio_intr, sc); 300 if (sc->sc_intr_handle == NULL) { 301 printf("%s: can't establish interrupt\n", sc->sc_dev.dv_xname); 302 return; 303 } 304 305 /* 306 * fill hpcio_chip structure 307 */ 308 sc->sc_iochip = vrc4172gpio_iochip; /* structure copy */ 309 sc->sc_iochip.hc_chipid = VRIP_IOCHIP_VRC4172GPIO; 310 sc->sc_iochip.hc_name = sc->sc_dev.dv_xname; 311 sc->sc_iochip.hc_sc = sc; 312 /* Register functions to upper interface */ 313 hpcio_register_iochip(sc->sc_hc, &sc->sc_iochip); 314 315 /* 316 * hpcio I/F 317 */ 318 sc->sc_haa.haa_busname = HPCIO_BUSNAME; 319 sc->sc_haa.haa_sc = sc; 320 sc->sc_haa.haa_getchip = vrc4172gpio_getchip; 321 sc->sc_haa.haa_iot = sc->sc_iot; 322 while (config_found(self, &sc->sc_haa, vrc4172gpio_print)) ; 323 /* 324 * GIU-ISA bridge 325 */ 326 #if 1 /* XXX Sometimes mounting root device failed. Why? XXX*/ 327 config_defer(self, vrc4172gpio_callback); 328 #else 329 vrc4172gpio_callback(self); 330 #endif 331 } 332 333 void 334 vrc4172gpio_callback(struct device *self) 335 { 336 struct vrc4172gpio_softc *sc = (void*)self; 337 338 sc->sc_haa.haa_busname = "vrisab"; 339 config_found(self, &sc->sc_haa, vrc4172gpio_print); 340 } 341 342 int 343 vrc4172gpio_print(void *aux, const char *pnp) 344 { 345 if (pnp) 346 return (QUIET); 347 return (UNCONF); 348 } 349 350 /* 351 * PORT 352 */ 353 int 354 vrc4172gpio_port_read(hpcio_chip_t hc, int port) 355 { 356 struct vrc4172gpio_softc *sc = hc->hc_sc; 357 int on; 358 359 if (!CHECK_PORT(port)) 360 panic("%s: illegal gpio port", __FUNCTION__); 361 362 on = (read_4(sc, VRC2_EXGPDATA) & (1 << port)); 363 364 return (on ? 1 : 0); 365 } 366 367 void 368 vrc4172gpio_port_write(hpcio_chip_t hc, int port, int onoff) 369 { 370 struct vrc4172gpio_softc *sc = hc->hc_sc; 371 u_int32_t data; 372 373 if (!CHECK_PORT(port)) 374 panic("%s: illegal gpio port", __FUNCTION__); 375 data = read_4(sc, VRC2_EXGPDATA); 376 if (onoff) 377 data |= (1<<port); 378 else 379 data &= ~(1<<port); 380 write_4(sc, VRC2_EXGPDATA, data); 381 } 382 383 void 384 vrc4172gpio_update(hpcio_chip_t hc) 385 { 386 } 387 388 void 389 vrc4172gpio_intr_dump(struct vrc4172gpio_softc *sc, int port) 390 { 391 u_int32_t mask, mask2; 392 int intlv_reg; 393 394 mask = (1 << port); 395 mask2 = (1 << (port % 8)); 396 intlv_reg = intlv_regs[port/8]; 397 398 if (read_4(sc, VRC2_EXGPDIR) & mask) { 399 printf(" output"); 400 return; 401 } 402 printf(" input"); 403 404 if (read_4(sc, VRC2_EXGPINTTYP) & mask) { 405 if (read_4(sc, intlv_reg) & (mask2 << 8)) { 406 printf(", both edge"); 407 } else { 408 if (read_4(sc, intlv_reg) & mask2) 409 printf(", positive edge"); 410 else 411 printf(", negative edge"); 412 } 413 } else { 414 if (read_4(sc, intlv_reg) & mask2) 415 printf(", high level"); 416 else 417 printf(", low level"); 418 } 419 } 420 421 static void 422 vrc4172gpio_diffport(struct vrc4172gpio_softc *sc) 423 { 424 u_int32_t data; 425 data = read_4(sc, VRC2_EXGPDATA); 426 if (sc->sc_data != data) { 427 printf(" port# 321098765432109876543210\n"); 428 printf("vrc4172data:"); 429 dumpbits(&data, 1, 23, 0, "10\n"); 430 /* bits which changed */ 431 data = (data & ~sc->sc_data)|(~data & sc->sc_data); 432 printf(" "); 433 dumpbits(&data, 1, 23, 0, "^ \n"); 434 sc->sc_data = data; 435 } 436 } 437 438 static void 439 dumpbits(u_int32_t *data, int ndata, int start, int end, const char *sym) 440 { 441 int i, j; 442 443 if (start <= end) 444 panic("%s(%d): %s", __FILE__, __LINE__, __FUNCTION__); 445 446 for (i = start; end <= i; i--) { 447 int d = 0; 448 for (j = 0; j < ndata; j++) 449 d = (d << 1) | ((data[j] & (1 << i)) ? 1 : 0); 450 printf("%c", sym[(1 << ndata) - d - 1]); 451 452 } 453 if (sym[1<<ndata]) 454 printf("%c", sym[1<<ndata]); 455 } 456 457 void 458 vrc4172gpio_dump(hpcio_chip_t hc) 459 { 460 } 461 462 hpcio_chip_t 463 vrc4172gpio_getchip(void* scx, int chipid) 464 { 465 struct vrc4172gpio_softc *sc = scx; 466 467 return (&sc->sc_iochip); 468 } 469 470 /* 471 * Interrupt staff 472 */ 473 void * 474 vrc4172gpio_intr_establish( 475 hpcio_chip_t hc, 476 int port, /* GPIO pin # */ 477 int mode, /* GIU trigger setting */ 478 int (*ih_fun)(void*), 479 void *ih_arg) 480 { 481 struct vrc4172gpio_softc *sc = hc->hc_sc; 482 int s; 483 u_int32_t reg, mask, mask2; 484 struct vrc4172gpio_intr_entry *ih; 485 int intlv_reg; 486 487 s = splhigh(); 488 489 if (!CHECK_PORT(port)) 490 panic (__FUNCTION__": bogus interrupt line"); 491 if (sc->sc_intr_mode[port] && mode != sc->sc_intr_mode[port]) 492 panic (__FUNCTION__": bogus interrupt type"); 493 else 494 sc->sc_intr_mode[port] = mode; 495 496 mask = (1 << port); 497 mask2 = (1 << (port % 8)); 498 intlv_reg = intlv_regs[port/8]; 499 500 ih = malloc(sizeof(struct vrc4172gpio_intr_entry), M_DEVBUF, M_NOWAIT); 501 if (ih == NULL) 502 panic(__FUNCTION__": no memory"); 503 504 ih->ih_port = port; 505 ih->ih_fun = ih_fun; 506 ih->ih_arg = ih_arg; 507 TAILQ_INSERT_TAIL(&sc->sc_intr_head[port], ih, ih_link); 508 509 #ifdef VRC2GPIODEBUG 510 if (DBG(DBG_INFO)) { 511 printf("port %2d:", port); 512 vrc4172gpio_intr_dump(sc, port); 513 printf("->"); 514 } 515 #endif 516 517 /* 518 * Setup registers 519 */ 520 /* I/O direction */ 521 reg = read_4(sc, VRC2_EXGPDIR); 522 reg &= ~mask; 523 write_4(sc, VRC2_EXGPDIR, reg); 524 525 /* interrupt triger (level/edge) */ 526 reg = read_4(sc, VRC2_EXGPINTTYP); 527 if (mode & HPCIO_INTR_EDGE) 528 reg |= mask; /* edge */ 529 else 530 reg &= ~mask; /* level */ 531 write_4(sc, VRC2_EXGPINTTYP, reg); 532 533 /* interrupt trigger option */ 534 reg = read_4(sc, intlv_reg); 535 if (mode & HPCIO_INTR_EDGE) { 536 switch (mode & (HPCIO_INTR_POSEDGE | HPCIO_INTR_NEGEDGE)) { 537 case HPCIO_INTR_POSEDGE: 538 reg &= ~(mask2 << 8); 539 reg |= mask2; 540 break; 541 case HPCIO_INTR_NEGEDGE: 542 reg &= ~(mask2 << 8); 543 reg &= ~mask2; 544 break; 545 case HPCIO_INTR_POSEDGE | HPCIO_INTR_NEGEDGE: 546 default: 547 reg |= (mask2 << 8); 548 break; 549 } 550 } else { 551 if (mode & HPCIO_INTR_HIGH) 552 reg |= mask2; /* high */ 553 else 554 reg &= ~mask2; /* low */ 555 } 556 write_4(sc, intlv_reg, reg); 557 558 #ifdef VRC2GPIODEBUG 559 if (DBG(DBG_INFO)) { 560 vrc4172gpio_intr_dump(sc, port); 561 printf("\n"); 562 } 563 #endif 564 565 /* XXX, Vrc4172 doesn't have register to set hold or through */ 566 567 /* 568 * clear interrupt status and enable interrupt 569 */ 570 vrc4172gpio_intr_clear(&sc->sc_iochip, ih); 571 sc->sc_intr_mask |= mask; 572 write_4(sc, VRC2_EXGPINTEN, sc->sc_intr_mask); 573 574 splx(s); 575 576 DPRINTF(DBG_INFO, "\n"); 577 578 return (ih); 579 } 580 581 void 582 vrc4172gpio_intr_disestablish(hpcio_chip_t hc, void *arg) 583 { 584 struct vrc4172gpio_intr_entry *ihe = arg; 585 struct vrc4172gpio_softc *sc = hc->hc_sc; 586 int port = ihe->ih_port; 587 struct vrc4172gpio_intr_entry *ih; 588 int s; 589 590 s = splhigh(); 591 TAILQ_FOREACH(ih, &sc->sc_intr_head[port], ih_link) { 592 if (ih == ihe) { 593 TAILQ_REMOVE(&sc->sc_intr_head[port], ih, ih_link); 594 free(ih, M_DEVBUF); 595 if (TAILQ_EMPTY(&sc->sc_intr_head[port])) { 596 /* disable interrupt */ 597 sc->sc_intr_mask &= ~(1<<port); 598 write_4(sc, VRC2_EXGPINTEN, 599 sc->sc_intr_mask); 600 } 601 splx(s); 602 return; 603 } 604 } 605 panic(__FUNCTION__": no such a handle."); 606 /* NOTREACHED */ 607 } 608 609 /* Clear interrupt */ 610 void 611 vrc4172gpio_intr_clear(hpcio_chip_t hc, void *arg) 612 { 613 struct vrc4172gpio_softc *sc = hc->hc_sc; 614 struct vrc4172gpio_intr_entry *ihe = arg; 615 616 write_4(sc, VRC2_EXGPINTST, 1 << ihe->ih_port); 617 write_4(sc, VRC2_EXGPINTST, 0); 618 } 619 620 void 621 vrc4172gpio_register_iochip(hpcio_chip_t hc, hpcio_chip_t iochip) 622 { 623 struct vrc4172gpio_softc *sc = hc->hc_sc; 624 625 hpcio_register_iochip(sc->sc_hc, iochip); 626 } 627 628 /* interrupt handler */ 629 int 630 vrc4172gpio_intr(void *arg) 631 { 632 struct vrc4172gpio_softc *sc = arg; 633 int i; 634 u_int32_t reg; 635 636 /* dispatch handler */ 637 reg = read_4(sc, VRC2_EXGPINTST); 638 DPRINTF(DBG_INTR, "%s: EXGPINTST=%06x\n", __FUNCTION__, reg); 639 for (i = 0; i < VRC2_EXGP_NPORTS; i++) { 640 if (reg & (1 << i)) { 641 register struct vrc4172gpio_intr_entry *ih; 642 643 /* 644 * call interrupt handler 645 */ 646 TAILQ_FOREACH(ih, &sc->sc_intr_head[i], ih_link) { 647 ih->ih_fun(ih->ih_arg); 648 } 649 650 /* 651 * disable interrupt if no handler is installed 652 */ 653 if (TAILQ_EMPTY(&sc->sc_intr_head[i])) { 654 sc->sc_intr_mask &= ~(1 << i); 655 write_2(sc, VRC2_EXGPINTEN, sc->sc_intr_mask); 656 657 /* dump EXGPDATA bits which changed */ 658 if (bootverbose || DBG(DBG_INFO)) 659 vrc4172gpio_diffport(sc); 660 } 661 } 662 } 663 664 return (0); 665 } 666
Indexes created Mon Sep 29 21:09:56 GMT 2025