vrc4172gpio.c revision 1.5
1 /* $NetBSD: vrc4172gpio.c,v 1.5 2002/10/02 05:26:54 thorpej Exp $ */ 2 /*- 3 * Copyright (c) 2001 TAKEMRUA Shin. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. Neither the name of the project nor the names of its contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 */ 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/device.h> 34 #include <sys/malloc.h> 35 #include <sys/queue.h> 36 #include <sys/reboot.h> 37 #include <machine/bus.h> 38 #include <machine/platid.h> 39 #include <machine/platid_mask.h> 40 41 #include <dev/hpc/hpciovar.h> 42 43 #include <hpcmips/vr/vripif.h> 44 #include <hpcmips/vr/vripvar.h> 45 #include <hpcmips/vr/vrc4172gpioreg.h> 46 47 #include "locators.h" 48 49 #define VRC2GPIODEBUG 50 #ifdef VRC2GPIODEBUG 51 #define DBG_IO (1<<0) 52 #define DBG_INTR (1<<1) 53 #define DBG_INFO (1<<2) 54 #ifndef VRC2GPIODEBUG_CONF 55 #define VRC2GPIODEBUG_CONF 0 56 #endif /* VRC2GPIODEBUG_CONF */ 57 int vrc4172gpio_debug = VRC2GPIODEBUG_CONF; 58 #define DBG(flag) (vrc4172gpio_debug & (flag)) 59 #define DPRINTF(flag, arg...) do { \ 60 if (DBG(flag)) \ 61 printf(##arg); \ 62 } while (0) 63 #else 64 #define DBG(flag) (0) 65 #define DPRINTF(flag, arg...) do {} while(0) 66 #endif 67 #define VPRINTF(arg...) do { \ 68 if (bootverbose) \ 69 printf(##arg); \ 70 } while (0) 71 72 #define CHECK_PORT(x) (0 <= (x) && (x) < VRC2_EXGP_NPORTS) 73 74 struct vrc4172gpio_intr_entry { 75 int ih_port; 76 int (*ih_fun)(void*); 77 void *ih_arg; 78 TAILQ_ENTRY(vrc4172gpio_intr_entry) ih_link; 79 }; 80 81 struct vrc4172gpio_softc { 82 struct device sc_dev; 83 bus_space_tag_t sc_iot; 84 bus_space_handle_t sc_ioh; 85 struct hpcio_attach_args sc_args; 86 struct hpcio_chip *sc_hc; 87 88 void *sc_intr_handle; 89 u_int32_t sc_intr_mask; 90 u_int32_t sc_data; 91 u_int32_t sc_intr_mode[VRC2_EXGP_NPORTS]; 92 TAILQ_HEAD(, vrc4172gpio_intr_entry) sc_intr_head[VRC2_EXGP_NPORTS]; 93 struct hpcio_chip sc_iochip; 94 struct hpcio_attach_args sc_haa; 95 }; 96 97 int vrc4172gpio_match(struct device*, struct cfdata*, void*); 98 void vrc4172gpio_attach(struct device*, struct device*, void*); 99 void vrc4172gpio_callback(struct device *self); 100 int vrc4172gpio_intr(void*); 101 int vrc4172gpio_print(void*, const char*); 102 103 int vrc4172gpio_port_read(hpcio_chip_t, int); 104 void vrc4172gpio_port_write(hpcio_chip_t, int, int); 105 void *vrc4172gpio_intr_establish(hpcio_chip_t, int, int, int (*)(void *), void*); 106 void vrc4172gpio_intr_disestablish(hpcio_chip_t, void*); 107 void vrc4172gpio_intr_clear(hpcio_chip_t, void*); 108 void vrc4172gpio_register_iochip(hpcio_chip_t, hpcio_chip_t); 109 void vrc4172gpio_update(hpcio_chip_t); 110 void vrc4172gpio_dump(hpcio_chip_t); 111 void vrc4172gpio_intr_dump(struct vrc4172gpio_softc *, int); 112 hpcio_chip_t vrc4172gpio_getchip(void*, int); 113 static void vrc4172gpio_diffport(struct vrc4172gpio_softc *sc); 114 115 static u_int16_t read_2(struct vrc4172gpio_softc *, bus_addr_t); 116 static void write_2(struct vrc4172gpio_softc *, bus_addr_t, u_int16_t); 117 static u_int32_t read_4(struct vrc4172gpio_softc *, bus_addr_t); 118 static void write_4(struct vrc4172gpio_softc *, bus_addr_t, u_int32_t); 119 static void dumpbits(u_int32_t*, int, int, int, const char[2]); 120 121 static struct hpcio_chip vrc4172gpio_iochip = { 122 .hc_portread = vrc4172gpio_port_read, 123 .hc_portwrite = vrc4172gpio_port_write, 124 .hc_intr_establish = vrc4172gpio_intr_establish, 125 .hc_intr_disestablish = vrc4172gpio_intr_disestablish, 126 .hc_intr_clear = vrc4172gpio_intr_clear, 127 .hc_register_iochip = vrc4172gpio_register_iochip, 128 .hc_update = vrc4172gpio_update, 129 .hc_dump = vrc4172gpio_dump, 130 }; 131 132 static int intlv_regs[] = { 133 VRC2_EXGPINTLV0L, 134 VRC2_EXGPINTLV0H, 135 VRC2_EXGPINTLV1L 136 }; 137 138 CFATTACH_DECL(vrc4172gpio, sizeof(struct vrc4172gpio_softc), 139 vrc4172gpio_match, vrc4172gpio_attach, NULL, NULL); 140 141 /* 142 * regster access method 143 */ 144 static inline u_int16_t 145 read_2(struct vrc4172gpio_softc *sc, bus_addr_t off) 146 { 147 return bus_space_read_2(sc->sc_iot, sc->sc_ioh, off); 148 } 149 150 static inline void 151 write_2(struct vrc4172gpio_softc *sc, bus_addr_t off, u_int16_t data) 152 { 153 bus_space_write_2(sc->sc_iot, sc->sc_ioh, off, data); 154 } 155 156 static u_int32_t 157 read_4(struct vrc4172gpio_softc *sc, bus_addr_t off) 158 { 159 u_int16_t reg0, reg1; 160 161 reg0 = read_2(sc, off); 162 reg1 = read_2(sc, off + VRC2_EXGP_OFFSET); 163 164 return (reg0|(reg1<<16)); 165 } 166 167 static void 168 write_4(struct vrc4172gpio_softc *sc, bus_addr_t off, u_int32_t data) 169 { 170 write_2(sc, off, data & 0xffff); 171 write_2(sc, off + VRC2_EXGP_OFFSET, (data>>16)&0xffff); 172 } 173 174 int 175 vrc4172gpio_match(struct device *parent, struct cfdata *cf, void *aux) 176 { 177 struct hpcio_attach_args *haa = aux; 178 platid_mask_t mask; 179 180 if (strcmp(haa->haa_busname, HPCIO_BUSNAME)) 181 return (0); 182 if (cf->cf_loc[HPCIOIFCF_PLATFORM] == 0) 183 return (0); 184 mask = PLATID_DEREF(cf->cf_loc[HPCIOIFCF_PLATFORM]); 185 186 return platid_match(&platid, &mask); 187 } 188 189 void 190 vrc4172gpio_attach(struct device *parent, struct device *self, void *aux) 191 { 192 struct hpcio_attach_args *args = aux; 193 struct vrc4172gpio_softc *sc = (void*)self; 194 int i, *loc, port, mode; 195 u_int32_t regs[6], t0, t1, t2; 196 197 printf("\n"); 198 loc = sc->sc_dev.dv_cfdata->cf_loc; 199 200 /* 201 * map bus space 202 */ 203 sc->sc_iot = args->haa_iot; 204 sc->sc_hc = (*args->haa_getchip)(args->haa_sc, loc[HPCIOIFCF_IOCHIP]); 205 sc->sc_args = *args; /* structure copy */ 206 bus_space_map(sc->sc_iot, loc[HPCIOIFCF_ADDR], loc[HPCIOIFCF_SIZE], 207 0 /* no cache */, &sc->sc_ioh); 208 if (sc->sc_ioh == NULL) { 209 printf("%s: can't map bus space\n", sc->sc_dev.dv_xname); 210 return; 211 } 212 213 /* 214 * dump Windows CE register setting 215 */ 216 regs[0] = read_4(sc, VRC2_EXGPDATA); 217 regs[1] = read_4(sc, VRC2_EXGPDIR); 218 regs[2] = read_4(sc, VRC2_EXGPINTEN); 219 regs[3] = read_4(sc, VRC2_EXGPINTTYP); 220 t0 = read_2(sc, VRC2_EXGPINTLV0L); 221 t1 = read_2(sc, VRC2_EXGPINTLV0H); 222 t2 = read_2(sc, VRC2_EXGPINTLV1L); 223 regs[4] = ((t2&0xff00)<<8) | (t1&0xff00) | ((t0&0xff00)>>8); 224 regs[5] = ((t2&0xff)<<16) | ((t1&0xff)<<8) | (t0&0xff); 225 226 if (bootverbose || DBG(DBG_INFO)) { 227 /* 228 * o: output 229 * i: input (no interrupt) 230 * H: level sense interrupt (active high) 231 * L: level sense interrupt (active low) 232 * B: both edge trigger interrupt 233 * P: positive edge trigger interrupt 234 * N: negative edge trigger interrupt 235 */ 236 printf(" port#:321098765432109876543210\n"); 237 printf(" EXGPDATA :"); 238 dumpbits(®s[0], 1, 23, 0, "10\n"); 239 printf("WIN setting:"); 240 dumpbits(®s[1], 5, 23, 0, 241 "oooo" /* dir=1 en=1 typ=1 */ 242 "oooo" /* dir=1 en=1 typ=0 */ 243 "oooo" /* dir=1 en=0 typ=1 */ 244 "oooo" /* dir=1 en=0 typ=0 */ 245 "BBPN" /* dir=0 en=1 typ=1 */ 246 "HLHL" /* dir=0 en=1 typ=0 */ 247 "iiii" /* dir=0 en=0 typ=1 */ 248 "iiii" /* dir=0 en=0 typ=0 */ 249 ); 250 printf("\n"); 251 } 252 #ifdef VRC2GPIODEBUG 253 if (DBG(DBG_INFO)) { 254 printf(" EXGPDIR :"); 255 dumpbits(®s[1], 1, 23, 0, "oi\n"); 256 257 printf(" EXGPINTEN :"); 258 dumpbits(®s[2], 1, 23, 0, "I-\n"); 259 260 printf(" EXGPINTTYP:"); 261 dumpbits(®s[3], 1, 23, 0, "EL\n"); 262 263 printf(" EXPIB :"); 264 dumpbits(®s[4], 1, 23, 0, "10\n"); 265 266 printf(" EXPIL :"); 267 dumpbits(®s[5], 1, 23, 0, "10\n"); 268 269 printf(" EXGPINTLV :%04x %04x %04x\n", t2, t1, t0); 270 } 271 #endif /* VRC2GPIODEBUG */ 272 273 /* 274 * initialize register and internal data 275 */ 276 sc->sc_intr_mask = 0; 277 write_2(sc, VRC2_EXGPINTEN, sc->sc_intr_mask); 278 for (i = 0; i < VRC2_EXGP_NPORTS; i++) 279 TAILQ_INIT(&sc->sc_intr_head[i]); 280 sc->sc_data = read_4(sc, VRC2_EXGPDATA); 281 if (bootverbose || DBG(DBG_INFO)) { 282 u_int32_t data; 283 284 sc->sc_intr_mask = (~read_4(sc, VRC2_EXGPDIR) & 0xffffff); 285 write_4(sc, VRC2_EXGPINTTYP, 0); /* level sence interrupt */ 286 data = ~read_4(sc, VRC2_EXGPDATA); 287 write_2(sc, VRC2_EXGPINTLV0L, (data >> 0) & 0xff); 288 write_2(sc, VRC2_EXGPINTLV0H, (data >> 8) & 0xff); 289 write_2(sc, VRC2_EXGPINTLV1L, (data >> 16) & 0xff); 290 } 291 292 /* 293 * install interrupt handler 294 */ 295 port = loc[HPCIOIFCF_PORT]; 296 mode = HPCIO_INTR_LEVEL | HPCIO_INTR_HIGH; 297 sc->sc_intr_handle = 298 hpcio_intr_establish(sc->sc_hc, port, mode, vrc4172gpio_intr, sc); 299 if (sc->sc_intr_handle == NULL) { 300 printf("%s: can't establish interrupt\n", sc->sc_dev.dv_xname); 301 return; 302 } 303 304 /* 305 * fill hpcio_chip structure 306 */ 307 sc->sc_iochip = vrc4172gpio_iochip; /* structure copy */ 308 sc->sc_iochip.hc_chipid = VRIP_IOCHIP_VRC4172GPIO; 309 sc->sc_iochip.hc_name = sc->sc_dev.dv_xname; 310 sc->sc_iochip.hc_sc = sc; 311 /* Register functions to upper interface */ 312 hpcio_register_iochip(sc->sc_hc, &sc->sc_iochip); 313 314 /* 315 * hpcio I/F 316 */ 317 sc->sc_haa.haa_busname = HPCIO_BUSNAME; 318 sc->sc_haa.haa_sc = sc; 319 sc->sc_haa.haa_getchip = vrc4172gpio_getchip; 320 sc->sc_haa.haa_iot = sc->sc_iot; 321 while (config_found(self, &sc->sc_haa, vrc4172gpio_print)) ; 322 /* 323 * GIU-ISA bridge 324 */ 325 #if 1 /* XXX Sometimes mounting root device failed. Why? XXX*/ 326 config_defer(self, vrc4172gpio_callback); 327 #else 328 vrc4172gpio_callback(self); 329 #endif 330 } 331 332 void 333 vrc4172gpio_callback(struct device *self) 334 { 335 struct vrc4172gpio_softc *sc = (void*)self; 336 337 sc->sc_haa.haa_busname = "vrisab"; 338 config_found(self, &sc->sc_haa, vrc4172gpio_print); 339 } 340 341 int 342 vrc4172gpio_print(void *aux, const char *pnp) 343 { 344 if (pnp) 345 return (QUIET); 346 return (UNCONF); 347 } 348 349 /* 350 * PORT 351 */ 352 int 353 vrc4172gpio_port_read(hpcio_chip_t hc, int port) 354 { 355 struct vrc4172gpio_softc *sc = hc->hc_sc; 356 int on; 357 358 if (!CHECK_PORT(port)) 359 panic("%s: illegal gpio port", __FUNCTION__); 360 361 on = (read_4(sc, VRC2_EXGPDATA) & (1 << port)); 362 363 return (on ? 1 : 0); 364 } 365 366 void 367 vrc4172gpio_port_write(hpcio_chip_t hc, int port, int onoff) 368 { 369 struct vrc4172gpio_softc *sc = hc->hc_sc; 370 u_int32_t data; 371 372 if (!CHECK_PORT(port)) 373 panic("%s: illegal gpio port", __FUNCTION__); 374 data = read_4(sc, VRC2_EXGPDATA); 375 if (onoff) 376 data |= (1<<port); 377 else 378 data &= ~(1<<port); 379 write_4(sc, VRC2_EXGPDATA, data); 380 } 381 382 void 383 vrc4172gpio_update(hpcio_chip_t hc) 384 { 385 } 386 387 void 388 vrc4172gpio_intr_dump(struct vrc4172gpio_softc *sc, int port) 389 { 390 u_int32_t mask, mask2; 391 int intlv_reg; 392 393 mask = (1 << port); 394 mask2 = (1 << (port % 8)); 395 intlv_reg = intlv_regs[port/8]; 396 397 if (read_4(sc, VRC2_EXGPDIR) & mask) { 398 printf(" output"); 399 return; 400 } 401 printf(" input"); 402 403 if (read_4(sc, VRC2_EXGPINTTYP) & mask) { 404 if (read_4(sc, intlv_reg) & (mask2 << 8)) { 405 printf(", both edge"); 406 } else { 407 if (read_4(sc, intlv_reg) & mask2) 408 printf(", positive edge"); 409 else 410 printf(", negative edge"); 411 } 412 } else { 413 if (read_4(sc, intlv_reg) & mask2) 414 printf(", high level"); 415 else 416 printf(", low level"); 417 } 418 } 419 420 static void 421 vrc4172gpio_diffport(struct vrc4172gpio_softc *sc) 422 { 423 u_int32_t data; 424 data = read_4(sc, VRC2_EXGPDATA); 425 if (sc->sc_data != data) { 426 printf(" port# 321098765432109876543210\n"); 427 printf("vrc4172data:"); 428 dumpbits(&data, 1, 23, 0, "10\n"); 429 /* bits which changed */ 430 data = (data & ~sc->sc_data)|(~data & sc->sc_data); 431 printf(" "); 432 dumpbits(&data, 1, 23, 0, "^ \n"); 433 sc->sc_data = data; 434 } 435 } 436 437 static void 438 dumpbits(u_int32_t *data, int ndata, int start, int end, const char *sym) 439 { 440 int i, j; 441 442 if (start <= end) 443 panic("%s(%d): %s", __FILE__, __LINE__, __FUNCTION__); 444 445 for (i = start; end <= i; i--) { 446 int d = 0; 447 for (j = 0; j < ndata; j++) 448 d = (d << 1) | ((data[j] & (1 << i)) ? 1 : 0); 449 printf("%c", sym[(1 << ndata) - d - 1]); 450 451 } 452 if (sym[1<<ndata]) 453 printf("%c", sym[1<<ndata]); 454 } 455 456 void 457 vrc4172gpio_dump(hpcio_chip_t hc) 458 { 459 } 460 461 hpcio_chip_t 462 vrc4172gpio_getchip(void* scx, int chipid) 463 { 464 struct vrc4172gpio_softc *sc = scx; 465 466 return (&sc->sc_iochip); 467 } 468 469 /* 470 * Interrupt staff 471 */ 472 void * 473 vrc4172gpio_intr_establish( 474 hpcio_chip_t hc, 475 int port, /* GPIO pin # */ 476 int mode, /* GIU trigger setting */ 477 int (*ih_fun)(void*), 478 void *ih_arg) 479 { 480 struct vrc4172gpio_softc *sc = hc->hc_sc; 481 int s; 482 u_int32_t reg, mask, mask2; 483 struct vrc4172gpio_intr_entry *ih; 484 int intlv_reg; 485 486 s = splhigh(); 487 488 if (!CHECK_PORT(port)) 489 panic (__FUNCTION__": bogus interrupt line"); 490 if (sc->sc_intr_mode[port] && mode != sc->sc_intr_mode[port]) 491 panic (__FUNCTION__": bogus interrupt type"); 492 else 493 sc->sc_intr_mode[port] = mode; 494 495 mask = (1 << port); 496 mask2 = (1 << (port % 8)); 497 intlv_reg = intlv_regs[port/8]; 498 499 ih = malloc(sizeof(struct vrc4172gpio_intr_entry), M_DEVBUF, M_NOWAIT); 500 if (ih == NULL) 501 panic(__FUNCTION__": no memory"); 502 503 ih->ih_port = port; 504 ih->ih_fun = ih_fun; 505 ih->ih_arg = ih_arg; 506 TAILQ_INSERT_TAIL(&sc->sc_intr_head[port], ih, ih_link); 507 508 #ifdef VRC2GPIODEBUG 509 if (DBG(DBG_INFO)) { 510 printf("port %2d:", port); 511 vrc4172gpio_intr_dump(sc, port); 512 printf("->"); 513 } 514 #endif 515 516 /* 517 * Setup registers 518 */ 519 /* I/O direction */ 520 reg = read_4(sc, VRC2_EXGPDIR); 521 reg &= ~mask; 522 write_4(sc, VRC2_EXGPDIR, reg); 523 524 /* interrupt triger (level/edge) */ 525 reg = read_4(sc, VRC2_EXGPINTTYP); 526 if (mode & HPCIO_INTR_EDGE) 527 reg |= mask; /* edge */ 528 else 529 reg &= ~mask; /* level */ 530 write_4(sc, VRC2_EXGPINTTYP, reg); 531 532 /* interrupt trigger option */ 533 reg = read_4(sc, intlv_reg); 534 if (mode & HPCIO_INTR_EDGE) { 535 switch (mode & (HPCIO_INTR_POSEDGE | HPCIO_INTR_NEGEDGE)) { 536 case HPCIO_INTR_POSEDGE: 537 reg &= ~(mask2 << 8); 538 reg |= mask2; 539 break; 540 case HPCIO_INTR_NEGEDGE: 541 reg &= ~(mask2 << 8); 542 reg &= ~mask2; 543 break; 544 case HPCIO_INTR_POSEDGE | HPCIO_INTR_NEGEDGE: 545 default: 546 reg |= (mask2 << 8); 547 break; 548 } 549 } else { 550 if (mode & HPCIO_INTR_HIGH) 551 reg |= mask2; /* high */ 552 else 553 reg &= ~mask2; /* low */ 554 } 555 write_4(sc, intlv_reg, reg); 556 557 #ifdef VRC2GPIODEBUG 558 if (DBG(DBG_INFO)) { 559 vrc4172gpio_intr_dump(sc, port); 560 printf("\n"); 561 } 562 #endif 563 564 /* XXX, Vrc4172 doesn't have register to set hold or through */ 565 566 /* 567 * clear interrupt status and enable interrupt 568 */ 569 vrc4172gpio_intr_clear(&sc->sc_iochip, ih); 570 sc->sc_intr_mask |= mask; 571 write_4(sc, VRC2_EXGPINTEN, sc->sc_intr_mask); 572 573 splx(s); 574 575 DPRINTF(DBG_INFO, "\n"); 576 577 return (ih); 578 } 579 580 void 581 vrc4172gpio_intr_disestablish(hpcio_chip_t hc, void *arg) 582 { 583 struct vrc4172gpio_intr_entry *ihe = arg; 584 struct vrc4172gpio_softc *sc = hc->hc_sc; 585 int port = ihe->ih_port; 586 struct vrc4172gpio_intr_entry *ih; 587 int s; 588 589 s = splhigh(); 590 TAILQ_FOREACH(ih, &sc->sc_intr_head[port], ih_link) { 591 if (ih == ihe) { 592 TAILQ_REMOVE(&sc->sc_intr_head[port], ih, ih_link); 593 free(ih, M_DEVBUF); 594 if (TAILQ_EMPTY(&sc->sc_intr_head[port])) { 595 /* disable interrupt */ 596 sc->sc_intr_mask &= ~(1<<port); 597 write_4(sc, VRC2_EXGPINTEN, 598 sc->sc_intr_mask); 599 } 600 splx(s); 601 return; 602 } 603 } 604 panic(__FUNCTION__": no such a handle."); 605 /* NOTREACHED */ 606 } 607 608 /* Clear interrupt */ 609 void 610 vrc4172gpio_intr_clear(hpcio_chip_t hc, void *arg) 611 { 612 struct vrc4172gpio_softc *sc = hc->hc_sc; 613 struct vrc4172gpio_intr_entry *ihe = arg; 614 615 write_4(sc, VRC2_EXGPINTST, 1 << ihe->ih_port); 616 write_4(sc, VRC2_EXGPINTST, 0); 617 } 618 619 void 620 vrc4172gpio_register_iochip(hpcio_chip_t hc, hpcio_chip_t iochip) 621 { 622 struct vrc4172gpio_softc *sc = hc->hc_sc; 623 624 hpcio_register_iochip(sc->sc_hc, iochip); 625 } 626 627 /* interrupt handler */ 628 int 629 vrc4172gpio_intr(void *arg) 630 { 631 struct vrc4172gpio_softc *sc = arg; 632 int i; 633 u_int32_t reg; 634 635 /* dispatch handler */ 636 reg = read_4(sc, VRC2_EXGPINTST); 637 DPRINTF(DBG_INTR, "%s: EXGPINTST=%06x\n", __FUNCTION__, reg); 638 for (i = 0; i < VRC2_EXGP_NPORTS; i++) { 639 if (reg & (1 << i)) { 640 register struct vrc4172gpio_intr_entry *ih; 641 642 /* 643 * call interrupt handler 644 */ 645 TAILQ_FOREACH(ih, &sc->sc_intr_head[i], ih_link) { 646 ih->ih_fun(ih->ih_arg); 647 } 648 649 /* 650 * disable interrupt if no handler is installed 651 */ 652 if (TAILQ_EMPTY(&sc->sc_intr_head[i])) { 653 sc->sc_intr_mask &= ~(1 << i); 654 write_2(sc, VRC2_EXGPINTEN, sc->sc_intr_mask); 655 656 /* dump EXGPDATA bits which changed */ 657 if (bootverbose || DBG(DBG_INFO)) 658 vrc4172gpio_diffport(sc); 659 } 660 } 661 } 662 663 return (0); 664 } 665
Indexes created Mon Sep 29 21:09:56 GMT 2025