11.2Sandvar/* $NetBSD: vrc4172pcsreg.h,v 1.2 2022/04/08 10:17:53 andvar Exp $ */ 21.1Ssato 31.1Ssato/* 41.1Ssato * Copyright (c) 2000 SATO Kazumi. All rights reserved. 51.1Ssato * 61.1Ssato * Redistribution and use in source and binary forms, with or without 71.1Ssato * modification, are permitted provided that the following conditions 81.1Ssato * are met: 91.1Ssato * 1. Redistributions of source code must retain the above copyright 101.1Ssato * notice, this list of conditions, and the following disclaimer. 111.1Ssato * 2. Redistributions in binary form must reproduce the above copyright 121.1Ssato * notice, this list of conditions and the following disclaimer in the 131.1Ssato * documentation and/or other materials provided with the distribution. 141.1Ssato * 151.1Ssato * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 161.1Ssato * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 171.1Ssato * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 181.1Ssato * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 191.1Ssato * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 201.1Ssato * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 211.1Ssato * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 221.1Ssato * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 231.1Ssato * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 241.1Ssato * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 251.1Ssato * SUCH DAMAGE. 261.1Ssato */ 271.1Ssato 281.1Ssato/* 291.2Sandvar * Vrc4172 PCS (Programmable Chip Select) Unit Registers. 301.1Ssato */ 311.1Ssato#define VRC2_EXCSREG_MAX 0x30 321.1Ssato 331.1Ssato#define VRC2_EXCS0SELL 0x00 341.1Ssato#define VRC2_EXCS0SELH 0x02 351.1Ssato#define VRC2_EXCS0MSKL 0x04 361.1Ssato#define VRC2_EXCS0MSKH 0x06 371.1Ssato#define VRC2_EXCS1SELL 0x08 381.1Ssato#define VRC2_EXCS1SELH 0x0a 391.1Ssato#define VRC2_EXCS1MSKL 0x0c 401.1Ssato#define VRC2_EXCS1MSKH 0x0e 411.1Ssato#define VRC2_EXCS2SELL 0x10 421.1Ssato#define VRC2_EXCS2SELH 0x12 431.1Ssato#define VRC2_EXCS2MSKL 0x14 441.1Ssato#define VRC2_EXCS2MSKH 0x16 451.1Ssato#define VRC2_EXCS3SELL 0x18 461.1Ssato#define VRC2_EXCS3SELH 0x1a 471.1Ssato#define VRC2_EXCS3MSKL 0x1c 481.1Ssato#define VRC2_EXCS3MSKH 0x1e 491.1Ssato#define VRC2_EXCS4SELL 0x20 501.1Ssato#define VRC2_EXCS4SELH 0x22 511.1Ssato#define VRC2_EXCS4MSKL 0x24 521.1Ssato#define VRC2_EXCS4MSKH 0x26 531.1Ssato#define VRC2_EXCS5SELL 0x28 541.1Ssato#define VRC2_EXCS5SELH 0x2a 551.1Ssato#define VRC2_EXCS5MSKL 0x2c 561.1Ssato#define VRC2_EXCS5MSKH 0x2e 571.1Ssato 581.1Ssato/* for EXCSnSELL */ 591.1Ssato#define VRC2_EXCSSELLMASK 0xfffe 601.1Ssato/* for EXCSnSELH */ 611.1Ssato#define VRC2_EXCSSELHMASK 0x01ff 621.1Ssato 631.1Ssato/* for EXCSnMSKL */ 641.1Ssato#define VRC2_EXCSENMASK 0x1 651.1Ssato#define VRC2_EXCSEN 0x1 661.1Ssato#define VRC2_EXCSDIS 0x00 671.1Ssato#define VRC2_EXCSMSKLMASK 0xfffe 681.1Ssato/* for EXCSnMSKH */ 691.1Ssato#define VRC2_EXCSMSKHMASK 0x01ff 701.1Ssato/* end */ 71