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vrc4172pmureg.h revision 1.1 
      1 /* $NetBSD: vrc4172pmureg.h,v 1.1 2000/11/11 04:42:09 sato Exp $ */
      2 /*
      3  * Copyright (c) 2000 SATO Kazumi.  All rights reserved.
      4  *
      5  * Redistribution and use in source and binary forms, with or without
      6  * modification, are permitted provided that the following conditions
      7  * are met:
      8  * 1. Redistributions of source code must retain the above copyright
      9  *    notice, this list of conditions, and the following disclaimer.
     10  * 2. Redistributions in binary form must reproduce the above copyright
     11  *    notice, this list of conditions and the following disclaimer in the
     12  *    documentation and/or other materials provided with the distribution.
     13  *
     14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
     15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
     18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     24  * SUCH DAMAGE.
     25  */
     26 
     27 /*
     28  * Vrc4172 PMU unit register definition
     29  */
     30 
     31 #define VRC2_PMU_SYSCLKCTRL	0x00
     32 #define 	VRC2_PMU_IRST		0x20	/* internal reset */
     33 #define		VRC2_PMU_OSCDIS		0x10	/* OSC disable */
     34 #define 	VRC2_PMU_CKO48		0x01	/* CKO48 enable */
     35 #define VRC2_PMU_1284CTRL	0x02
     36 #define 	VRC2_PMU_1284EN		0x04	/* 1284 enable */
     37 #define 	VRC2_PMU_1284RST	0x02	/* 1284 reset (>= 1us) */
     38 #define 	VRC2_PMU_1284CLKDIS	0x01	/* 1284 clock disanle */
     39 #define VRC2_PMU_16550CTRL	0x04
     40 #define 	VRC2_PMU_16550RST	0x02	/* 16550 reset (>= 200ms) */
     41 #define 	VRC2_PMU_16550CLKDIS	0x01	/* 16550 clock disable */
     42 #define VRC2_PMU_USBCTL		0x0c
     43 #define 	VRC2_PMU_USBCLKDIS	0x01	/* USB clock disable  */
     44 #define VRC2_PMU_PS2PWMCTL	0x0e
     45 #define 	VRC2_PMU_PWMCLKDIS	0x10	/* PWM clock disable */
     46 #define		VRC2_PMU_PS2RST		0x02	/* PS2 reset */
     47 #define		VRC2_PMU_PS2CLKDIS	0x01	/* PS2 clock disable */
     48 
     49 /* end */
     50