vrc4173bcu.c revision 1.3.4.4 1 1.3.4.4 nathanw /* $NetBSD: vrc4173bcu.c,v 1.3.4.4 2002/04/01 07:40:29 nathanw Exp $ */
2 1.3.4.2 nathanw
3 1.3.4.2 nathanw /*-
4 1.3.4.2 nathanw * Copyright (c) 2001,2002 Enami Tsugutomo.
5 1.3.4.2 nathanw * All rights reserved.
6 1.3.4.2 nathanw *
7 1.3.4.2 nathanw * Redistribution and use in source and binary forms, with or without
8 1.3.4.2 nathanw * modification, are permitted provided that the following conditions
9 1.3.4.2 nathanw * are met:
10 1.3.4.2 nathanw * 1. Redistributions of source code must retain the above copyright
11 1.3.4.2 nathanw * notice, this list of conditions and the following disclaimer.
12 1.3.4.2 nathanw * 2. Redistributions in binary form must reproduce the above copyright
13 1.3.4.2 nathanw * notice, this list of conditions and the following disclaimer in the
14 1.3.4.2 nathanw * documentation and/or other materials provided with the distribution.
15 1.3.4.2 nathanw *
16 1.3.4.2 nathanw * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
17 1.3.4.2 nathanw * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 1.3.4.2 nathanw * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 1.3.4.2 nathanw * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
20 1.3.4.2 nathanw * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 1.3.4.2 nathanw * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 1.3.4.2 nathanw * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 1.3.4.2 nathanw * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 1.3.4.2 nathanw * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 1.3.4.2 nathanw * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 1.3.4.2 nathanw * SUCH DAMAGE.
27 1.3.4.2 nathanw */
28 1.3.4.2 nathanw
29 1.3.4.2 nathanw #include <sys/param.h>
30 1.3.4.2 nathanw #include <sys/systm.h>
31 1.3.4.2 nathanw #include <sys/device.h>
32 1.3.4.2 nathanw
33 1.3.4.2 nathanw #include <machine/bus.h>
34 1.3.4.2 nathanw
35 1.3.4.2 nathanw #include <dev/pci/pcivar.h>
36 1.3.4.2 nathanw #include <dev/pci/pcidevs.h>
37 1.3.4.2 nathanw
38 1.3.4.2 nathanw #include <machine/platid.h>
39 1.3.4.2 nathanw #include <machine/platid_mask.h>
40 1.3.4.3 nathanw #include <machine/config_hook.h>
41 1.3.4.2 nathanw
42 1.3.4.4 nathanw #include <hpcmips/vr/vripunit.h>
43 1.3.4.4 nathanw #include <hpcmips/vr/vripif.h>
44 1.3.4.2 nathanw #include <hpcmips/vr/vrc4173bcuvar.h>
45 1.3.4.2 nathanw #include <hpcmips/vr/vrc4173icureg.h>
46 1.3.4.2 nathanw #include <hpcmips/vr/vrc4173cmureg.h>
47 1.3.4.2 nathanw
48 1.3.4.4 nathanw #ifdef VRC4173BCU_DEBUG
49 1.3.4.4 nathanw #define DPRINTF_ENABLE
50 1.3.4.4 nathanw #define DPRINTF_DEBUG vrc4173bcu_debug
51 1.3.4.2 nathanw #endif
52 1.3.4.4 nathanw #define USE_HPC_DPRINTF
53 1.3.4.4 nathanw #include <machine/debug.h>
54 1.3.4.2 nathanw
55 1.3.4.4 nathanw #define VRC4173BCU_BADR 0x10
56 1.3.4.2 nathanw #define USE_WINCE_CLKMASK (~0)
57 1.3.4.2 nathanw
58 1.3.4.2 nathanw static int vrc4173bcu_match(struct device *, struct cfdata *, void *);
59 1.3.4.2 nathanw static void vrc4173bcu_attach(struct device *, struct device *, void *);
60 1.3.4.3 nathanw static int vrc4173bcu_intr(void *);
61 1.3.4.4 nathanw static int vrc4173bcu_print(void *, const char *);
62 1.3.4.4 nathanw static int vrc4173bcu_search(struct device *, struct cfdata *cf, void *);
63 1.3.4.4 nathanw static int vrc4173bcu_pci_intr(void *);
64 1.3.4.4 nathanw #ifdef VRC4173BCU_DEBUG
65 1.3.4.4 nathanw static void vrc4173bcu_dump_level2mask(vrip_chipset_tag_t,
66 1.3.4.4 nathanw vrip_intr_handle_t);
67 1.3.4.4 nathanw #endif
68 1.3.4.4 nathanw
69 1.3.4.4 nathanw int __vrc4173bcu_power(vrip_chipset_tag_t, int, int);
70 1.3.4.4 nathanw vrip_intr_handle_t __vrc4173bcu_intr_establish(vrip_chipset_tag_t, int, int,
71 1.3.4.4 nathanw int, int(*)(void*), void*);
72 1.3.4.4 nathanw void __vrc4173bcu_intr_disestablish(vrip_chipset_tag_t, vrip_intr_handle_t);
73 1.3.4.4 nathanw void __vrc4173bcu_intr_setmask1(vrip_chipset_tag_t, vrip_intr_handle_t, int);
74 1.3.4.4 nathanw void __vrc4173bcu_intr_setmask2(vrip_chipset_tag_t, vrip_intr_handle_t,
75 1.3.4.4 nathanw u_int32_t, int);
76 1.3.4.4 nathanw void __vrc4173bcu_intr_getstatus2(vrip_chipset_tag_t, vrip_intr_handle_t,
77 1.3.4.4 nathanw u_int32_t*);
78 1.3.4.4 nathanw void __vrc4173bcu_register_cmu(vrip_chipset_tag_t, vrcmu_chipset_tag_t);
79 1.3.4.4 nathanw void __vrc4173bcu_register_gpio(vrip_chipset_tag_t, hpcio_chip_t);
80 1.3.4.4 nathanw void __vrc4173bcu_register_dmaau(vrip_chipset_tag_t, vrdmaau_chipset_tag_t);
81 1.3.4.4 nathanw void __vrc4173bcu_register_dcu(vrip_chipset_tag_t, vrdcu_chipset_tag_t);
82 1.3.4.4 nathanw int __vrc4173bcu_clock(vrcmu_chipset_tag_t, u_int16_t, int);
83 1.3.4.2 nathanw
84 1.3.4.2 nathanw /*
85 1.3.4.2 nathanw * machine dependent info
86 1.3.4.2 nathanw */
87 1.3.4.2 nathanw static struct vrc4173bcu_platdep {
88 1.3.4.2 nathanw platid_mask_t *platidmask;
89 1.3.4.2 nathanw u_int32_t clkmask;
90 1.3.4.3 nathanw int intrmask;
91 1.3.4.2 nathanw } platdep_table[] = {
92 1.3.4.2 nathanw {
93 1.3.4.2 nathanw &platid_mask_MACH_VICTOR_INTERLINK_MPC303,
94 1.3.4.3 nathanw USE_WINCE_CLKMASK, /* clock mask */
95 1.3.4.3 nathanw (1 << VRC4173ICU_USBINTR)| /* intrrupts */
96 1.3.4.3 nathanw (1 << VRC4173ICU_PCMCIA1INTR)|
97 1.3.4.3 nathanw (1 << VRC4173ICU_PCMCIA2INTR),
98 1.3.4.2 nathanw },
99 1.3.4.2 nathanw {
100 1.3.4.2 nathanw &platid_mask_MACH_VICTOR_INTERLINK_MPC304,
101 1.3.4.3 nathanw USE_WINCE_CLKMASK, /* clock mask */
102 1.3.4.3 nathanw (1 << VRC4173ICU_USBINTR)| /* intrrupts */
103 1.3.4.3 nathanw (1 << VRC4173ICU_PCMCIA1INTR)|
104 1.3.4.3 nathanw (1 << VRC4173ICU_PCMCIA2INTR),
105 1.3.4.2 nathanw },
106 1.3.4.2 nathanw {
107 1.3.4.2 nathanw &platid_mask_MACH_NEC_MCR_SIGMARION2,
108 1.3.4.3 nathanw USE_WINCE_CLKMASK, /* clock mask */
109 1.3.4.3 nathanw (1 << VRC4173ICU_USBINTR), /* intrrupts */
110 1.3.4.2 nathanw },
111 1.3.4.2 nathanw {
112 1.3.4.2 nathanw &platid_wild,
113 1.3.4.2 nathanw USE_WINCE_CLKMASK, /* XXX */
114 1.3.4.2 nathanw -1,
115 1.3.4.2 nathanw },
116 1.3.4.2 nathanw };
117 1.3.4.2 nathanw
118 1.3.4.4 nathanw struct vrc4173bcu_unit {
119 1.3.4.4 nathanw char *vu_name;
120 1.3.4.4 nathanw int vu_intr[2];
121 1.3.4.4 nathanw int vu_clkmask;
122 1.3.4.4 nathanw bus_addr_t vu_lreg;
123 1.3.4.4 nathanw bus_addr_t vu_mlreg;
124 1.3.4.4 nathanw bus_addr_t vu_hreg;
125 1.3.4.4 nathanw bus_addr_t vu_mhreg;
126 1.3.4.4 nathanw };
127 1.3.4.4 nathanw
128 1.3.4.2 nathanw struct vrc4173bcu_softc {
129 1.3.4.2 nathanw struct device sc_dev;
130 1.3.4.4 nathanw struct vrip_chipset_tag sc_chipset;
131 1.3.4.4 nathanw struct vrcmu_chipset_tag sc_cmuchip;
132 1.3.4.2 nathanw
133 1.3.4.2 nathanw pci_chipset_tag_t sc_pc;
134 1.3.4.2 nathanw bus_space_tag_t sc_iot;
135 1.3.4.2 nathanw bus_space_handle_t sc_ioh;
136 1.3.4.2 nathanw bus_size_t sc_size;
137 1.3.4.2 nathanw
138 1.3.4.2 nathanw bus_space_handle_t sc_icuh; /* I/O handle for ICU. */
139 1.3.4.2 nathanw bus_space_handle_t sc_cmuh; /* I/O handle for CMU. */
140 1.3.4.2 nathanw void *sc_ih;
141 1.3.4.3 nathanw #define VRC4173BCU_NINTRS 16
142 1.3.4.2 nathanw int sc_intrmask;
143 1.3.4.4 nathanw struct vrc4173bcu_intrhand {
144 1.3.4.4 nathanw int (*ih_fun)(void *);
145 1.3.4.4 nathanw void *ih_arg;
146 1.3.4.4 nathanw const struct vrc4173bcu_unit *ih_unit;
147 1.3.4.4 nathanw } sc_intrhands[32];
148 1.3.4.4 nathanw
149 1.3.4.4 nathanw struct vrc4173bcu_unit *sc_units;
150 1.3.4.4 nathanw int sc_nunits;
151 1.3.4.4 nathanw int sc_pri;
152 1.3.4.2 nathanw
153 1.3.4.2 nathanw struct vrc4173bcu_platdep *sc_platdep;
154 1.3.4.2 nathanw };
155 1.3.4.2 nathanw
156 1.3.4.4 nathanw #define VALID_UNIT(sc, unit) (0 <= (unit) && (unit) < (sc)->sc_nunits)
157 1.3.4.4 nathanw
158 1.3.4.4 nathanw static struct vrc4173bcu_unit vrc4173bcu_units[] = {
159 1.3.4.4 nathanw [VRIP_UNIT_KIU] = {
160 1.3.4.4 nathanw "kiu",
161 1.3.4.4 nathanw { VRC4173ICU_KIUINTR, },
162 1.3.4.4 nathanw VRC4173CMU_CLKMSK_KIU,
163 1.3.4.4 nathanw VRC4173ICU_KIUINT, VRC4173ICU_MKIUINT,
164 1.3.4.4 nathanw },
165 1.3.4.4 nathanw [VRIP_UNIT_PIU] = {
166 1.3.4.4 nathanw "piu",
167 1.3.4.4 nathanw { VRC4173ICU_PIUINTR, VRC4173ICU_DOZEPIUINTR},
168 1.3.4.4 nathanw VRC4173CMU_CLKMSK_PIU,
169 1.3.4.4 nathanw VRC4173ICU_PIUINT, VRC4173ICU_MPIUINT,
170 1.3.4.4 nathanw },
171 1.3.4.4 nathanw [VRIP_UNIT_AIU] = {
172 1.3.4.4 nathanw "aiu",
173 1.3.4.4 nathanw { VRC4173ICU_AIUINTR, },
174 1.3.4.4 nathanw VRC4173CMU_CLKMSK_AIU,
175 1.3.4.4 nathanw VRC4173ICU_AIUINT, VRC4173ICU_MAIUINT,
176 1.3.4.4 nathanw },
177 1.3.4.4 nathanw [VRIP_UNIT_GIU] = {
178 1.3.4.4 nathanw "giu",
179 1.3.4.4 nathanw { VRC4173ICU_GIUINTR, },
180 1.3.4.4 nathanw 0,
181 1.3.4.4 nathanw VRC4173ICU_GIULINT, VRC4173ICU_MGIULINT,
182 1.3.4.4 nathanw VRC4173ICU_GIUHINT, VRC4173ICU_MGIUHINT,
183 1.3.4.4 nathanw },
184 1.3.4.4 nathanw [VRIP_UNIT_PS2U0] = {
185 1.3.4.4 nathanw "PS/2-Ch1",
186 1.3.4.4 nathanw { VRC4173ICU_PS2CH1INTR, },
187 1.3.4.4 nathanw VRC4173CMU_CLKMSK_PS2CH1,
188 1.3.4.4 nathanw },
189 1.3.4.4 nathanw [VRIP_UNIT_PS2U1] = {
190 1.3.4.4 nathanw "PS/2-Ch2",
191 1.3.4.4 nathanw { VRC4173ICU_PS2CH2INTR, },
192 1.3.4.4 nathanw VRC4173CMU_CLKMSK_PS2CH2,
193 1.3.4.4 nathanw },
194 1.3.4.4 nathanw [VRIP_UNIT_USBU] = {
195 1.3.4.4 nathanw "usbu",
196 1.3.4.4 nathanw { VRC4173ICU_USBINTR, },
197 1.3.4.4 nathanw VRC4173CMU_CLKMSK_USB,
198 1.3.4.4 nathanw },
199 1.3.4.4 nathanw [VRIP_UNIT_CARDU0] = {
200 1.3.4.4 nathanw "cardu0",
201 1.3.4.4 nathanw { VRC4173ICU_PCMCIA1INTR, },
202 1.3.4.4 nathanw VRC4173CMU_CLKMSK_CARD1,
203 1.3.4.4 nathanw },
204 1.3.4.4 nathanw [VRIP_UNIT_CARDU1] = {
205 1.3.4.4 nathanw "cardu1",
206 1.3.4.4 nathanw { VRC4173ICU_PCMCIA2INTR, },
207 1.3.4.4 nathanw VRC4173CMU_CLKMSK_CARD2,
208 1.3.4.4 nathanw },
209 1.3.4.4 nathanw };
210 1.3.4.4 nathanw
211 1.3.4.2 nathanw struct cfattach vrc4173bcu_ca = {
212 1.3.4.2 nathanw sizeof(struct vrc4173bcu_softc), vrc4173bcu_match, vrc4173bcu_attach,
213 1.3.4.2 nathanw };
214 1.3.4.2 nathanw
215 1.3.4.4 nathanw static const struct vrip_chipset_tag vrc4173bcu_chipset_methods = {
216 1.3.4.4 nathanw .vc_power = __vrc4173bcu_power,
217 1.3.4.4 nathanw .vc_intr_establish = __vrc4173bcu_intr_establish,
218 1.3.4.4 nathanw .vc_intr_disestablish = __vrc4173bcu_intr_disestablish,
219 1.3.4.4 nathanw .vc_intr_setmask1 = __vrc4173bcu_intr_setmask1,
220 1.3.4.4 nathanw .vc_intr_setmask2 = __vrc4173bcu_intr_setmask2,
221 1.3.4.4 nathanw .vc_intr_getstatus2 = __vrc4173bcu_intr_getstatus2,
222 1.3.4.4 nathanw .vc_register_cmu = __vrc4173bcu_register_cmu,
223 1.3.4.4 nathanw .vc_register_gpio = __vrc4173bcu_register_gpio,
224 1.3.4.4 nathanw .vc_register_dmaau = __vrc4173bcu_register_dmaau,
225 1.3.4.4 nathanw .vc_register_dcu = __vrc4173bcu_register_dcu,
226 1.3.4.4 nathanw };
227 1.3.4.4 nathanw
228 1.3.4.2 nathanw int
229 1.3.4.2 nathanw vrc4173bcu_match(struct device *parent, struct cfdata *match, void *aux)
230 1.3.4.2 nathanw {
231 1.3.4.2 nathanw struct pci_attach_args *pa = (struct pci_attach_args *)aux;
232 1.3.4.2 nathanw
233 1.3.4.2 nathanw if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NEC &&
234 1.3.4.2 nathanw PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NEC_VRC4173_BCU)
235 1.3.4.2 nathanw return (1);
236 1.3.4.2 nathanw
237 1.3.4.2 nathanw return (0);
238 1.3.4.2 nathanw }
239 1.3.4.2 nathanw
240 1.3.4.2 nathanw void
241 1.3.4.2 nathanw vrc4173bcu_attach(struct device *parent, struct device *self, void *aux)
242 1.3.4.2 nathanw {
243 1.3.4.2 nathanw struct vrc4173bcu_softc *sc = (struct vrc4173bcu_softc *)self;
244 1.3.4.2 nathanw struct pci_attach_args *pa = (struct pci_attach_args *)aux;
245 1.3.4.2 nathanw pci_chipset_tag_t pc = pa->pa_pc;
246 1.3.4.2 nathanw pcitag_t tag = pa->pa_tag;
247 1.3.4.2 nathanw pcireg_t csr;
248 1.3.4.2 nathanw char devinfo[256];
249 1.3.4.2 nathanw u_int16_t reg;
250 1.3.4.3 nathanw pci_intr_handle_t ih;
251 1.3.4.3 nathanw const char *intrstr;
252 1.3.4.3 nathanw int bus, device, function;
253 1.3.4.2 nathanw #ifdef DEBUG
254 1.3.4.2 nathanw char buf[80];
255 1.3.4.2 nathanw #endif
256 1.3.4.2 nathanw
257 1.3.4.2 nathanw pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo);
258 1.3.4.2 nathanw printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class));
259 1.3.4.2 nathanw
260 1.3.4.2 nathanw #if 0
261 1.3.4.2 nathanw printf("%s: ", sc->sc_dev.dv_xname);
262 1.3.4.2 nathanw pci_conf_print(pa->pa_pc, pa->pa_tag, NULL);
263 1.3.4.2 nathanw #endif
264 1.3.4.2 nathanw
265 1.3.4.4 nathanw sc->sc_pc = pc;
266 1.3.4.4 nathanw sc->sc_cmuchip.cc_sc = sc;
267 1.3.4.4 nathanw sc->sc_cmuchip.cc_clock = __vrc4173bcu_clock;
268 1.3.4.4 nathanw sc->sc_units = vrc4173bcu_units;
269 1.3.4.4 nathanw sc->sc_nunits = sizeof(vrc4173bcu_units)/sizeof(struct vrc4173bcu_unit);
270 1.3.4.4 nathanw sc->sc_chipset = vrc4173bcu_chipset_methods; /* structure assignment */
271 1.3.4.4 nathanw sc->sc_chipset.vc_sc = sc;
272 1.3.4.2 nathanw
273 1.3.4.2 nathanw sc->sc_platdep = platid_search(&platid, platdep_table,
274 1.3.4.2 nathanw sizeof(platdep_table)/sizeof(*platdep_table),
275 1.3.4.2 nathanw sizeof(*platdep_table));
276 1.3.4.2 nathanw
277 1.3.4.2 nathanw /* Map I/O registers */
278 1.3.4.2 nathanw if (pci_mapreg_map(pa, VRC4173BCU_BADR, PCI_MAPREG_TYPE_IO, 0,
279 1.3.4.2 nathanw &sc->sc_iot, &sc->sc_ioh, NULL, &sc->sc_size)) {
280 1.3.4.2 nathanw printf("%s: can't map mem space\n", sc->sc_dev.dv_xname);
281 1.3.4.2 nathanw return;
282 1.3.4.2 nathanw }
283 1.3.4.2 nathanw
284 1.3.4.2 nathanw /* Enable the device. */
285 1.3.4.2 nathanw csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
286 1.3.4.2 nathanw DPRINTF(("%s: csr = 0x%08x", sc->sc_dev.dv_xname, csr));
287 1.3.4.2 nathanw pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG,
288 1.3.4.2 nathanw csr | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_IO_ENABLE);
289 1.3.4.2 nathanw csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
290 1.3.4.2 nathanw DPRINTF((" -> 0x%08x\n", csr));
291 1.3.4.2 nathanw
292 1.3.4.2 nathanw csr = pci_conf_read(pc, tag, VRC4173BCU_BADR);
293 1.3.4.2 nathanw DPRINTF(("%s: base addr = %x@0x%08x\n", sc->sc_dev.dv_xname,
294 1.3.4.2 nathanw (int)sc->sc_size, csr));
295 1.3.4.2 nathanw DPRINTF(("%s: iot = 0x%08x, ioh = 0x%08x\n", sc->sc_dev.dv_xname,
296 1.3.4.2 nathanw (int)sc->sc_iot, (int)sc->sc_ioh));
297 1.3.4.2 nathanw
298 1.3.4.2 nathanw /*
299 1.3.4.2 nathanw * Map I/O space for ICU.
300 1.3.4.2 nathanw */
301 1.3.4.2 nathanw if (bus_space_subregion(sc->sc_iot, sc->sc_ioh,
302 1.3.4.2 nathanw VRC4173ICU_IOBASE, VRC4173ICU_IOSIZE, &sc->sc_icuh)) {
303 1.3.4.2 nathanw printf(": can't map ICU i/o space\n");
304 1.3.4.2 nathanw return;
305 1.3.4.2 nathanw }
306 1.3.4.2 nathanw
307 1.3.4.2 nathanw /*
308 1.3.4.2 nathanw * Map I/O space for CMU.
309 1.3.4.2 nathanw */
310 1.3.4.2 nathanw if (bus_space_subregion(sc->sc_iot, sc->sc_ioh,
311 1.3.4.2 nathanw VRC4173CMU_IOBASE, VRC4173CMU_IOSIZE, &sc->sc_cmuh)) {
312 1.3.4.2 nathanw printf(": can't map CMU i/o space\n");
313 1.3.4.2 nathanw return;
314 1.3.4.2 nathanw }
315 1.3.4.2 nathanw
316 1.3.4.2 nathanw /* machine dependent setup */
317 1.3.4.2 nathanw if (sc->sc_platdep->clkmask == USE_WINCE_CLKMASK) {
318 1.3.4.2 nathanw /* XXX, You can nothing! */
319 1.3.4.2 nathanw reg = bus_space_read_2(sc->sc_iot, sc->sc_cmuh,
320 1.3.4.2 nathanw VRC4173CMU_CLKMSK);
321 1.3.4.2 nathanw printf("%s: default clock mask is %04x\n",
322 1.3.4.2 nathanw sc->sc_dev.dv_xname, reg);
323 1.3.4.2 nathanw } else {
324 1.3.4.2 nathanw /* assert all reset bits */
325 1.3.4.2 nathanw bus_space_write_2(sc->sc_iot, sc->sc_cmuh, VRC4173CMU_SRST,
326 1.3.4.2 nathanw VRC4173CMU_SRST_AC97 | VRC4173CMU_SRST_USB |
327 1.3.4.2 nathanw VRC4173CMU_SRST_CARD2 | VRC4173CMU_SRST_CARD1);
328 1.3.4.2 nathanw /* set clock mask */
329 1.3.4.2 nathanw bus_space_write_2(sc->sc_iot, sc->sc_cmuh,
330 1.3.4.2 nathanw VRC4173CMU_CLKMSK, sc->sc_platdep->clkmask);
331 1.3.4.2 nathanw /* clear reset bit */
332 1.3.4.2 nathanw bus_space_write_2(sc->sc_iot, sc->sc_cmuh, VRC4173CMU_SRST, 0);
333 1.3.4.2 nathanw }
334 1.3.4.2 nathanw
335 1.3.4.2 nathanw #ifdef DEBUG
336 1.3.4.2 nathanw reg = bus_space_read_2(sc->sc_iot, sc->sc_icuh, VRC4173ICU_SYSINT1);
337 1.3.4.2 nathanw bitmask_snprintf(reg,
338 1.3.4.2 nathanw "\20\1USB\2PCMCIA2\3PCMCIA1\4PS2CH2\5PS2CH1\6PIU\7AIU\10KIU"
339 1.3.4.2 nathanw "\11GIU\12AC97\13AC97-1\14B11\15B12\16DOZEPIU\17B14\20B15",
340 1.3.4.2 nathanw buf, sizeof(buf));
341 1.3.4.2 nathanw printf("%s: SYSINT1 = 0x%s\n", sc->sc_dev.dv_xname, buf);
342 1.3.4.2 nathanw
343 1.3.4.2 nathanw reg = bus_space_read_2(sc->sc_iot, sc->sc_icuh, VRC4173ICU_MKIUINT);
344 1.3.4.2 nathanw bitmask_snprintf(reg,
345 1.3.4.2 nathanw "\20\1SCANINT\2KDATRDY\3KDATLOST\4B3\5B4\6B5\7B6\10B7"
346 1.3.4.2 nathanw "\11B8\12B9\13B10\14B11\15B12\16B13\17B14\20B15",
347 1.3.4.2 nathanw buf, sizeof(buf));
348 1.3.4.2 nathanw printf("%s: MKIUINT = 0x%s\n", sc->sc_dev.dv_xname, buf);
349 1.3.4.2 nathanw
350 1.3.4.2 nathanw reg = bus_space_read_2(sc->sc_iot, sc->sc_icuh, VRC4173ICU_MSYSINT1);
351 1.3.4.2 nathanw bitmask_snprintf(reg,
352 1.3.4.2 nathanw "\20\1USB\2PCMCIA2\3PCMCIA1\4PS2CH2\5PS2CH1\6PIU\7AIU\10KIU"
353 1.3.4.2 nathanw "\11GIU\12AC97\13AC97-1\14B11\15B12\16DOZEPIU\17B14\20B15",
354 1.3.4.2 nathanw buf, sizeof(buf));
355 1.3.4.2 nathanw printf("%s: MSYSINT1 = 0x%s\n", sc->sc_dev.dv_xname, buf);
356 1.3.4.2 nathanw
357 1.3.4.2 nathanw #if 1
358 1.3.4.2 nathanw reg = VRC4173ICU_USBINTR | VRC4173ICU_PIUINTR | VRC4173ICU_KIUINTR |
359 1.3.4.2 nathanw VRC4173ICU_DOZEPIUINTR;
360 1.3.4.2 nathanw bus_space_write_2(sc->sc_iot, sc->sc_icuh, VRC4173ICU_MSYSINT1, reg);
361 1.3.4.2 nathanw
362 1.3.4.2 nathanw reg = bus_space_read_2(sc->sc_iot, sc->sc_icuh, VRC4173ICU_MSYSINT1);
363 1.3.4.2 nathanw bitmask_snprintf(reg,
364 1.3.4.2 nathanw "\20\1USB\2PCMCIA2\3PCMCIA1\4PS2CH2\5PS2CH1\6PIU\7AIU\10KIU"
365 1.3.4.2 nathanw "\11GIU\12AC97\13AC97-1\14B11\15B12\16DOZEPIU\17B14\20B15",
366 1.3.4.2 nathanw buf, sizeof(buf));
367 1.3.4.2 nathanw printf("%s: MSYSINT1 = 0x%s\n", sc->sc_dev.dv_xname, buf);
368 1.3.4.2 nathanw #endif
369 1.3.4.2 nathanw #endif
370 1.3.4.2 nathanw
371 1.3.4.3 nathanw /*
372 1.3.4.4 nathanw * set interrupt mask
373 1.3.4.4 nathanw */
374 1.3.4.4 nathanw sc->sc_intrmask = sc->sc_platdep->intrmask;
375 1.3.4.4 nathanw bus_space_write_2(sc->sc_iot, sc->sc_icuh, VRC4173ICU_MSYSINT1,
376 1.3.4.4 nathanw sc->sc_intrmask);
377 1.3.4.4 nathanw
378 1.3.4.4 nathanw /*
379 1.3.4.3 nathanw * install interrupt handler
380 1.3.4.3 nathanw */
381 1.3.4.3 nathanw if (pci_intr_map(pa, &ih)) {
382 1.3.4.3 nathanw printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname);
383 1.3.4.3 nathanw return;
384 1.3.4.3 nathanw }
385 1.3.4.3 nathanw intrstr = pci_intr_string(pc, ih);
386 1.3.4.3 nathanw sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, vrc4173bcu_intr, sc);
387 1.3.4.3 nathanw if (sc->sc_ih == NULL) {
388 1.3.4.3 nathanw printf("%s: couldn't establish interrupt",
389 1.3.4.3 nathanw sc->sc_dev.dv_xname);
390 1.3.4.3 nathanw if (intrstr != NULL)
391 1.3.4.3 nathanw printf(" at %s", intrstr);
392 1.3.4.3 nathanw printf("\n");
393 1.3.4.3 nathanw return;
394 1.3.4.3 nathanw }
395 1.3.4.3 nathanw printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr);
396 1.3.4.3 nathanw
397 1.3.4.3 nathanw /*
398 1.3.4.3 nathanw * install pci intr hooks
399 1.3.4.3 nathanw */
400 1.3.4.3 nathanw pci_decompose_tag(pc, pa->pa_intrtag, &bus, &device, &function);
401 1.3.4.3 nathanw /* USB unit */
402 1.3.4.3 nathanw if (sc->sc_intrmask & (1 << VRC4173ICU_USBINTR))
403 1.3.4.4 nathanw vrip_intr_establish(&sc->sc_chipset, VRIP_UNIT_USBU, 0,
404 1.3.4.4 nathanw IPL_NET, vrc4173bcu_pci_intr,
405 1.3.4.3 nathanw config_connect(CONFIG_HOOK_PCIINTR,
406 1.3.4.4 nathanw CONFIG_HOOK_PCIINTR_ID(bus, device, 2)));
407 1.3.4.3 nathanw /* PC card unit 1 */
408 1.3.4.3 nathanw if (sc->sc_intrmask & (1 << VRC4173ICU_PCMCIA1INTR))
409 1.3.4.4 nathanw vrip_intr_establish(&sc->sc_chipset, VRIP_UNIT_CARDU0, 0,
410 1.3.4.4 nathanw IPL_NET, vrc4173bcu_pci_intr,
411 1.3.4.3 nathanw config_connect(CONFIG_HOOK_PCIINTR,
412 1.3.4.4 nathanw CONFIG_HOOK_PCIINTR_ID(bus, 1, 0)));
413 1.3.4.3 nathanw /* PC card unit 2 */
414 1.3.4.3 nathanw if (sc->sc_intrmask & (1 << VRC4173ICU_PCMCIA2INTR))
415 1.3.4.4 nathanw vrip_intr_establish(&sc->sc_chipset, VRIP_UNIT_CARDU1, 0,
416 1.3.4.4 nathanw IPL_NET, vrc4173bcu_pci_intr,
417 1.3.4.3 nathanw config_connect(CONFIG_HOOK_PCIINTR,
418 1.3.4.4 nathanw CONFIG_HOOK_PCIINTR_ID(bus, 2, 0)));
419 1.3.4.3 nathanw
420 1.3.4.3 nathanw /*
421 1.3.4.4 nathanw * Attach each devices
422 1.3.4.4 nathanw * sc->sc_pri = 2~1
423 1.3.4.2 nathanw */
424 1.3.4.4 nathanw for (sc->sc_pri = 2; 0 < sc->sc_pri; sc->sc_pri--)
425 1.3.4.4 nathanw config_search(vrc4173bcu_search, self, vrc4173bcu_print);
426 1.3.4.2 nathanw }
427 1.3.4.2 nathanw
428 1.3.4.2 nathanw int
429 1.3.4.4 nathanw vrc4173bcu_print(void *aux, const char *hoge)
430 1.3.4.2 nathanw {
431 1.3.4.4 nathanw struct vrip_attach_args *va = (struct vrip_attach_args*)aux;
432 1.3.4.2 nathanw
433 1.3.4.4 nathanw if (va->va_addr != VRIPIFCF_ADDR_DEFAULT)
434 1.3.4.4 nathanw printf(" addr 0x%04lx", va->va_addr);
435 1.3.4.4 nathanw if (va->va_size != VRIPIFCF_SIZE_DEFAULT)
436 1.3.4.4 nathanw printf("-%04lx", (va->va_addr + va->va_size - 1) & 0xffff);
437 1.3.4.4 nathanw if (va->va_addr2 != VRIPIFCF_ADDR2_DEFAULT)
438 1.3.4.4 nathanw printf(", 0x%04lx", va->va_addr2);
439 1.3.4.4 nathanw if (va->va_size2 != VRIPIFCF_SIZE2_DEFAULT)
440 1.3.4.4 nathanw printf("-%04lx", (va->va_addr2 + va->va_size2 - 1) & 0xffff);
441 1.3.4.2 nathanw
442 1.3.4.2 nathanw return (UNCONF);
443 1.3.4.2 nathanw }
444 1.3.4.2 nathanw
445 1.3.4.2 nathanw int
446 1.3.4.4 nathanw vrc4173bcu_search(struct device *parent, struct cfdata *cf, void *aux)
447 1.3.4.4 nathanw {
448 1.3.4.4 nathanw struct vrc4173bcu_softc *sc = (struct vrc4173bcu_softc *)parent;
449 1.3.4.4 nathanw struct vrip_attach_args va;
450 1.3.4.4 nathanw
451 1.3.4.4 nathanw memset(&va, 0, sizeof(va));
452 1.3.4.4 nathanw va.va_vc = &sc->sc_chipset;
453 1.3.4.4 nathanw va.va_iot = sc->sc_iot;
454 1.3.4.4 nathanw va.va_parent_ioh = sc->sc_ioh;
455 1.3.4.4 nathanw va.va_unit = cf->cf_loc[VRIPIFCF_UNIT];
456 1.3.4.4 nathanw va.va_addr = cf->cf_loc[VRIPIFCF_ADDR];
457 1.3.4.4 nathanw va.va_size = cf->cf_loc[VRIPIFCF_SIZE];
458 1.3.4.4 nathanw va.va_addr2 = cf->cf_loc[VRIPIFCF_ADDR2];
459 1.3.4.4 nathanw va.va_size2 = cf->cf_loc[VRIPIFCF_SIZE2];
460 1.3.4.4 nathanw va.va_gpio_chips = NULL; /* XXX */
461 1.3.4.4 nathanw va.va_cc = sc->sc_chipset.vc_cc;
462 1.3.4.4 nathanw va.va_ac = sc->sc_chipset.vc_ac;
463 1.3.4.4 nathanw va.va_dc = sc->sc_chipset.vc_dc;
464 1.3.4.4 nathanw if (((*cf->cf_attach->ca_match)(parent, cf, &va) == sc->sc_pri))
465 1.3.4.4 nathanw config_attach(parent, cf, &va, vrc4173bcu_print);
466 1.3.4.4 nathanw
467 1.3.4.4 nathanw return (0);
468 1.3.4.4 nathanw }
469 1.3.4.4 nathanw
470 1.3.4.4 nathanw int
471 1.3.4.2 nathanw vrc4173bcu_intr(void *arg)
472 1.3.4.2 nathanw {
473 1.3.4.2 nathanw struct vrc4173bcu_softc *sc = (struct vrc4173bcu_softc *)arg;
474 1.3.4.2 nathanw u_int16_t reg;
475 1.3.4.4 nathanw struct vrc4173bcu_intrhand *ih;
476 1.3.4.3 nathanw int i;
477 1.3.4.2 nathanw
478 1.3.4.2 nathanw reg = bus_space_read_2(sc->sc_iot, sc->sc_icuh, VRC4173ICU_SYSINT1);
479 1.3.4.3 nathanw reg &= sc->sc_intrmask;
480 1.3.4.2 nathanw if (reg == 0)
481 1.3.4.2 nathanw return (0);
482 1.3.4.2 nathanw
483 1.3.4.2 nathanw #if 0
484 1.3.4.2 nathanw {
485 1.3.4.2 nathanw char buf[80];
486 1.3.4.2 nathanw bitmask_snprintf(reg,
487 1.3.4.2 nathanw "\20\1USB\2PCMCIA2\3PCMCIA1\4PS2CH2\5PS2CH1\6PIU\7AIU\10KIU"
488 1.3.4.2 nathanw "\11GIU\12AC97\13AC97-1\14B11\15B12\16DOZEPIU\17B14\20B15",
489 1.3.4.2 nathanw buf, sizeof(buf));
490 1.3.4.2 nathanw printf("%s: %s\n", sc->sc_dev.dv_xname, buf);
491 1.3.4.2 nathanw }
492 1.3.4.2 nathanw #endif
493 1.3.4.4 nathanw for (ih = sc->sc_intrhands, i = 0; i < VRC4173BCU_NINTRS; i++, ih++)
494 1.3.4.4 nathanw if ((reg & (1 << i)) && ih->ih_fun != NULL)
495 1.3.4.4 nathanw ih->ih_fun(ih->ih_arg);
496 1.3.4.2 nathanw
497 1.3.4.3 nathanw return (1);
498 1.3.4.2 nathanw }
499 1.3.4.4 nathanw
500 1.3.4.4 nathanw static int
501 1.3.4.4 nathanw vrc4173bcu_pci_intr(void *arg)
502 1.3.4.4 nathanw {
503 1.3.4.4 nathanw config_call_tag ct = (config_call_tag)arg;
504 1.3.4.4 nathanw config_connected_call(ct, NULL);
505 1.3.4.4 nathanw
506 1.3.4.4 nathanw return (0);
507 1.3.4.4 nathanw }
508 1.3.4.4 nathanw
509 1.3.4.4 nathanw #ifdef VRC4173BCU_DEBUG
510 1.3.4.4 nathanw static void
511 1.3.4.4 nathanw vrc4173bcu_dump_level2mask(vrip_chipset_tag_t vc, vrip_intr_handle_t handle)
512 1.3.4.4 nathanw {
513 1.3.4.4 nathanw struct vrc4173bcu_softc *sc = vc->vc_sc;
514 1.3.4.4 nathanw struct vrc4173bcu_intrhand *ih = handle;
515 1.3.4.4 nathanw const struct vrc4173bcu_unit *vu = ih->ih_unit;
516 1.3.4.4 nathanw u_int32_t reg;
517 1.3.4.4 nathanw
518 1.3.4.4 nathanw if (vu->vu_mlreg) {
519 1.3.4.4 nathanw DPRINTF(("level1[%d] level2 mask:", vu->vu_intr[0]));
520 1.3.4.4 nathanw reg = bus_space_read_2(sc->sc_iot, sc->sc_icuh, vu->vu_mlreg);
521 1.3.4.4 nathanw if (vu->vu_mhreg) {
522 1.3.4.4 nathanw reg |= (bus_space_read_2(sc->sc_iot, sc->sc_icuh,
523 1.3.4.4 nathanw vu->vu_mhreg) << 16);
524 1.3.4.4 nathanw dbg_bit_print(reg);
525 1.3.4.4 nathanw } else
526 1.3.4.4 nathanw dbg_bit_print(reg);
527 1.3.4.4 nathanw }
528 1.3.4.4 nathanw }
529 1.3.4.4 nathanw #endif
530 1.3.4.4 nathanw
531 1.3.4.4 nathanw int
532 1.3.4.4 nathanw __vrc4173bcu_power(vrip_chipset_tag_t vc, int unit, int onoff)
533 1.3.4.4 nathanw {
534 1.3.4.4 nathanw struct vrc4173bcu_softc *sc = vc->vc_sc;
535 1.3.4.4 nathanw const struct vrc4173bcu_unit *vu;
536 1.3.4.4 nathanw
537 1.3.4.4 nathanw if (sc->sc_chipset.vc_cc == NULL)
538 1.3.4.4 nathanw return (0); /* You have no clock mask unit yet. */
539 1.3.4.4 nathanw if (!VALID_UNIT(sc, unit))
540 1.3.4.4 nathanw return (0);
541 1.3.4.4 nathanw vu = &sc->sc_units[unit];
542 1.3.4.4 nathanw
543 1.3.4.4 nathanw return (*sc->sc_chipset.vc_cc->cc_clock)(sc->sc_chipset.vc_cc,
544 1.3.4.4 nathanw vu->vu_clkmask, onoff);
545 1.3.4.4 nathanw }
546 1.3.4.4 nathanw
547 1.3.4.4 nathanw vrip_intr_handle_t
548 1.3.4.4 nathanw __vrc4173bcu_intr_establish(vrip_chipset_tag_t vc, int unit, int line,
549 1.3.4.4 nathanw int level, int (*ih_fun)(void *), void *ih_arg)
550 1.3.4.4 nathanw {
551 1.3.4.4 nathanw struct vrc4173bcu_softc *sc = vc->vc_sc;
552 1.3.4.4 nathanw const struct vrc4173bcu_unit *vu;
553 1.3.4.4 nathanw struct vrc4173bcu_intrhand *ih;
554 1.3.4.4 nathanw
555 1.3.4.4 nathanw if (!VALID_UNIT(sc, unit))
556 1.3.4.4 nathanw return (NULL);
557 1.3.4.4 nathanw vu = &sc->sc_units[unit];
558 1.3.4.4 nathanw ih = &sc->sc_intrhands[vu->vu_intr[line]];
559 1.3.4.4 nathanw if (ih->ih_fun) /* Can't share level 1 interrupt */
560 1.3.4.4 nathanw return (NULL);
561 1.3.4.4 nathanw ih->ih_fun = ih_fun;
562 1.3.4.4 nathanw ih->ih_arg = ih_arg;
563 1.3.4.4 nathanw ih->ih_unit = vu;
564 1.3.4.4 nathanw
565 1.3.4.4 nathanw /* Mask level 2 interrupt mask register. (disable interrupt) */
566 1.3.4.4 nathanw vrip_intr_setmask2(vc, ih, ~0, 0);
567 1.3.4.4 nathanw /* Unmask Level 1 interrupt mask register (enable interrupt) */
568 1.3.4.4 nathanw vrip_intr_setmask1(vc, ih, 1);
569 1.3.4.4 nathanw
570 1.3.4.4 nathanw return ((void *)ih);
571 1.3.4.4 nathanw }
572 1.3.4.4 nathanw
573 1.3.4.4 nathanw void
574 1.3.4.4 nathanw __vrc4173bcu_intr_disestablish(vrip_chipset_tag_t vc, vrip_intr_handle_t handle)
575 1.3.4.4 nathanw {
576 1.3.4.4 nathanw struct vrc4173bcu_intrhand *ih = handle;
577 1.3.4.4 nathanw
578 1.3.4.4 nathanw /* Mask Level 1 interrupt mask register (disable interrupt) */
579 1.3.4.4 nathanw vrip_intr_setmask1(vc, ih, 0);
580 1.3.4.4 nathanw /* Mask level 2 interrupt mask register(if any). (disable interrupt) */
581 1.3.4.4 nathanw vrip_intr_setmask2(vc, ih, ~0, 0);
582 1.3.4.4 nathanw ih->ih_fun = NULL;
583 1.3.4.4 nathanw ih->ih_arg = NULL;
584 1.3.4.4 nathanw }
585 1.3.4.4 nathanw
586 1.3.4.4 nathanw /* Set level 1 interrupt mask. */
587 1.3.4.4 nathanw void
588 1.3.4.4 nathanw __vrc4173bcu_intr_setmask1(vrip_chipset_tag_t vc, vrip_intr_handle_t handle,
589 1.3.4.4 nathanw int enable)
590 1.3.4.4 nathanw {
591 1.3.4.4 nathanw struct vrc4173bcu_softc *sc = vc->vc_sc;
592 1.3.4.4 nathanw struct vrc4173bcu_intrhand *ih = handle;
593 1.3.4.4 nathanw int level1 = ih - sc->sc_intrhands;
594 1.3.4.4 nathanw
595 1.3.4.4 nathanw DPRINTF(("__vrc4173bcu_intr_setmask1: SYSINT: %s %d\n",
596 1.3.4.4 nathanw enable ? "enable" : "disable", level1));
597 1.3.4.4 nathanw if (enable)
598 1.3.4.4 nathanw sc->sc_intrmask |= (1 << level1);
599 1.3.4.4 nathanw else
600 1.3.4.4 nathanw sc->sc_intrmask &= ~(1 << level1);
601 1.3.4.4 nathanw bus_space_write_2 (sc->sc_iot, sc->sc_icuh, VRC4173ICU_MSYSINT1,
602 1.3.4.4 nathanw sc->sc_intrmask);
603 1.3.4.4 nathanw #ifdef VRC4173BCU_DEBUG
604 1.3.4.4 nathanw if (vrc4173bcu_debug)
605 1.3.4.4 nathanw dbg_bit_print(sc->sc_intrmask);
606 1.3.4.4 nathanw #endif
607 1.3.4.4 nathanw
608 1.3.4.4 nathanw return;
609 1.3.4.4 nathanw }
610 1.3.4.4 nathanw
611 1.3.4.4 nathanw /* Get level 2 interrupt status */
612 1.3.4.4 nathanw void
613 1.3.4.4 nathanw __vrc4173bcu_intr_getstatus2(vrip_chipset_tag_t vc, vrip_intr_handle_t handle,
614 1.3.4.4 nathanw u_int32_t *status /* Level 2 status */)
615 1.3.4.4 nathanw {
616 1.3.4.4 nathanw struct vrc4173bcu_softc *sc = vc->vc_sc;
617 1.3.4.4 nathanw struct vrc4173bcu_intrhand *ih = handle;
618 1.3.4.4 nathanw const struct vrc4173bcu_unit *vu = ih->ih_unit;
619 1.3.4.4 nathanw u_int32_t reg;
620 1.3.4.4 nathanw
621 1.3.4.4 nathanw reg = bus_space_read_2(sc->sc_iot, sc->sc_icuh, vu->vu_lreg);
622 1.3.4.4 nathanw reg |= (bus_space_read_2(sc->sc_iot, sc->sc_icuh, vu->vu_hreg) << 16);
623 1.3.4.4 nathanw *status = reg;
624 1.3.4.4 nathanw }
625 1.3.4.4 nathanw
626 1.3.4.4 nathanw /* Set level 2 interrupt mask. */
627 1.3.4.4 nathanw void
628 1.3.4.4 nathanw __vrc4173bcu_intr_setmask2(vrip_chipset_tag_t vc, vrip_intr_handle_t handle,
629 1.3.4.4 nathanw u_int32_t mask /* Level 2 mask */, int onoff)
630 1.3.4.4 nathanw {
631 1.3.4.4 nathanw struct vrc4173bcu_softc *sc = vc->vc_sc;
632 1.3.4.4 nathanw struct vrc4173bcu_intrhand *ih = handle;
633 1.3.4.4 nathanw const struct vrc4173bcu_unit *vu = ih->ih_unit;
634 1.3.4.4 nathanw u_int16_t reg;
635 1.3.4.4 nathanw
636 1.3.4.4 nathanw DPRINTF(("vrc4173bcu_intr_setmask2:\n"));
637 1.3.4.4 nathanw #ifdef VRC4173BCU_DEBUG
638 1.3.4.4 nathanw if (vrc4173bcu_debug)
639 1.3.4.4 nathanw vrc4173bcu_dump_level2mask(vc, handle);
640 1.3.4.4 nathanw #endif
641 1.3.4.4 nathanw if (vu->vu_mlreg) {
642 1.3.4.4 nathanw reg = bus_space_read_2(sc->sc_iot, sc->sc_icuh, vu->vu_mlreg);
643 1.3.4.4 nathanw if (onoff)
644 1.3.4.4 nathanw reg |= (mask & 0xffff);
645 1.3.4.4 nathanw else
646 1.3.4.4 nathanw reg &= ~(mask & 0xffff);
647 1.3.4.4 nathanw bus_space_write_2(sc->sc_iot, sc->sc_ioh, vu->vu_mlreg, reg);
648 1.3.4.4 nathanw }
649 1.3.4.4 nathanw if (vu->vu_mhreg) {
650 1.3.4.4 nathanw reg = bus_space_read_2(sc->sc_iot, sc->sc_icuh, vu->vu_mhreg);
651 1.3.4.4 nathanw if (onoff)
652 1.3.4.4 nathanw reg |= ((mask >> 16) & 0xffff);
653 1.3.4.4 nathanw else
654 1.3.4.4 nathanw reg &= ~((mask >> 16) & 0xffff);
655 1.3.4.4 nathanw bus_space_write_2(sc->sc_iot, sc->sc_icuh, vu->vu_mhreg, reg);
656 1.3.4.4 nathanw }
657 1.3.4.4 nathanw #ifdef VRC4173BCU_DEBUG
658 1.3.4.4 nathanw if (vrc4173bcu_debug)
659 1.3.4.4 nathanw vrc4173bcu_dump_level2mask(vc, handle);
660 1.3.4.4 nathanw #endif
661 1.3.4.4 nathanw
662 1.3.4.4 nathanw return;
663 1.3.4.4 nathanw }
664 1.3.4.4 nathanw
665 1.3.4.4 nathanw int
666 1.3.4.4 nathanw __vrc4173bcu_clock(vrcmu_chipset_tag_t cc, u_int16_t mask, int onoff)
667 1.3.4.4 nathanw {
668 1.3.4.4 nathanw struct vrc4173bcu_softc *sc = cc->cc_sc;
669 1.3.4.4 nathanw u_int16_t reg;
670 1.3.4.4 nathanw
671 1.3.4.4 nathanw reg = bus_space_read_2(sc->sc_iot, sc->sc_cmuh, VRC4173CMU_CLKMSK);
672 1.3.4.4 nathanw #if 0
673 1.3.4.4 nathanw printf("cmu register(enter):");
674 1.3.4.4 nathanw dbg_bit_print(reg);
675 1.3.4.4 nathanw #endif
676 1.3.4.4 nathanw if (onoff)
677 1.3.4.4 nathanw reg |= mask;
678 1.3.4.4 nathanw else
679 1.3.4.4 nathanw reg &= ~mask;
680 1.3.4.4 nathanw bus_space_write_2(sc->sc_iot, sc->sc_cmuh, VRC4173CMU_CLKMSK, reg);
681 1.3.4.4 nathanw #if 0
682 1.3.4.4 nathanw printf("cmu register(exit) :");
683 1.3.4.4 nathanw dbg_bit_print(reg);
684 1.3.4.4 nathanw #endif
685 1.3.4.4 nathanw return (0);
686 1.3.4.4 nathanw }
687 1.3.4.4 nathanw
688 1.3.4.4 nathanw void
689 1.3.4.4 nathanw __vrc4173bcu_register_cmu(vrip_chipset_tag_t vc, vrcmu_chipset_tag_t cmu)
690 1.3.4.4 nathanw {
691 1.3.4.4 nathanw vc->vc_cc = cmu;
692 1.3.4.4 nathanw }
693 1.3.4.4 nathanw
694 1.3.4.4 nathanw void
695 1.3.4.4 nathanw __vrc4173bcu_register_gpio(vrip_chipset_tag_t vc, hpcio_chip_t chip)
696 1.3.4.4 nathanw {
697 1.3.4.4 nathanw /* XXX, not implemented yet */
698 1.3.4.4 nathanw }
699 1.3.4.4 nathanw
700 1.3.4.4 nathanw void
701 1.3.4.4 nathanw __vrc4173bcu_register_dmaau(vrip_chipset_tag_t vc, vrdmaau_chipset_tag_t dmaau)
702 1.3.4.4 nathanw {
703 1.3.4.4 nathanw
704 1.3.4.4 nathanw vc->vc_ac = dmaau;
705 1.3.4.4 nathanw }
706 1.3.4.4 nathanw
707 1.3.4.4 nathanw void
708 1.3.4.4 nathanw __vrc4173bcu_register_dcu(vrip_chipset_tag_t vc, vrdcu_chipset_tag_t dcu)
709 1.3.4.4 nathanw {
710 1.3.4.4 nathanw
711 1.3.4.4 nathanw vc->vc_dc = dcu;
712 1.3.4.4 nathanw }
713