vrc4173bcu.c revision 1.18
1 /* $NetBSD: vrc4173bcu.c,v 1.18 2005/08/26 13:19:36 drochner Exp $ */ 2 3 /*- 4 * Copyright (c) 2001,2002 Enami Tsugutomo. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: vrc4173bcu.c,v 1.18 2005/08/26 13:19:36 drochner Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/device.h> 35 36 #include <machine/bus.h> 37 38 #include <dev/pci/pcivar.h> 39 #include <dev/pci/pcidevs.h> 40 41 #include <machine/platid.h> 42 #include <machine/platid_mask.h> 43 #include <machine/config_hook.h> 44 45 #include <hpcmips/vr/vripunit.h> 46 #include <hpcmips/vr/vripif.h> 47 #include <hpcmips/vr/vrc4173bcuvar.h> 48 #include <hpcmips/vr/vrc4173icureg.h> 49 #include <hpcmips/vr/vrc4173cmureg.h> 50 51 #include "locators.h" 52 53 #ifdef VRC4173BCU_DEBUG 54 #define DPRINTF_ENABLE 55 #define DPRINTF_DEBUG vrc4173bcu_debug 56 #endif 57 #define USE_HPC_DPRINTF 58 #include <machine/debug.h> 59 60 #define VRC4173BCU_BADR 0x10 61 #define USE_WINCE_CLKMASK (~0) 62 63 static int vrc4173bcu_match(struct device *, struct cfdata *, void *); 64 static void vrc4173bcu_attach(struct device *, struct device *, void *); 65 static int vrc4173bcu_intr(void *); 66 static int vrc4173bcu_print(void *, const char *); 67 static int vrc4173bcu_search(struct device *, struct cfdata *cf, 68 const int *, void *); 69 static int vrc4173bcu_pci_intr(void *); 70 #ifdef VRC4173BCU_DEBUG 71 static void vrc4173bcu_dump_level2mask(vrip_chipset_tag_t, 72 vrip_intr_handle_t); 73 #endif 74 75 int __vrc4173bcu_power(vrip_chipset_tag_t, int, int); 76 vrip_intr_handle_t __vrc4173bcu_intr_establish(vrip_chipset_tag_t, int, int, 77 int, int(*)(void*), void*); 78 void __vrc4173bcu_intr_disestablish(vrip_chipset_tag_t, vrip_intr_handle_t); 79 void __vrc4173bcu_intr_setmask1(vrip_chipset_tag_t, vrip_intr_handle_t, int); 80 void __vrc4173bcu_intr_setmask2(vrip_chipset_tag_t, vrip_intr_handle_t, 81 u_int32_t, int); 82 void __vrc4173bcu_intr_getstatus2(vrip_chipset_tag_t, vrip_intr_handle_t, 83 u_int32_t*); 84 void __vrc4173bcu_register_cmu(vrip_chipset_tag_t, vrcmu_chipset_tag_t); 85 void __vrc4173bcu_register_gpio(vrip_chipset_tag_t, hpcio_chip_t); 86 void __vrc4173bcu_register_dmaau(vrip_chipset_tag_t, vrdmaau_chipset_tag_t); 87 void __vrc4173bcu_register_dcu(vrip_chipset_tag_t, vrdcu_chipset_tag_t); 88 int __vrc4173bcu_clock(vrcmu_chipset_tag_t, u_int16_t, int); 89 90 /* 91 * machine dependent info 92 */ 93 static struct vrc4173bcu_platdep { 94 platid_mask_t *platidmask; 95 u_int32_t clkmask; 96 int intrmask; 97 } platdep_table[] = { 98 { 99 &platid_mask_MACH_VICTOR_INTERLINK_MPC303, 100 USE_WINCE_CLKMASK, /* clock mask */ 101 (1 << VRC4173ICU_USBINTR)| /* intrrupts */ 102 (1 << VRC4173ICU_PCMCIA1INTR)| 103 (1 << VRC4173ICU_PCMCIA2INTR), 104 }, 105 { 106 &platid_mask_MACH_VICTOR_INTERLINK_MPC304, 107 USE_WINCE_CLKMASK, /* clock mask */ 108 (1 << VRC4173ICU_USBINTR)| /* intrrupts */ 109 (1 << VRC4173ICU_PCMCIA1INTR)| 110 (1 << VRC4173ICU_PCMCIA2INTR), 111 }, 112 { 113 &platid_mask_MACH_NEC_MCR_SIGMARION2, 114 USE_WINCE_CLKMASK, /* clock mask */ 115 (1 << VRC4173ICU_USBINTR), /* intrrupts */ 116 }, 117 { 118 &platid_wild, 119 USE_WINCE_CLKMASK, /* XXX */ 120 -1, 121 }, 122 }; 123 124 struct vrc4173bcu_unit { 125 const char *vu_name; 126 int vu_intr[2]; 127 int vu_clkmask; 128 bus_addr_t vu_lreg; 129 bus_addr_t vu_mlreg; 130 bus_addr_t vu_hreg; 131 bus_addr_t vu_mhreg; 132 }; 133 134 struct vrc4173bcu_softc { 135 struct device sc_dev; 136 struct vrip_chipset_tag sc_chipset; 137 struct vrcmu_chipset_tag sc_cmuchip; 138 139 pci_chipset_tag_t sc_pc; 140 bus_space_tag_t sc_iot; 141 bus_space_handle_t sc_ioh; 142 bus_size_t sc_size; 143 144 bus_space_handle_t sc_icuh; /* I/O handle for ICU. */ 145 bus_space_handle_t sc_cmuh; /* I/O handle for CMU. */ 146 void *sc_ih; 147 #define VRC4173BCU_NINTRS 16 148 int sc_intrmask; 149 struct vrc4173bcu_intrhand { 150 int (*ih_fun)(void *); 151 void *ih_arg; 152 const struct vrc4173bcu_unit *ih_unit; 153 } sc_intrhands[32]; 154 155 struct vrc4173bcu_unit *sc_units; 156 int sc_nunits; 157 int sc_pri; 158 159 struct vrc4173bcu_platdep *sc_platdep; 160 }; 161 162 #define VALID_UNIT(sc, unit) (0 <= (unit) && (unit) < (sc)->sc_nunits) 163 164 static struct vrc4173bcu_unit vrc4173bcu_units[] = { 165 [VRIP_UNIT_KIU] = { 166 "kiu", 167 { VRC4173ICU_KIUINTR, }, 168 VRC4173CMU_CLKMSK_KIU, 169 VRC4173ICU_KIUINT, VRC4173ICU_MKIUINT, 170 }, 171 [VRIP_UNIT_PIU] = { 172 "piu", 173 { VRC4173ICU_PIUINTR, VRC4173ICU_DOZEPIUINTR}, 174 VRC4173CMU_CLKMSK_PIU, 175 VRC4173ICU_PIUINT, VRC4173ICU_MPIUINT, 176 }, 177 [VRIP_UNIT_AIU] = { 178 "aiu", 179 { VRC4173ICU_AIUINTR, }, 180 VRC4173CMU_CLKMSK_AIU, 181 VRC4173ICU_AIUINT, VRC4173ICU_MAIUINT, 182 }, 183 [VRIP_UNIT_GIU] = { 184 "giu", 185 { VRC4173ICU_GIUINTR, }, 186 0, 187 VRC4173ICU_GIULINT, VRC4173ICU_MGIULINT, 188 VRC4173ICU_GIUHINT, VRC4173ICU_MGIUHINT, 189 }, 190 [VRIP_UNIT_PS2U0] = { 191 "PS/2-Ch1", 192 { VRC4173ICU_PS2CH1INTR, }, 193 VRC4173CMU_CLKMSK_PS2CH1, 194 }, 195 [VRIP_UNIT_PS2U1] = { 196 "PS/2-Ch2", 197 { VRC4173ICU_PS2CH2INTR, }, 198 VRC4173CMU_CLKMSK_PS2CH2, 199 }, 200 [VRIP_UNIT_USBU] = { 201 "usbu", 202 { VRC4173ICU_USBINTR, }, 203 VRC4173CMU_CLKMSK_USB, 204 }, 205 [VRIP_UNIT_CARDU0] = { 206 "cardu0", 207 { VRC4173ICU_PCMCIA1INTR, }, 208 VRC4173CMU_CLKMSK_CARD1, 209 }, 210 [VRIP_UNIT_CARDU1] = { 211 "cardu1", 212 { VRC4173ICU_PCMCIA2INTR, }, 213 VRC4173CMU_CLKMSK_CARD2, 214 }, 215 }; 216 217 CFATTACH_DECL(vrc4173bcu, sizeof(struct vrc4173bcu_softc), 218 vrc4173bcu_match, vrc4173bcu_attach, NULL, NULL); 219 220 static const struct vrip_chipset_tag vrc4173bcu_chipset_methods = { 221 .vc_power = __vrc4173bcu_power, 222 .vc_intr_establish = __vrc4173bcu_intr_establish, 223 .vc_intr_disestablish = __vrc4173bcu_intr_disestablish, 224 .vc_intr_setmask1 = __vrc4173bcu_intr_setmask1, 225 .vc_intr_setmask2 = __vrc4173bcu_intr_setmask2, 226 .vc_intr_getstatus2 = __vrc4173bcu_intr_getstatus2, 227 .vc_register_cmu = __vrc4173bcu_register_cmu, 228 .vc_register_gpio = __vrc4173bcu_register_gpio, 229 .vc_register_dmaau = __vrc4173bcu_register_dmaau, 230 .vc_register_dcu = __vrc4173bcu_register_dcu, 231 }; 232 233 int 234 vrc4173bcu_match(struct device *parent, struct cfdata *match, void *aux) 235 { 236 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 237 238 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NEC && 239 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NEC_VRC4173_BCU) 240 return (1); 241 242 return (0); 243 } 244 245 void 246 vrc4173bcu_attach(struct device *parent, struct device *self, void *aux) 247 { 248 struct vrc4173bcu_softc *sc = (struct vrc4173bcu_softc *)self; 249 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 250 pci_chipset_tag_t pc = pa->pa_pc; 251 pcitag_t tag = pa->pa_tag; 252 pcireg_t csr; 253 char devinfo[256]; 254 u_int16_t reg; 255 pci_intr_handle_t ih; 256 const char *intrstr; 257 int bus, device, function; 258 #ifdef DEBUG 259 char buf[80]; 260 #endif 261 262 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 263 printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 264 265 #if 0 266 printf("%s: ", sc->sc_dev.dv_xname); 267 pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 268 #endif 269 270 sc->sc_pc = pc; 271 sc->sc_cmuchip.cc_sc = sc; 272 sc->sc_cmuchip.cc_clock = __vrc4173bcu_clock; 273 sc->sc_units = vrc4173bcu_units; 274 sc->sc_nunits = sizeof(vrc4173bcu_units)/sizeof(struct vrc4173bcu_unit); 275 sc->sc_chipset = vrc4173bcu_chipset_methods; /* structure assignment */ 276 sc->sc_chipset.vc_sc = sc; 277 278 sc->sc_platdep = platid_search(&platid, platdep_table, 279 sizeof(platdep_table)/sizeof(*platdep_table), 280 sizeof(*platdep_table)); 281 282 /* Map I/O registers */ 283 if (pci_mapreg_map(pa, VRC4173BCU_BADR, PCI_MAPREG_TYPE_IO, 0, 284 &sc->sc_iot, &sc->sc_ioh, NULL, &sc->sc_size)) { 285 printf("%s: can't map mem space\n", sc->sc_dev.dv_xname); 286 return; 287 } 288 289 /* Enable the device. */ 290 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 291 DPRINTF(("%s: csr = 0x%08x", sc->sc_dev.dv_xname, csr)); 292 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 293 csr | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_IO_ENABLE); 294 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 295 DPRINTF((" -> 0x%08x\n", csr)); 296 297 csr = pci_conf_read(pc, tag, VRC4173BCU_BADR); 298 DPRINTF(("%s: base addr = %x@0x%08x\n", sc->sc_dev.dv_xname, 299 (int)sc->sc_size, csr)); 300 DPRINTF(("%s: iot = 0x%08x, ioh = 0x%08x\n", sc->sc_dev.dv_xname, 301 (int)sc->sc_iot, (int)sc->sc_ioh)); 302 303 /* 304 * Map I/O space for ICU. 305 */ 306 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 307 VRC4173ICU_IOBASE, VRC4173ICU_IOSIZE, &sc->sc_icuh)) { 308 printf(": can't map ICU i/o space\n"); 309 return; 310 } 311 312 /* 313 * Map I/O space for CMU. 314 */ 315 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 316 VRC4173CMU_IOBASE, VRC4173CMU_IOSIZE, &sc->sc_cmuh)) { 317 printf(": can't map CMU i/o space\n"); 318 return; 319 } 320 321 /* machine dependent setup */ 322 if (sc->sc_platdep->clkmask == USE_WINCE_CLKMASK) { 323 /* XXX, You can nothing! */ 324 reg = bus_space_read_2(sc->sc_iot, sc->sc_cmuh, 325 VRC4173CMU_CLKMSK); 326 printf("%s: default clock mask is %04x\n", 327 sc->sc_dev.dv_xname, reg); 328 } else { 329 /* assert all reset bits */ 330 bus_space_write_2(sc->sc_iot, sc->sc_cmuh, VRC4173CMU_SRST, 331 VRC4173CMU_SRST_AC97 | VRC4173CMU_SRST_USB | 332 VRC4173CMU_SRST_CARD2 | VRC4173CMU_SRST_CARD1); 333 /* set clock mask */ 334 bus_space_write_2(sc->sc_iot, sc->sc_cmuh, 335 VRC4173CMU_CLKMSK, sc->sc_platdep->clkmask); 336 /* clear reset bit */ 337 bus_space_write_2(sc->sc_iot, sc->sc_cmuh, VRC4173CMU_SRST, 0); 338 } 339 340 #ifdef DEBUG 341 reg = bus_space_read_2(sc->sc_iot, sc->sc_icuh, VRC4173ICU_SYSINT1); 342 bitmask_snprintf(reg, 343 "\20\1USB\2PCMCIA2\3PCMCIA1\4PS2CH2\5PS2CH1\6PIU\7AIU\10KIU" 344 "\11GIU\12AC97\13AC97-1\14B11\15B12\16DOZEPIU\17B14\20B15", 345 buf, sizeof(buf)); 346 printf("%s: SYSINT1 = 0x%s\n", sc->sc_dev.dv_xname, buf); 347 348 reg = bus_space_read_2(sc->sc_iot, sc->sc_icuh, VRC4173ICU_MKIUINT); 349 bitmask_snprintf(reg, 350 "\20\1SCANINT\2KDATRDY\3KDATLOST\4B3\5B4\6B5\7B6\10B7" 351 "\11B8\12B9\13B10\14B11\15B12\16B13\17B14\20B15", 352 buf, sizeof(buf)); 353 printf("%s: MKIUINT = 0x%s\n", sc->sc_dev.dv_xname, buf); 354 355 reg = bus_space_read_2(sc->sc_iot, sc->sc_icuh, VRC4173ICU_MSYSINT1); 356 bitmask_snprintf(reg, 357 "\20\1USB\2PCMCIA2\3PCMCIA1\4PS2CH2\5PS2CH1\6PIU\7AIU\10KIU" 358 "\11GIU\12AC97\13AC97-1\14B11\15B12\16DOZEPIU\17B14\20B15", 359 buf, sizeof(buf)); 360 printf("%s: MSYSINT1 = 0x%s\n", sc->sc_dev.dv_xname, buf); 361 362 #if 1 363 reg = VRC4173ICU_USBINTR | VRC4173ICU_PIUINTR | VRC4173ICU_KIUINTR | 364 VRC4173ICU_DOZEPIUINTR; 365 bus_space_write_2(sc->sc_iot, sc->sc_icuh, VRC4173ICU_MSYSINT1, reg); 366 367 reg = bus_space_read_2(sc->sc_iot, sc->sc_icuh, VRC4173ICU_MSYSINT1); 368 bitmask_snprintf(reg, 369 "\20\1USB\2PCMCIA2\3PCMCIA1\4PS2CH2\5PS2CH1\6PIU\7AIU\10KIU" 370 "\11GIU\12AC97\13AC97-1\14B11\15B12\16DOZEPIU\17B14\20B15", 371 buf, sizeof(buf)); 372 printf("%s: MSYSINT1 = 0x%s\n", sc->sc_dev.dv_xname, buf); 373 #endif 374 #endif 375 376 /* 377 * set interrupt mask 378 */ 379 sc->sc_intrmask = sc->sc_platdep->intrmask; 380 bus_space_write_2(sc->sc_iot, sc->sc_icuh, VRC4173ICU_MSYSINT1, 381 sc->sc_intrmask); 382 383 /* 384 * install interrupt handler 385 */ 386 if (pci_intr_map(pa, &ih)) { 387 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 388 return; 389 } 390 intrstr = pci_intr_string(pc, ih); 391 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, vrc4173bcu_intr, sc); 392 if (sc->sc_ih == NULL) { 393 printf("%s: couldn't establish interrupt", 394 sc->sc_dev.dv_xname); 395 if (intrstr != NULL) 396 printf(" at %s", intrstr); 397 printf("\n"); 398 return; 399 } 400 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 401 402 /* 403 * install pci intr hooks 404 */ 405 pci_decompose_tag(pc, pa->pa_intrtag, &bus, &device, &function); 406 /* USB unit */ 407 if (sc->sc_intrmask & (1 << VRC4173ICU_USBINTR)) 408 vrip_intr_establish(&sc->sc_chipset, VRIP_UNIT_USBU, 0, 409 IPL_NET, vrc4173bcu_pci_intr, 410 config_connect(CONFIG_HOOK_PCIINTR, 411 CONFIG_HOOK_PCIINTR_ID(bus, device, 2))); 412 /* PC card unit 1 */ 413 if (sc->sc_intrmask & (1 << VRC4173ICU_PCMCIA1INTR)) 414 vrip_intr_establish(&sc->sc_chipset, VRIP_UNIT_CARDU0, 0, 415 IPL_NET, vrc4173bcu_pci_intr, 416 config_connect(CONFIG_HOOK_PCIINTR, 417 CONFIG_HOOK_PCIINTR_ID(bus, 1, 0))); 418 /* PC card unit 2 */ 419 if (sc->sc_intrmask & (1 << VRC4173ICU_PCMCIA2INTR)) 420 vrip_intr_establish(&sc->sc_chipset, VRIP_UNIT_CARDU1, 0, 421 IPL_NET, vrc4173bcu_pci_intr, 422 config_connect(CONFIG_HOOK_PCIINTR, 423 CONFIG_HOOK_PCIINTR_ID(bus, 2, 0))); 424 425 /* 426 * Attach each devices 427 * sc->sc_pri = 2~1 428 */ 429 for (sc->sc_pri = 2; 0 < sc->sc_pri; sc->sc_pri--) 430 config_search_ia(vrc4173bcu_search, self, "vripif", 431 vrc4173bcu_print); 432 } 433 434 int 435 vrc4173bcu_print(void *aux, const char *hoge) 436 { 437 struct vrip_attach_args *va = (struct vrip_attach_args*)aux; 438 439 if (va->va_addr != VRIPIFCF_ADDR_DEFAULT) 440 aprint_normal(" addr 0x%04lx", va->va_addr); 441 if (va->va_size != VRIPIFCF_SIZE_DEFAULT) 442 aprint_normal("-%04lx", 443 (va->va_addr + va->va_size - 1) & 0xffff); 444 if (va->va_addr2 != VRIPIFCF_ADDR2_DEFAULT) 445 aprint_normal(", 0x%04lx", va->va_addr2); 446 if (va->va_size2 != VRIPIFCF_SIZE2_DEFAULT) 447 aprint_normal("-%04lx", 448 (va->va_addr2 + va->va_size2 - 1) & 0xffff); 449 450 return (UNCONF); 451 } 452 453 int 454 vrc4173bcu_search(struct device *parent, struct cfdata *cf, 455 const int *ldesc, void *aux) 456 { 457 struct vrc4173bcu_softc *sc = (struct vrc4173bcu_softc *)parent; 458 struct vrip_attach_args va; 459 460 memset(&va, 0, sizeof(va)); 461 va.va_vc = &sc->sc_chipset; 462 va.va_iot = sc->sc_iot; 463 va.va_parent_ioh = sc->sc_ioh; 464 va.va_unit = cf->cf_loc[VRIPIFCF_UNIT]; 465 va.va_addr = cf->cf_loc[VRIPIFCF_ADDR]; 466 va.va_size = cf->cf_loc[VRIPIFCF_SIZE]; 467 va.va_addr2 = cf->cf_loc[VRIPIFCF_ADDR2]; 468 va.va_size2 = cf->cf_loc[VRIPIFCF_SIZE2]; 469 va.va_gpio_chips = NULL; /* XXX */ 470 va.va_cc = sc->sc_chipset.vc_cc; 471 va.va_ac = sc->sc_chipset.vc_ac; 472 va.va_dc = sc->sc_chipset.vc_dc; 473 if ((config_match(parent, cf, &va) == sc->sc_pri)) 474 config_attach(parent, cf, &va, vrc4173bcu_print); 475 476 return (0); 477 } 478 479 int 480 vrc4173bcu_intr(void *arg) 481 { 482 struct vrc4173bcu_softc *sc = (struct vrc4173bcu_softc *)arg; 483 u_int16_t reg; 484 struct vrc4173bcu_intrhand *ih; 485 int i; 486 487 reg = bus_space_read_2(sc->sc_iot, sc->sc_icuh, VRC4173ICU_SYSINT1); 488 reg &= sc->sc_intrmask; 489 if (reg == 0) 490 return (0); 491 492 #if 0 493 { 494 char buf[80]; 495 bitmask_snprintf(reg, 496 "\20\1USB\2PCMCIA2\3PCMCIA1\4PS2CH2\5PS2CH1\6PIU\7AIU\10KIU" 497 "\11GIU\12AC97\13AC97-1\14B11\15B12\16DOZEPIU\17B14\20B15", 498 buf, sizeof(buf)); 499 printf("%s: %s\n", sc->sc_dev.dv_xname, buf); 500 } 501 #endif 502 for (ih = sc->sc_intrhands, i = 0; i < VRC4173BCU_NINTRS; i++, ih++) 503 if ((reg & (1 << i)) && ih->ih_fun != NULL) 504 ih->ih_fun(ih->ih_arg); 505 506 return (1); 507 } 508 509 static int 510 vrc4173bcu_pci_intr(void *arg) 511 { 512 config_call_tag ct = (config_call_tag)arg; 513 config_connected_call(ct, NULL); 514 515 return (0); 516 } 517 518 #ifdef VRC4173BCU_DEBUG 519 static void 520 vrc4173bcu_dump_level2mask(vrip_chipset_tag_t vc, vrip_intr_handle_t handle) 521 { 522 struct vrc4173bcu_softc *sc = vc->vc_sc; 523 struct vrc4173bcu_intrhand *ih = handle; 524 const struct vrc4173bcu_unit *vu = ih->ih_unit; 525 u_int32_t reg; 526 527 if (vu->vu_mlreg) { 528 DPRINTF(("level1[%d] level2 mask:", vu->vu_intr[0])); 529 reg = bus_space_read_2(sc->sc_iot, sc->sc_icuh, vu->vu_mlreg); 530 if (vu->vu_mhreg) { 531 reg |= (bus_space_read_2(sc->sc_iot, sc->sc_icuh, 532 vu->vu_mhreg) << 16); 533 dbg_bit_print(reg); 534 } else 535 dbg_bit_print(reg); 536 } 537 } 538 #endif 539 540 int 541 __vrc4173bcu_power(vrip_chipset_tag_t vc, int unit, int onoff) 542 { 543 struct vrc4173bcu_softc *sc = vc->vc_sc; 544 const struct vrc4173bcu_unit *vu; 545 546 if (sc->sc_chipset.vc_cc == NULL) 547 return (0); /* You have no clock mask unit yet. */ 548 if (!VALID_UNIT(sc, unit)) 549 return (0); 550 vu = &sc->sc_units[unit]; 551 552 return (*sc->sc_chipset.vc_cc->cc_clock)(sc->sc_chipset.vc_cc, 553 vu->vu_clkmask, onoff); 554 } 555 556 vrip_intr_handle_t 557 __vrc4173bcu_intr_establish(vrip_chipset_tag_t vc, int unit, int line, 558 int level, int (*ih_fun)(void *), void *ih_arg) 559 { 560 struct vrc4173bcu_softc *sc = vc->vc_sc; 561 const struct vrc4173bcu_unit *vu; 562 struct vrc4173bcu_intrhand *ih; 563 564 if (!VALID_UNIT(sc, unit)) 565 return (NULL); 566 vu = &sc->sc_units[unit]; 567 ih = &sc->sc_intrhands[vu->vu_intr[line]]; 568 if (ih->ih_fun) /* Can't share level 1 interrupt */ 569 return (NULL); 570 ih->ih_fun = ih_fun; 571 ih->ih_arg = ih_arg; 572 ih->ih_unit = vu; 573 574 /* Mask level 2 interrupt mask register. (disable interrupt) */ 575 vrip_intr_setmask2(vc, ih, ~0, 0); 576 /* Unmask Level 1 interrupt mask register (enable interrupt) */ 577 vrip_intr_setmask1(vc, ih, 1); 578 579 return ((void *)ih); 580 } 581 582 void 583 __vrc4173bcu_intr_disestablish(vrip_chipset_tag_t vc, vrip_intr_handle_t handle) 584 { 585 struct vrc4173bcu_intrhand *ih = handle; 586 587 /* Mask Level 1 interrupt mask register (disable interrupt) */ 588 vrip_intr_setmask1(vc, ih, 0); 589 /* Mask level 2 interrupt mask register(if any). (disable interrupt) */ 590 vrip_intr_setmask2(vc, ih, ~0, 0); 591 ih->ih_fun = NULL; 592 ih->ih_arg = NULL; 593 } 594 595 /* Set level 1 interrupt mask. */ 596 void 597 __vrc4173bcu_intr_setmask1(vrip_chipset_tag_t vc, vrip_intr_handle_t handle, 598 int enable) 599 { 600 struct vrc4173bcu_softc *sc = vc->vc_sc; 601 struct vrc4173bcu_intrhand *ih = handle; 602 int level1 = ih - sc->sc_intrhands; 603 604 DPRINTF(("__vrc4173bcu_intr_setmask1: SYSINT: %s %d\n", 605 enable ? "enable" : "disable", level1)); 606 if (enable) 607 sc->sc_intrmask |= (1 << level1); 608 else 609 sc->sc_intrmask &= ~(1 << level1); 610 bus_space_write_2 (sc->sc_iot, sc->sc_icuh, VRC4173ICU_MSYSINT1, 611 sc->sc_intrmask); 612 #ifdef VRC4173BCU_DEBUG 613 if (vrc4173bcu_debug) 614 dbg_bit_print(sc->sc_intrmask); 615 #endif 616 617 return; 618 } 619 620 /* Get level 2 interrupt status */ 621 void 622 __vrc4173bcu_intr_getstatus2(vrip_chipset_tag_t vc, vrip_intr_handle_t handle, 623 u_int32_t *status /* Level 2 status */) 624 { 625 struct vrc4173bcu_softc *sc = vc->vc_sc; 626 struct vrc4173bcu_intrhand *ih = handle; 627 const struct vrc4173bcu_unit *vu = ih->ih_unit; 628 u_int32_t reg; 629 630 reg = bus_space_read_2(sc->sc_iot, sc->sc_icuh, vu->vu_lreg); 631 reg |= (bus_space_read_2(sc->sc_iot, sc->sc_icuh, vu->vu_hreg) << 16); 632 *status = reg; 633 } 634 635 /* Set level 2 interrupt mask. */ 636 void 637 __vrc4173bcu_intr_setmask2(vrip_chipset_tag_t vc, vrip_intr_handle_t handle, 638 u_int32_t mask /* Level 2 mask */, int onoff) 639 { 640 struct vrc4173bcu_softc *sc = vc->vc_sc; 641 struct vrc4173bcu_intrhand *ih = handle; 642 const struct vrc4173bcu_unit *vu = ih->ih_unit; 643 u_int16_t reg; 644 645 DPRINTF(("vrc4173bcu_intr_setmask2:\n")); 646 #ifdef VRC4173BCU_DEBUG 647 if (vrc4173bcu_debug) 648 vrc4173bcu_dump_level2mask(vc, handle); 649 #endif 650 if (vu->vu_mlreg) { 651 reg = bus_space_read_2(sc->sc_iot, sc->sc_icuh, vu->vu_mlreg); 652 if (onoff) 653 reg |= (mask & 0xffff); 654 else 655 reg &= ~(mask & 0xffff); 656 bus_space_write_2(sc->sc_iot, sc->sc_ioh, vu->vu_mlreg, reg); 657 } 658 if (vu->vu_mhreg) { 659 reg = bus_space_read_2(sc->sc_iot, sc->sc_icuh, vu->vu_mhreg); 660 if (onoff) 661 reg |= ((mask >> 16) & 0xffff); 662 else 663 reg &= ~((mask >> 16) & 0xffff); 664 bus_space_write_2(sc->sc_iot, sc->sc_icuh, vu->vu_mhreg, reg); 665 } 666 #ifdef VRC4173BCU_DEBUG 667 if (vrc4173bcu_debug) 668 vrc4173bcu_dump_level2mask(vc, handle); 669 #endif 670 671 return; 672 } 673 674 int 675 __vrc4173bcu_clock(vrcmu_chipset_tag_t cc, u_int16_t mask, int onoff) 676 { 677 struct vrc4173bcu_softc *sc = cc->cc_sc; 678 u_int16_t reg; 679 680 reg = bus_space_read_2(sc->sc_iot, sc->sc_cmuh, VRC4173CMU_CLKMSK); 681 #if 0 682 printf("cmu register(enter):"); 683 dbg_bit_print(reg); 684 #endif 685 if (onoff) 686 reg |= mask; 687 else 688 reg &= ~mask; 689 bus_space_write_2(sc->sc_iot, sc->sc_cmuh, VRC4173CMU_CLKMSK, reg); 690 #if 0 691 printf("cmu register(exit) :"); 692 dbg_bit_print(reg); 693 #endif 694 return (0); 695 } 696 697 void 698 __vrc4173bcu_register_cmu(vrip_chipset_tag_t vc, vrcmu_chipset_tag_t cmu) 699 { 700 vc->vc_cc = cmu; 701 } 702 703 void 704 __vrc4173bcu_register_gpio(vrip_chipset_tag_t vc, hpcio_chip_t chip) 705 { 706 /* XXX, not implemented yet */ 707 } 708 709 void 710 __vrc4173bcu_register_dmaau(vrip_chipset_tag_t vc, vrdmaau_chipset_tag_t dmaau) 711 { 712 713 vc->vc_ac = dmaau; 714 } 715 716 void 717 __vrc4173bcu_register_dcu(vrip_chipset_tag_t vc, vrdcu_chipset_tag_t dcu) 718 { 719 720 vc->vc_dc = dcu; 721 } 722
Indexes created Thu Oct 02 01:09:59 GMT 2025