vrc4173bcu.c revision 1.24.28.2
1 /* $NetBSD: vrc4173bcu.c,v 1.24.28.2 2021/03/20 20:49:43 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2001,2002 Enami Tsugutomo. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: vrc4173bcu.c,v 1.24.28.2 2021/03/20 20:49:43 thorpej Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/device.h> 35 36 #include <machine/bus.h> 37 38 #include <dev/pci/pcivar.h> 39 #include <dev/pci/pcidevs.h> 40 41 #include <machine/platid.h> 42 #include <machine/platid_mask.h> 43 #include <machine/config_hook.h> 44 45 #include <hpcmips/vr/vripunit.h> 46 #include <hpcmips/vr/vripif.h> 47 #include <hpcmips/vr/vrc4173bcuvar.h> 48 #include <hpcmips/vr/vrc4173icureg.h> 49 #include <hpcmips/vr/vrc4173cmureg.h> 50 51 #include "locators.h" 52 53 #ifdef VRC4173BCU_DEBUG 54 #define DPRINTF_ENABLE 55 #define DPRINTF_DEBUG vrc4173bcu_debug 56 #endif 57 #define USE_HPC_DPRINTF 58 #include <machine/debug.h> 59 60 #define VRC4173BCU_BADR 0x10 61 #define USE_WINCE_CLKMASK (~0) 62 63 static int vrc4173bcu_match(device_t, cfdata_t, void *); 64 static void vrc4173bcu_attach(device_t, device_t, void *); 65 static int vrc4173bcu_intr(void *); 66 static int vrc4173bcu_print(void *, const char *); 67 static int vrc4173bcu_search(device_t, cfdata_t, const int *, void *); 68 static int vrc4173bcu_pci_intr(void *); 69 #ifdef VRC4173BCU_DEBUG 70 static void vrc4173bcu_dump_level2mask(vrip_chipset_tag_t, 71 vrip_intr_handle_t); 72 #endif 73 74 int __vrc4173bcu_power(vrip_chipset_tag_t, int, int); 75 vrip_intr_handle_t __vrc4173bcu_intr_establish(vrip_chipset_tag_t, int, int, 76 int, int(*)(void*), void*); 77 void __vrc4173bcu_intr_disestablish(vrip_chipset_tag_t, vrip_intr_handle_t); 78 void __vrc4173bcu_intr_setmask1(vrip_chipset_tag_t, vrip_intr_handle_t, int); 79 void __vrc4173bcu_intr_setmask2(vrip_chipset_tag_t, vrip_intr_handle_t, 80 u_int32_t, int); 81 void __vrc4173bcu_intr_getstatus2(vrip_chipset_tag_t, vrip_intr_handle_t, 82 u_int32_t*); 83 void __vrc4173bcu_register_cmu(vrip_chipset_tag_t, vrcmu_chipset_tag_t); 84 void __vrc4173bcu_register_gpio(vrip_chipset_tag_t, hpcio_chip_t); 85 void __vrc4173bcu_register_dmaau(vrip_chipset_tag_t, vrdmaau_chipset_tag_t); 86 void __vrc4173bcu_register_dcu(vrip_chipset_tag_t, vrdcu_chipset_tag_t); 87 int __vrc4173bcu_clock(vrcmu_chipset_tag_t, u_int16_t, int); 88 89 /* 90 * machine dependent info 91 */ 92 static struct vrc4173bcu_platdep { 93 platid_mask_t *platidmask; 94 u_int32_t clkmask; 95 int intrmask; 96 } platdep_table[] = { 97 { 98 &platid_mask_MACH_VICTOR_INTERLINK_MPC303, 99 USE_WINCE_CLKMASK, /* clock mask */ 100 (1 << VRC4173ICU_USBINTR)| /* intrrupts */ 101 (1 << VRC4173ICU_PCMCIA1INTR)| 102 (1 << VRC4173ICU_PCMCIA2INTR), 103 }, 104 { 105 &platid_mask_MACH_VICTOR_INTERLINK_MPC304, 106 USE_WINCE_CLKMASK, /* clock mask */ 107 (1 << VRC4173ICU_USBINTR)| /* intrrupts */ 108 (1 << VRC4173ICU_PCMCIA1INTR)| 109 (1 << VRC4173ICU_PCMCIA2INTR), 110 }, 111 { 112 &platid_mask_MACH_NEC_MCR_SIGMARION2, 113 USE_WINCE_CLKMASK, /* clock mask */ 114 (1 << VRC4173ICU_USBINTR), /* intrrupts */ 115 }, 116 { 117 &platid_wild, 118 USE_WINCE_CLKMASK, /* XXX */ 119 -1, 120 }, 121 }; 122 123 struct vrc4173bcu_unit { 124 const char *vu_name; 125 int vu_intr[2]; 126 int vu_clkmask; 127 bus_addr_t vu_lreg; 128 bus_addr_t vu_mlreg; 129 bus_addr_t vu_hreg; 130 bus_addr_t vu_mhreg; 131 }; 132 133 struct vrc4173bcu_softc { 134 device_t sc_dev; 135 struct vrip_chipset_tag sc_chipset; 136 struct vrcmu_chipset_tag sc_cmuchip; 137 138 pci_chipset_tag_t sc_pc; 139 bus_space_tag_t sc_iot; 140 bus_space_handle_t sc_ioh; 141 bus_size_t sc_size; 142 143 bus_space_handle_t sc_icuh; /* I/O handle for ICU. */ 144 bus_space_handle_t sc_cmuh; /* I/O handle for CMU. */ 145 void *sc_ih; 146 #define VRC4173BCU_NINTRS 16 147 int sc_intrmask; 148 struct vrc4173bcu_intrhand { 149 int (*ih_fun)(void *); 150 void *ih_arg; 151 const struct vrc4173bcu_unit *ih_unit; 152 } sc_intrhands[32]; 153 154 struct vrc4173bcu_unit *sc_units; 155 int sc_nunits; 156 int sc_pri; 157 158 struct vrc4173bcu_platdep *sc_platdep; 159 }; 160 161 #define VALID_UNIT(sc, unit) (0 <= (unit) && (unit) < (sc)->sc_nunits) 162 163 static struct vrc4173bcu_unit vrc4173bcu_units[] = { 164 [VRIP_UNIT_KIU] = { 165 "kiu", 166 { VRC4173ICU_KIUINTR, }, 167 VRC4173CMU_CLKMSK_KIU, 168 VRC4173ICU_KIUINT, VRC4173ICU_MKIUINT, 169 }, 170 [VRIP_UNIT_PIU] = { 171 "piu", 172 { VRC4173ICU_PIUINTR, VRC4173ICU_DOZEPIUINTR}, 173 VRC4173CMU_CLKMSK_PIU, 174 VRC4173ICU_PIUINT, VRC4173ICU_MPIUINT, 175 }, 176 [VRIP_UNIT_AIU] = { 177 "aiu", 178 { VRC4173ICU_AIUINTR, }, 179 VRC4173CMU_CLKMSK_AIU, 180 VRC4173ICU_AIUINT, VRC4173ICU_MAIUINT, 181 }, 182 [VRIP_UNIT_GIU] = { 183 "giu", 184 { VRC4173ICU_GIUINTR, }, 185 0, 186 VRC4173ICU_GIULINT, VRC4173ICU_MGIULINT, 187 VRC4173ICU_GIUHINT, VRC4173ICU_MGIUHINT, 188 }, 189 [VRIP_UNIT_PS2U0] = { 190 "PS/2-Ch1", 191 { VRC4173ICU_PS2CH1INTR, }, 192 VRC4173CMU_CLKMSK_PS2CH1, 193 }, 194 [VRIP_UNIT_PS2U1] = { 195 "PS/2-Ch2", 196 { VRC4173ICU_PS2CH2INTR, }, 197 VRC4173CMU_CLKMSK_PS2CH2, 198 }, 199 [VRIP_UNIT_USBU] = { 200 "usbu", 201 { VRC4173ICU_USBINTR, }, 202 VRC4173CMU_CLKMSK_USB, 203 }, 204 [VRIP_UNIT_CARDU0] = { 205 "cardu0", 206 { VRC4173ICU_PCMCIA1INTR, }, 207 VRC4173CMU_CLKMSK_CARD1, 208 }, 209 [VRIP_UNIT_CARDU1] = { 210 "cardu1", 211 { VRC4173ICU_PCMCIA2INTR, }, 212 VRC4173CMU_CLKMSK_CARD2, 213 }, 214 }; 215 216 CFATTACH_DECL_NEW(vrc4173bcu, sizeof(struct vrc4173bcu_softc), 217 vrc4173bcu_match, vrc4173bcu_attach, NULL, NULL); 218 219 static const struct vrip_chipset_tag vrc4173bcu_chipset_methods = { 220 .vc_power = __vrc4173bcu_power, 221 .vc_intr_establish = __vrc4173bcu_intr_establish, 222 .vc_intr_disestablish = __vrc4173bcu_intr_disestablish, 223 .vc_intr_setmask1 = __vrc4173bcu_intr_setmask1, 224 .vc_intr_setmask2 = __vrc4173bcu_intr_setmask2, 225 .vc_intr_getstatus2 = __vrc4173bcu_intr_getstatus2, 226 .vc_register_cmu = __vrc4173bcu_register_cmu, 227 .vc_register_gpio = __vrc4173bcu_register_gpio, 228 .vc_register_dmaau = __vrc4173bcu_register_dmaau, 229 .vc_register_dcu = __vrc4173bcu_register_dcu, 230 }; 231 232 int 233 vrc4173bcu_match(device_t parent, cfdata_t match, void *aux) 234 { 235 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 236 237 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NEC && 238 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NEC_VRC4173_BCU) 239 return (1); 240 241 return (0); 242 } 243 244 void 245 vrc4173bcu_attach(device_t parent, device_t self, void *aux) 246 { 247 struct vrc4173bcu_softc *sc = device_private(self); 248 struct pci_attach_args *pa = aux; 249 pci_chipset_tag_t pc = pa->pa_pc; 250 pcitag_t tag = pa->pa_tag; 251 pcireg_t csr; 252 char devinfo[256]; 253 u_int16_t reg; 254 pci_intr_handle_t ih; 255 const char *intrstr; 256 int bus, device, function; 257 char ibuf[PCI_INTRSTR_LEN]; 258 #ifdef DEBUG 259 char buf[80]; 260 #endif 261 262 sc->sc_dev = self; 263 264 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 265 printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 266 267 #if 0 268 printf("%s: ", device_xname(self)); 269 pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 270 #endif 271 272 sc->sc_pc = pc; 273 sc->sc_cmuchip.cc_sc = sc; 274 sc->sc_cmuchip.cc_clock = __vrc4173bcu_clock; 275 sc->sc_units = vrc4173bcu_units; 276 sc->sc_nunits = sizeof(vrc4173bcu_units)/sizeof(struct vrc4173bcu_unit); 277 sc->sc_chipset = vrc4173bcu_chipset_methods; /* structure assignment */ 278 sc->sc_chipset.vc_sc = sc; 279 280 sc->sc_platdep = platid_search(&platid, platdep_table, 281 sizeof(platdep_table)/sizeof(*platdep_table), 282 sizeof(*platdep_table)); 283 284 /* Map I/O registers */ 285 if (pci_mapreg_map(pa, VRC4173BCU_BADR, PCI_MAPREG_TYPE_IO, 0, 286 &sc->sc_iot, &sc->sc_ioh, NULL, &sc->sc_size)) { 287 printf("%s: can't map mem space\n", device_xname(self)); 288 return; 289 } 290 291 /* Enable the device. */ 292 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 293 DPRINTF(("%s: csr = 0x%08x", device_xname(self), csr)); 294 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 295 csr | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_IO_ENABLE); 296 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 297 DPRINTF((" -> 0x%08x\n", csr)); 298 299 csr = pci_conf_read(pc, tag, VRC4173BCU_BADR); 300 DPRINTF(("%s: base addr = %x@0x%08x\n", device_xname(self), 301 (int)sc->sc_size, csr)); 302 DPRINTF(("%s: iot = 0x%08x, ioh = 0x%08x\n", device_xname(self), 303 (int)sc->sc_iot, (int)sc->sc_ioh)); 304 305 /* 306 * Map I/O space for ICU. 307 */ 308 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 309 VRC4173ICU_IOBASE, VRC4173ICU_IOSIZE, &sc->sc_icuh)) { 310 printf(": can't map ICU i/o space\n"); 311 return; 312 } 313 314 /* 315 * Map I/O space for CMU. 316 */ 317 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 318 VRC4173CMU_IOBASE, VRC4173CMU_IOSIZE, &sc->sc_cmuh)) { 319 printf(": can't map CMU i/o space\n"); 320 return; 321 } 322 323 /* machine dependent setup */ 324 if (sc->sc_platdep->clkmask == USE_WINCE_CLKMASK) { 325 /* XXX, You can nothing! */ 326 reg = bus_space_read_2(sc->sc_iot, sc->sc_cmuh, 327 VRC4173CMU_CLKMSK); 328 printf("%s: default clock mask is %04x\n", 329 device_xname(self), reg); 330 } else { 331 /* assert all reset bits */ 332 bus_space_write_2(sc->sc_iot, sc->sc_cmuh, VRC4173CMU_SRST, 333 VRC4173CMU_SRST_AC97 | VRC4173CMU_SRST_USB | 334 VRC4173CMU_SRST_CARD2 | VRC4173CMU_SRST_CARD1); 335 /* set clock mask */ 336 bus_space_write_2(sc->sc_iot, sc->sc_cmuh, 337 VRC4173CMU_CLKMSK, sc->sc_platdep->clkmask); 338 /* clear reset bit */ 339 bus_space_write_2(sc->sc_iot, sc->sc_cmuh, VRC4173CMU_SRST, 0); 340 } 341 342 #ifdef DEBUG 343 reg = bus_space_read_2(sc->sc_iot, sc->sc_icuh, VRC4173ICU_SYSINT1); 344 snprintb(buf, sizeof(buf), 345 "\20\1USB\2PCMCIA2\3PCMCIA1\4PS2CH2\5PS2CH1\6PIU\7AIU\10KIU" 346 "\11GIU\12AC97\13AC97-1\14B11\15B12\16DOZEPIU\17B14\20B15", reg); 347 printf("%s: SYSINT1 = %s\n", device_xname(self), buf); 348 349 reg = bus_space_read_2(sc->sc_iot, sc->sc_icuh, VRC4173ICU_MKIUINT); 350 snprintb(buf, sizeof(buf), 351 "\20\1SCANINT\2KDATRDY\3KDATLOST\4B3\5B4\6B5\7B6\10B7" 352 "\11B8\12B9\13B10\14B11\15B12\16B13\17B14\20B15", reg); 353 printf("%s: MKIUINT = %s\n", device_xname(self), buf); 354 355 reg = bus_space_read_2(sc->sc_iot, sc->sc_icuh, VRC4173ICU_MSYSINT1); 356 snprintb(buf, sizeof(buf), 357 "\20\1USB\2PCMCIA2\3PCMCIA1\4PS2CH2\5PS2CH1\6PIU\7AIU\10KIU" 358 "\11GIU\12AC97\13AC97-1\14B11\15B12\16DOZEPIU\17B14\20B15", reg); 359 printf("%s: MSYSINT1 = %s\n", device_xname(self), buf); 360 361 #if 1 362 reg = VRC4173ICU_USBINTR | VRC4173ICU_PIUINTR | VRC4173ICU_KIUINTR | 363 VRC4173ICU_DOZEPIUINTR; 364 bus_space_write_2(sc->sc_iot, sc->sc_icuh, VRC4173ICU_MSYSINT1, reg); 365 366 reg = bus_space_read_2(sc->sc_iot, sc->sc_icuh, VRC4173ICU_MSYSINT1); 367 snprintb(buf, sizeof(buf), 368 "\20\1USB\2PCMCIA2\3PCMCIA1\4PS2CH2\5PS2CH1\6PIU\7AIU\10KIU" 369 "\11GIU\12AC97\13AC97-1\14B11\15B12\16DOZEPIU\17B14\20B15", reg); 370 printf("%s: MSYSINT1 = %s\n", device_xname(self), buf); 371 #endif 372 #endif 373 374 /* 375 * set interrupt mask 376 */ 377 sc->sc_intrmask = sc->sc_platdep->intrmask; 378 bus_space_write_2(sc->sc_iot, sc->sc_icuh, VRC4173ICU_MSYSINT1, 379 sc->sc_intrmask); 380 381 /* 382 * install interrupt handler 383 */ 384 if (pci_intr_map(pa, &ih)) { 385 printf("%s: couldn't map interrupt\n", device_xname(self)); 386 return; 387 } 388 intrstr = pci_intr_string(pc, ih, ibuf, sizeof(ibuf)); 389 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, vrc4173bcu_intr, sc); 390 if (sc->sc_ih == NULL) { 391 printf("%s: couldn't establish interrupt", 392 device_xname(self)); 393 if (intrstr != NULL) 394 printf(" at %s", intrstr); 395 printf("\n"); 396 return; 397 } 398 printf("%s: interrupting at %s\n", device_xname(self), intrstr); 399 400 /* 401 * install pci intr hooks 402 */ 403 pci_decompose_tag(pc, pa->pa_intrtag, &bus, &device, &function); 404 /* USB unit */ 405 if (sc->sc_intrmask & (1 << VRC4173ICU_USBINTR)) 406 vrip_intr_establish(&sc->sc_chipset, VRIP_UNIT_USBU, 0, 407 IPL_NET, vrc4173bcu_pci_intr, 408 config_connect(CONFIG_HOOK_PCIINTR, 409 CONFIG_HOOK_PCIINTR_ID(bus, device, 2))); 410 /* PC card unit 1 */ 411 if (sc->sc_intrmask & (1 << VRC4173ICU_PCMCIA1INTR)) 412 vrip_intr_establish(&sc->sc_chipset, VRIP_UNIT_CARDU0, 0, 413 IPL_NET, vrc4173bcu_pci_intr, 414 config_connect(CONFIG_HOOK_PCIINTR, 415 CONFIG_HOOK_PCIINTR_ID(bus, 1, 0))); 416 /* PC card unit 2 */ 417 if (sc->sc_intrmask & (1 << VRC4173ICU_PCMCIA2INTR)) 418 vrip_intr_establish(&sc->sc_chipset, VRIP_UNIT_CARDU1, 0, 419 IPL_NET, vrc4173bcu_pci_intr, 420 config_connect(CONFIG_HOOK_PCIINTR, 421 CONFIG_HOOK_PCIINTR_ID(bus, 2, 0))); 422 423 /* 424 * Attach each devices 425 * sc->sc_pri = 2~1 426 */ 427 for (sc->sc_pri = 2; 0 < sc->sc_pri; sc->sc_pri--) { 428 config_search(self, NULL, 429 CFARG_SUBMATCH, vrc4173bcu_search, 430 CFARG_IATTR, "vripif", 431 CFARG_EOL); 432 } 433 } 434 435 int 436 vrc4173bcu_print(void *aux, const char *hoge) 437 { 438 struct vrip_attach_args *va = (struct vrip_attach_args*)aux; 439 440 if (va->va_addr != VRIPIFCF_ADDR_DEFAULT) 441 aprint_normal(" addr 0x%04lx", va->va_addr); 442 if (va->va_size != VRIPIFCF_SIZE_DEFAULT) 443 aprint_normal("-%04lx", 444 (va->va_addr + va->va_size - 1) & 0xffff); 445 if (va->va_addr2 != VRIPIFCF_ADDR2_DEFAULT) 446 aprint_normal(", 0x%04lx", va->va_addr2); 447 if (va->va_size2 != VRIPIFCF_SIZE2_DEFAULT) 448 aprint_normal("-%04lx", 449 (va->va_addr2 + va->va_size2 - 1) & 0xffff); 450 451 return (UNCONF); 452 } 453 454 int 455 vrc4173bcu_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 456 { 457 struct vrc4173bcu_softc *sc = device_private(parent); 458 struct vrip_attach_args va; 459 460 memset(&va, 0, sizeof(va)); 461 va.va_vc = &sc->sc_chipset; 462 va.va_iot = sc->sc_iot; 463 va.va_parent_ioh = sc->sc_ioh; 464 va.va_unit = cf->cf_loc[VRIPIFCF_UNIT]; 465 va.va_addr = cf->cf_loc[VRIPIFCF_ADDR]; 466 va.va_size = cf->cf_loc[VRIPIFCF_SIZE]; 467 va.va_addr2 = cf->cf_loc[VRIPIFCF_ADDR2]; 468 va.va_size2 = cf->cf_loc[VRIPIFCF_SIZE2]; 469 va.va_gpio_chips = NULL; /* XXX */ 470 va.va_cc = sc->sc_chipset.vc_cc; 471 va.va_ac = sc->sc_chipset.vc_ac; 472 va.va_dc = sc->sc_chipset.vc_dc; 473 if ((config_match(parent, cf, &va) == sc->sc_pri)) 474 config_attach(parent, cf, &va, vrc4173bcu_print); 475 476 return (0); 477 } 478 479 int 480 vrc4173bcu_intr(void *arg) 481 { 482 struct vrc4173bcu_softc *sc = (struct vrc4173bcu_softc *)arg; 483 u_int16_t reg; 484 struct vrc4173bcu_intrhand *ih; 485 int i; 486 487 reg = bus_space_read_2(sc->sc_iot, sc->sc_icuh, VRC4173ICU_SYSINT1); 488 reg &= sc->sc_intrmask; 489 if (reg == 0) 490 return (0); 491 492 #if 0 493 { 494 char buf[80]; 495 snprintb(buf, sizeof(buf), 496 "\20\1USB\2PCMCIA2\3PCMCIA1\4PS2CH2\5PS2CH1\6PIU\7AIU\10KIU" 497 "\11GIU\12AC97\13AC97-1\14B11\15B12\16DOZEPIU\17B14\20B15", reg); 498 printf("%s: %s\n", device_xname(sc->sc_dev), buf); 499 } 500 #endif 501 for (ih = sc->sc_intrhands, i = 0; i < VRC4173BCU_NINTRS; i++, ih++) 502 if ((reg & (1 << i)) && ih->ih_fun != NULL) 503 ih->ih_fun(ih->ih_arg); 504 505 return (1); 506 } 507 508 static int 509 vrc4173bcu_pci_intr(void *arg) 510 { 511 config_call_tag ct = (config_call_tag)arg; 512 config_connected_call(ct, NULL); 513 514 return (0); 515 } 516 517 #ifdef VRC4173BCU_DEBUG 518 static void 519 vrc4173bcu_dump_level2mask(vrip_chipset_tag_t vc, vrip_intr_handle_t handle) 520 { 521 struct vrc4173bcu_softc *sc = vc->vc_sc; 522 struct vrc4173bcu_intrhand *ih = handle; 523 const struct vrc4173bcu_unit *vu = ih->ih_unit; 524 u_int32_t reg; 525 526 if (vu->vu_mlreg) { 527 DPRINTF(("level1[%d] level2 mask:", vu->vu_intr[0])); 528 reg = bus_space_read_2(sc->sc_iot, sc->sc_icuh, vu->vu_mlreg); 529 if (vu->vu_mhreg) { 530 reg |= (bus_space_read_2(sc->sc_iot, sc->sc_icuh, 531 vu->vu_mhreg) << 16); 532 dbg_bit_print(reg); 533 } else 534 dbg_bit_print(reg); 535 } 536 } 537 #endif 538 539 int 540 __vrc4173bcu_power(vrip_chipset_tag_t vc, int unit, int onoff) 541 { 542 struct vrc4173bcu_softc *sc = vc->vc_sc; 543 const struct vrc4173bcu_unit *vu; 544 545 if (sc->sc_chipset.vc_cc == NULL) 546 return (0); /* You have no clock mask unit yet. */ 547 if (!VALID_UNIT(sc, unit)) 548 return (0); 549 vu = &sc->sc_units[unit]; 550 551 return (*sc->sc_chipset.vc_cc->cc_clock)(sc->sc_chipset.vc_cc, 552 vu->vu_clkmask, onoff); 553 } 554 555 vrip_intr_handle_t 556 __vrc4173bcu_intr_establish(vrip_chipset_tag_t vc, int unit, int line, 557 int level, int (*ih_fun)(void *), void *ih_arg) 558 { 559 struct vrc4173bcu_softc *sc = vc->vc_sc; 560 const struct vrc4173bcu_unit *vu; 561 struct vrc4173bcu_intrhand *ih; 562 563 if (!VALID_UNIT(sc, unit)) 564 return (NULL); 565 vu = &sc->sc_units[unit]; 566 ih = &sc->sc_intrhands[vu->vu_intr[line]]; 567 if (ih->ih_fun) /* Can't share level 1 interrupt */ 568 return (NULL); 569 ih->ih_fun = ih_fun; 570 ih->ih_arg = ih_arg; 571 ih->ih_unit = vu; 572 573 /* Mask level 2 interrupt mask register. (disable interrupt) */ 574 vrip_intr_setmask2(vc, ih, ~0, 0); 575 /* Unmask Level 1 interrupt mask register (enable interrupt) */ 576 vrip_intr_setmask1(vc, ih, 1); 577 578 return ((void *)ih); 579 } 580 581 void 582 __vrc4173bcu_intr_disestablish(vrip_chipset_tag_t vc, vrip_intr_handle_t handle) 583 { 584 struct vrc4173bcu_intrhand *ih = handle; 585 586 /* Mask Level 1 interrupt mask register (disable interrupt) */ 587 vrip_intr_setmask1(vc, ih, 0); 588 /* Mask level 2 interrupt mask register(if any). (disable interrupt) */ 589 vrip_intr_setmask2(vc, ih, ~0, 0); 590 ih->ih_fun = NULL; 591 ih->ih_arg = NULL; 592 } 593 594 /* Set level 1 interrupt mask. */ 595 void 596 __vrc4173bcu_intr_setmask1(vrip_chipset_tag_t vc, vrip_intr_handle_t handle, 597 int enable) 598 { 599 struct vrc4173bcu_softc *sc = vc->vc_sc; 600 struct vrc4173bcu_intrhand *ih = handle; 601 int level1 = ih - sc->sc_intrhands; 602 603 DPRINTF(("__vrc4173bcu_intr_setmask1: SYSINT: %s %d\n", 604 enable ? "enable" : "disable", level1)); 605 if (enable) 606 sc->sc_intrmask |= (1 << level1); 607 else 608 sc->sc_intrmask &= ~(1 << level1); 609 bus_space_write_2 (sc->sc_iot, sc->sc_icuh, VRC4173ICU_MSYSINT1, 610 sc->sc_intrmask); 611 #ifdef VRC4173BCU_DEBUG 612 if (vrc4173bcu_debug) 613 dbg_bit_print(sc->sc_intrmask); 614 #endif 615 616 return; 617 } 618 619 /* Get level 2 interrupt status */ 620 void 621 __vrc4173bcu_intr_getstatus2(vrip_chipset_tag_t vc, vrip_intr_handle_t handle, 622 u_int32_t *status /* Level 2 status */) 623 { 624 struct vrc4173bcu_softc *sc = vc->vc_sc; 625 struct vrc4173bcu_intrhand *ih = handle; 626 const struct vrc4173bcu_unit *vu = ih->ih_unit; 627 u_int32_t reg; 628 629 reg = bus_space_read_2(sc->sc_iot, sc->sc_icuh, vu->vu_lreg); 630 reg |= (bus_space_read_2(sc->sc_iot, sc->sc_icuh, vu->vu_hreg) << 16); 631 *status = reg; 632 } 633 634 /* Set level 2 interrupt mask. */ 635 void 636 __vrc4173bcu_intr_setmask2(vrip_chipset_tag_t vc, vrip_intr_handle_t handle, 637 u_int32_t mask /* Level 2 mask */, int onoff) 638 { 639 struct vrc4173bcu_softc *sc = vc->vc_sc; 640 struct vrc4173bcu_intrhand *ih = handle; 641 const struct vrc4173bcu_unit *vu = ih->ih_unit; 642 u_int16_t reg; 643 644 DPRINTF(("vrc4173bcu_intr_setmask2:\n")); 645 #ifdef VRC4173BCU_DEBUG 646 if (vrc4173bcu_debug) 647 vrc4173bcu_dump_level2mask(vc, handle); 648 #endif 649 if (vu->vu_mlreg) { 650 reg = bus_space_read_2(sc->sc_iot, sc->sc_icuh, vu->vu_mlreg); 651 if (onoff) 652 reg |= (mask & 0xffff); 653 else 654 reg &= ~(mask & 0xffff); 655 bus_space_write_2(sc->sc_iot, sc->sc_ioh, vu->vu_mlreg, reg); 656 } 657 if (vu->vu_mhreg) { 658 reg = bus_space_read_2(sc->sc_iot, sc->sc_icuh, vu->vu_mhreg); 659 if (onoff) 660 reg |= ((mask >> 16) & 0xffff); 661 else 662 reg &= ~((mask >> 16) & 0xffff); 663 bus_space_write_2(sc->sc_iot, sc->sc_icuh, vu->vu_mhreg, reg); 664 } 665 #ifdef VRC4173BCU_DEBUG 666 if (vrc4173bcu_debug) 667 vrc4173bcu_dump_level2mask(vc, handle); 668 #endif 669 670 return; 671 } 672 673 int 674 __vrc4173bcu_clock(vrcmu_chipset_tag_t cc, u_int16_t mask, int onoff) 675 { 676 struct vrc4173bcu_softc *sc = cc->cc_sc; 677 u_int16_t reg; 678 679 reg = bus_space_read_2(sc->sc_iot, sc->sc_cmuh, VRC4173CMU_CLKMSK); 680 #if 0 681 printf("cmu register(enter):"); 682 dbg_bit_print(reg); 683 #endif 684 if (onoff) 685 reg |= mask; 686 else 687 reg &= ~mask; 688 bus_space_write_2(sc->sc_iot, sc->sc_cmuh, VRC4173CMU_CLKMSK, reg); 689 #if 0 690 printf("cmu register(exit) :"); 691 dbg_bit_print(reg); 692 #endif 693 return (0); 694 } 695 696 void 697 __vrc4173bcu_register_cmu(vrip_chipset_tag_t vc, vrcmu_chipset_tag_t cmu) 698 { 699 vc->vc_cc = cmu; 700 } 701 702 void 703 __vrc4173bcu_register_gpio(vrip_chipset_tag_t vc, hpcio_chip_t chip) 704 { 705 /* XXX, not implemented yet */ 706 } 707 708 void 709 __vrc4173bcu_register_dmaau(vrip_chipset_tag_t vc, vrdmaau_chipset_tag_t dmaau) 710 { 711 712 vc->vc_ac = dmaau; 713 } 714 715 void 716 __vrc4173bcu_register_dcu(vrip_chipset_tag_t vc, vrdcu_chipset_tag_t dcu) 717 { 718 719 vc->vc_dc = dcu; 720 } 721
Indexes created Mon Oct 20 05:10:11 GMT 2025