vrcpudef.h revision 1.3
1 1.1 sato /*- 2 1.1 sato * Copyright (c) 2001 SATO Kazumi, All rights reserved. 3 1.1 sato * 4 1.1 sato * Redistribution and use in source and binary forms, with or without 5 1.1 sato * modification, are permitted provided that the following conditions 6 1.1 sato * are met: 7 1.1 sato * 1. Redistributions of source code must retain the above copyright 8 1.1 sato * notice, this list of conditions and the following disclaimer. 9 1.1 sato * 2. Redistributions in binary form must reproduce the above copyright 10 1.1 sato * notice, this list of conditions and the following disclaimer in the 11 1.1 sato * documentation and/or other materials provided with the distribution. 12 1.1 sato * 3. The name of the author may not be used to endorse or promote products 13 1.1 sato * derived from this software without specific prior written permission. 14 1.1 sato * 15 1.1 sato * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 16 1.1 sato * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 1.1 sato * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 1.1 sato * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 19 1.1 sato * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 1.1 sato * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 1.1 sato * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 1.1 sato * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 1.1 sato * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 1.1 sato * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 1.1 sato * SUCH DAMAGE. 26 1.1 sato * 27 1.1 sato */ 28 1.1 sato 29 1.1 sato /* 30 1.1 sato * definition for identify VR series cpu 31 1.3 sato * $NetBSD: vrcpudef.h,v 1.3 2001/09/07 16:02:56 sato Exp $ 32 1.1 sato * 33 1.1 sato * REQUIRE #include "opt_vr41xx.h" before using this header. 34 1.1 sato */ 35 1.1 sato #include "opt_vr41xx.h" 36 1.1 sato 37 1.1 sato /* 38 1.1 sato * VR cpu id 39 1.1 sato * It is related with BCU cpu id. 40 1.1 sato * KEEP consistency with bcureg.h 41 1.1 sato */ 42 1.1 sato #define VRID_4101 0x0 /* VR4101 */ 43 1.1 sato #define VRID_4102 0x1 /* VR4102 */ 44 1.1 sato #define VRID_4111 0x2 /* VR4111 */ 45 1.1 sato #define VRID_4121 0x3 /* VR4121 */ 46 1.1 sato #define VRID_4122 0x4 /* VR4122 */ 47 1.3 sato #define VRID_4131 0x5 /* VR4131 */ 48 1.1 sato /* conflict other cpu */ 49 1.1 sato #define VRID_4181 0x10 /* VR4181 conflict VR4101 */ 50 1.1 sato 51 1.1 sato /* 52 1.1 sato * VR cpu architecure group 53 1.1 sato * 54 1.1 sato * vr41xx group: all vr cpus (some registers are same) 55 1.1 sato * vr4181 group: vr4181 (vrip address and registers are same) 56 1.1 sato * vr4101 group: vr4101??? 57 1.1 sato * vr4102 group: vr4102, vr4111, vr4121, vr4122 (some resgiters are same) 58 1.1 sato * or vr4102, vr4111, vr4121 (vrip address and registers are same) 59 1.1 sato * vr4111 group: vr4111, vr4121, vr4122 (some registers are same) 60 1.1 sato * or vr4111, vr4121 (vrip address and registers are same) 61 1.3 sato * vr4122 group: vr4122, vr4131 (vrip address and registers are same) 62 1.1 sato * 63 1.1 sato * REQUIRE #include "opt_vr41xx.h" before using this definition. 64 1.1 sato */ 65 1.1 sato #if defined VR4181 66 1.1 sato #define VRGROUP_4181 VRID_4181 67 1.1 sato #endif /* defined VR4181 */ 68 1.3 sato 69 1.1 sato #if defined VR4101 70 1.1 sato #define VRGROUP_4101 VRID_4101 71 1.1 sato #endif /* defined VR4101 */ 72 1.1 sato 73 1.1 sato #if defined VR4102 74 1.1 sato #define VRGROUP_4102 VRID_4102 75 1.1 sato #define VRGROUP_4102_4121 VRID_4102 76 1.1 sato #define VRGROUP_4102_4122 VRID_4102 77 1.3 sato #define VRGROUP_4102_4131 VRID_4102 78 1.1 sato #endif /* defined VR4102 */ 79 1.1 sato 80 1.1 sato #if defined VR4111 81 1.1 sato #define VRGROUP_4111_4121 VRID_4111 82 1.1 sato #define VRGROUP_4111_4122 VRID_4111 83 1.3 sato #define VRGROUP_4111_4131 VRID_4111 84 1.1 sato 85 1.1 sato #ifndef VRGROUP_4102_4121 86 1.1 sato #define VRGROUP_4102_4121 VRID_4111 87 1.1 sato #endif /* VRGROUP_4102_4121 */ 88 1.1 sato 89 1.1 sato #ifndef VRGROUP_4102_4122 90 1.1 sato #define VRGROUP_4102_4122 VRID_4111 91 1.1 sato #endif /* VRGROUP_4102_4122 */ 92 1.1 sato 93 1.3 sato #ifndef VRGROUP_4102_4131 94 1.3 sato #define VRGROUP_4102_4131 VRID_4111 95 1.3 sato #endif /* VRGROUP_4102_4131 */ 96 1.3 sato 97 1.1 sato #endif /* defined VR4111 */ 98 1.1 sato 99 1.1 sato #if defined VR4121 100 1.3 sato #define VRGROUP_4121_4122 VRID_4121 101 1.3 sato #define VRGROUP_4121_4131 VRID_4131 102 1.3 sato 103 1.1 sato #ifndef VRGROUP_4111_4121 104 1.1 sato #define VRGROUP_4111_4121 VRID_4121 105 1.1 sato #endif /* VRGROUP_4111_4121 */ 106 1.1 sato 107 1.1 sato #ifndef VRGROUP_4111_4122 108 1.1 sato #define VRGROUP_4111_4122 VRID_4121 109 1.1 sato #endif /* VRGROUP_4111_4122 */ 110 1.1 sato 111 1.3 sato #ifndef VRGROUP_4111_4131 112 1.3 sato #define VRGROUP_4111_4131 VRID_4121 113 1.3 sato #endif /* VRGROUP_4111_4131 */ 114 1.3 sato 115 1.1 sato #ifndef VRGROUP_4102_4121 116 1.1 sato #define VRGROUP_4102_4121 VRID_4121 117 1.1 sato #endif /* VRGROUP_4102_4121 */ 118 1.1 sato 119 1.1 sato #ifndef VRGROUP_4102_4122 120 1.1 sato #define VRGROUP_4102_4122 VRID_4121 121 1.1 sato #endif /* VRGROUP_4102_4122 */ 122 1.1 sato 123 1.3 sato #ifndef VRGROUP_4102_4131 124 1.3 sato #define VRGROUP_4102_4131 VRID_4121 125 1.3 sato #endif /* VRGROUP_4102_4131 */ 126 1.3 sato 127 1.1 sato #endif /* VR4121 */ 128 1.1 sato 129 1.1 sato 130 1.1 sato #if defined VR4122 131 1.1 sato #define VRGROUP_4122 VRID_4122 132 1.1 sato 133 1.3 sato #ifndef VRGROUP_4122_4131 134 1.3 sato #define VRGROUP_4122_4131 VRID_4122 135 1.3 sato #endif /* VRGROUP_4122_4131 */ 136 1.3 sato 137 1.3 sato #ifndef VRGROUP_4111_4122 138 1.3 sato #define VRGROUP_4111_4122 VRID_4122 139 1.3 sato #endif /* VRGROUP_4111_4122 */ 140 1.3 sato 141 1.3 sato #ifndef VRGROUP_4111_4131 142 1.3 sato #define VRGROUP_4111_4131 VRID_4122 143 1.3 sato #endif /* VRGROUP_4111_4131 */ 144 1.3 sato 145 1.1 sato #ifndef VRGROUP_4102_4122 146 1.1 sato #define VRGROUP_4102_4122 VRID_4122 147 1.1 sato #endif /* VRGROUP_4102_4122 */ 148 1.1 sato 149 1.3 sato #ifndef VRGROUP_4102_4131 150 1.3 sato #define VRGROUP_4102_4131 VRID_4122 151 1.3 sato #endif /* VRGROUP_4102_4131 */ 152 1.1 sato 153 1.1 sato #endif /* VR4122 */ 154 1.1 sato 155 1.3 sato #if defined VR4131 156 1.3 sato #define VRGROUP_4131 VRID_4131 157 1.3 sato 158 1.3 sato #ifndef VRGROUP_4122_4131 159 1.3 sato #define VRGROUP_4122_4131 VRID_4131 160 1.3 sato #endif /* VRGROUP_4122_4131 */ 161 1.3 sato 162 1.3 sato #ifndef VRGROUP_4111_4131 163 1.3 sato #define VRGROUP_4111_4131 VRID_4131 164 1.3 sato #endif /* VRGROUP_4111_4131 */ 165 1.3 sato 166 1.3 sato #ifndef VRGROUP_4102_4131 167 1.3 sato #define VRGROUP_4102_4131 VRID_4131 168 1.3 sato #endif /* VRGROUP_4102_4131 */ 169 1.3 sato 170 1.3 sato #endif /* VR4131 */ 171 1.3 sato 172 1.1 sato /* 173 1.1 sato * identify one cpu only 174 1.1 sato */ 175 1.3 sato #if defined VR4181 && !defined VR4101 && !defined VRGROUP_4102_4131 176 1.1 sato #define ONLY_VR4181 VRID_4181 177 1.1 sato #endif /* ONLY_VR4181 */ 178 1.1 sato 179 1.3 sato #if !defined VR4181 && defined VR4101 && !defined VRGROUP_4102_4131 180 1.1 sato #define ONLY_VR4101 VRID_4101 181 1.1 sato #endif /* ONLY_VR4101 */ 182 1.1 sato 183 1.3 sato #if !defined VRGROUP_4181 && !defined VRGROUP_4101 && defined VR4102 && !defined VRGROUP_4111_4131 184 1.1 sato #define ONLY_VR4102 VRID_4102 185 1.1 sato #endif /* ONLY_VR4102 */ 186 1.1 sato 187 1.3 sato #if !defined VRGROUP_4181 && !defined VRGROUP_4101 && !defined VR4102 && defined VRGROUP_4111_4121 && !defined VRGROUP_4122_4131 188 1.1 sato #define ONLY_VR4111_4121 VRGROUP_4111_4121 189 1.1 sato #endif /* ONLY_VR4111_4121 */ 190 1.1 sato 191 1.3 sato #if !defined VRGROUP_4181 && !defined VRGROUP_4101 && !defined VRGROUP_4102_4121 && defined VR4122 && !defined VRGROUP_4131 192 1.1 sato #define ONLY_VR4122 VRID4122 193 1.1 sato #endif /* ONLY_VR4122 */ 194 1.1 sato 195 1.3 sato #if !defined VRGROUP_4181 && !defined VRGROUP_4101 && !defined VRGROUP_4102_4121 && !defined VRGROUP_4122 && defined VR4131 196 1.3 sato #define ONLY_VR4131 VRID4131 197 1.3 sato #endif /* ONLY_VR4131 */ 198 1.3 sato 199 1.3 sato #if !defined VRGROUP_4181 && !defined VRGROUP_4101 && !defined VRGROUP_4102_4121 && defined VRGROUP_VR4122_4131 200 1.3 sato #define ONLY_VR4122_4131 VRGROUP_4122_4131 201 1.3 sato #endif /* ONLY_VR4131 */ 202 1.3 sato 203 1.3 sato 204 1.3 sato 205 1.1 sato #if defined ONLY_VR4181 206 1.1 sato #define ONLY_VR_SPECIFIED ONLY_VR4181 207 1.1 sato #endif /* defined ONLY_VR4181 */ 208 1.1 sato 209 1.1 sato #if !defined ONLY_VR_SPECIFIED && defined ONLY_VR4101 210 1.1 sato #define ONLY_VR_SPECIFIED ONLY_VR4101 211 1.1 sato #endif /* defined ONLY_VR4101 */ 212 1.1 sato 213 1.1 sato #if !defined ONLY_VR_SPECIFIED && defined ONLY_VR4102 214 1.1 sato #define ONLY_VR_SPECIFIED ONLY_VR4102 215 1.1 sato #endif /* defined ONLY_VR4102 */ 216 1.1 sato 217 1.1 sato #if !defined ONLY_VR_SPECIFIED && defined ONLY_VR4111_4121 218 1.1 sato #define ONLY_VR_SPECIFIED ONLY_VR4111_4121 219 1.1 sato #endif /* defined ONLY_VR4111_4121 */ 220 1.1 sato 221 1.3 sato #if !defined ONLY_VR_SPECIFIED && defined ONLY_VR4122_4131 222 1.3 sato #define ONLY_VR_SPECIFIED ONLY_VR4122_4131 223 1.3 sato #endif /* ONLY_VR4122 */ 224 1.3 sato 225 1.1 sato #if !defined ONLY_VR_SPECIFIED && defined ONLY_VR4122 226 1.1 sato #define ONLY_VR_SPECIFIED ONLY_VR4122 227 1.1 sato #endif /* ONLY_VR4122 */ 228 1.1 sato 229 1.3 sato #if !defined ONLY_VR_SPECIFIED && defined ONLY_VR4131 230 1.3 sato #define ONLY_VR_SPECIFIED ONLY_VR4131 231 1.3 sato #endif /* ONLY_VR4131 */ 232 1.3 sato 233 1.1 sato /* 234 1.1 sato * identify single vrip base address 235 1.1 sato */ 236 1.1 sato #if defined ONLY_VR4181 237 1.1 sato #define SINGLE_VRIP_BASE ONLY_VR4181 238 1.1 sato #endif /* defined ONLY_VR4181 */ 239 1.1 sato 240 1.3 sato #if !defined VR4181 && defined VRGROUP_4102_4121 && !defined VRGROUP_4122_4131 241 1.3 sato #define SINGLE_VRIP_BASE VRGROUP_4102_4121 242 1.3 sato #endif 243 1.1 sato 244 1.3 sato #if !defined VR4181 && !defined VRGROUP_4102_4121 && defined VRGROUP_4122_4131 245 1.3 sato #define SINGLE_VRIP_BASE VRGROUP_4122_4131 246 1.1 sato #endif 247 1.1 sato 248 1.1 sato /* end */ 249
Indexes created Tue Sep 30 17:09:57 GMT 2025