vrcpudef.h revision 1.1
1 /*- 2 * Copyright (c) 2001 SATO Kazumi, All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 3. The name of the author may not be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29 /* 30 * definition for identify VR series cpu 31 * $NetBSD: vrcpudef.h,v 1.1 2001/04/17 11:13:16 sato Exp $ 32 * 33 * REQUIRE #include "opt_vr41xx.h" before using this header. 34 */ 35 #include "opt_vr41xx.h" 36 37 /* 38 * VR cpu id 39 * It is related with BCU cpu id. 40 * KEEP consistency with bcureg.h 41 */ 42 #define VRID_4101 0x0 /* VR4101 */ 43 #define VRID_4102 0x1 /* VR4102 */ 44 #define VRID_4111 0x2 /* VR4111 */ 45 #define VRID_4121 0x3 /* VR4121 */ 46 #define VRID_4122 0x4 /* VR4122 */ 47 /* conflict other cpu */ 48 #define VRID_4181 0x10 /* VR4181 conflict VR4101 */ 49 50 /* 51 * VR cpu architecure group 52 * 53 * vr41xx group: all vr cpus (some registers are same) 54 * vr4181 group: vr4181 (vrip address and registers are same) 55 * vr4101 group: vr4101??? 56 * vr4102 group: vr4102, vr4111, vr4121, vr4122 (some resgiters are same) 57 * or vr4102, vr4111, vr4121 (vrip address and registers are same) 58 * vr4111 group: vr4111, vr4121, vr4122 (some registers are same) 59 * or vr4111, vr4121 (vrip address and registers are same) 60 * vr4121 group: vr4121, (vr4131?) (vrip address and registers are same) 61 * 62 * REQUIRE #include "opt_vr41xx.h" before using this definition. 63 */ 64 #if defined VR4181 65 #define VRGROUP_4181 VRID_4181 66 #endif /* defined VR4181 */ 67 #if defined VR4101 68 #define VRGROUP_4101 VRID_4101 69 #endif /* defined VR4101 */ 70 71 #if defined VR4102 72 #define VRGROUP_4102 VRID_4102 73 #define VRGROUP_4102_4121 VRID_4102 74 #define VRGROUP_4102_4122 VRID_4102 75 #endif /* defined VR4102 */ 76 77 #if defined VR4111 78 #define VRGROUP_4111_4121 VRID_4111 79 #define VRGROUP_4111_4122 VRID_4111 80 81 #ifndef VRGROUP_4102_4121 82 #define VRGROUP_4102_4121 VRID_4111 83 #endif /* VRGROUP_4102_4121 */ 84 85 #ifndef VRGROUP_4102_4122 86 #define VRGROUP_4102_4122 VRID_4111 87 #endif /* VRGROUP_4102_4122 */ 88 89 #endif /* defined VR4111 */ 90 91 #if defined VR4121 92 #ifndef VRGROUP_4111_4121 93 #define VRGROUP_4111_4121 VRID_4121 94 #endif /* VRGROUP_4111_4121 */ 95 96 #ifndef VRGROUP_4111_4122 97 #define VRGROUP_4111_4122 VRID_4121 98 #endif /* VRGROUP_4111_4122 */ 99 100 #ifndef VRGROUP_4102_4121 101 #define VRGROUP_4102_4121 VRID_4121 102 #endif /* VRGROUP_4102_4121 */ 103 104 #ifndef VRGROUP_4102_4122 105 #define VRGROUP_4102_4122 VRID_4121 106 #endif /* VRGROUP_4102_4122 */ 107 108 #endif /* VR4121 */ 109 110 111 #if defined VR4122 112 #define VRGROUP_4122 VRID_4122 113 114 #ifndef VRGROUP_4102_4122 115 #define VRGROUP_4102_4122 VRID_4122 116 #endif /* VRGROUP_4102_4122 */ 117 118 #ifndef VRGROUP_4111_4122 119 #define VRGROUP_4111_4122 VRID_4122 120 #endif /* VRGROUP_4111_4122 */ 121 122 #endif /* VR4122 */ 123 124 /* 125 * identify one cpu only 126 */ 127 #if defined VR4181 && !defined VR4101 && !defined VRGROUP_4102_4122 128 #define ONLY_VR4181 VRID_4181 129 #endif /* ONLY_VR4181 */ 130 131 #if !defined VR4181 && defined VR4101 && !defined VRGROUP_4102_4122 132 #define ONLY_VR4101 VRID_4101 133 #endif /* ONLY_VR4101 */ 134 135 #if !defined VRGROUP_4181 && !defined VRGROUP_4101 && defined VR4102 && !defined VRGROUP_4111_4122 136 #define ONLY_VR4102 VRID_4102 137 #endif /* ONLY_VR4102 */ 138 139 #if !defined VRGROUP_4181 && !defined VRGROUP_4101 && !defined VR4102 && defined VRGROUP_4111_4121 && !defined VR4122 140 #define ONLY_VR4111_4121 VRGROUP_4111_4121 141 #endif /* ONLY_VR4111_4121 */ 142 143 #if !defined VRGROUP_4181 && !defined VRGROUP_4101 && !defined VRGROUP_4102_4121 && defined VR4122 144 #define ONLY_VR4122 VRID4122 145 #endif /* ONLY_VR4122 */ 146 147 #if defined ONLY_VR4181 148 #define ONLY_VR_SPECIFIED ONLY_VR4181 149 #endif /* defined ONLY_VR4181 */ 150 151 #if !defined ONLY_VR_SPECIFIED && defined ONLY_VR4101 152 #define ONLY_VR_SPECIFIED ONLY_VR4101 153 #endif /* defined ONLY_VR4101 */ 154 155 #if !defined ONLY_VR_SPECIFIED && defined ONLY_VR4102 156 #define ONLY_VR_SPECIFIED ONLY_VR4102 157 #endif /* defined ONLY_VR4102 */ 158 159 #if !defined ONLY_VR_SPECIFIED && defined ONLY_VR4111_4121 160 #define ONLY_VR_SPECIFIED ONLY_VR4111_4121 161 #endif /* defined ONLY_VR4111_4121 */ 162 163 #if !defined ONLY_VR_SPECIFIED && defined ONLY_VR4122 164 #define ONLY_VR_SPECIFIED ONLY_VR4122 165 #endif /* ONLY_VR4122 */ 166 167 /* 168 * identify single vrip base address 169 */ 170 #if defined ONLY_VR4181 171 #define SINGLE_VRIP_BASE ONLY_VR4181 172 #endif /* defined ONLY_VR4181 */ 173 174 #if defined ONLY_VR4122 175 #define SINGLE_VRIP_BASE ONLY_VR4122 176 #endif /* defined ONLY_VR4122 */ 177 178 #if !defined SINGLE_VRIP_BASE && defined VRGROUP_4102_4121 179 #define SINGLE_VRIP_BASE VRGROUP_4102_4121 180 #endif 181 182 /* end */ 183
Indexes created Wed Oct 01 07:09:59 GMT 2025