vrdcu.c revision 1.1.2.2
1 1.1.2.2 nathanw /* 2 1.1.2.2 nathanw * Copyright (c) 2001 HAMAJIMA Katsuomi. All rights reserved. 3 1.1.2.2 nathanw * 4 1.1.2.2 nathanw * Redistribution and use in source and binary forms, with or without 5 1.1.2.2 nathanw * modification, are permitted provided that the following conditions 6 1.1.2.2 nathanw * are met: 7 1.1.2.2 nathanw * 1. Redistributions of source code must retain the above copyright 8 1.1.2.2 nathanw * notice, this list of conditions and the following disclaimer. 9 1.1.2.2 nathanw * 2. Redistributions in binary form must reproduce the above copyright 10 1.1.2.2 nathanw * notice, this list of conditions and the following disclaimer in the 11 1.1.2.2 nathanw * documentation and/or other materials provided with the distribution. 12 1.1.2.2 nathanw * 13 1.1.2.2 nathanw * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 1.1.2.2 nathanw * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 1.1.2.2 nathanw * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 1.1.2.2 nathanw * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 1.1.2.2 nathanw * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 1.1.2.2 nathanw * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 1.1.2.2 nathanw * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 1.1.2.2 nathanw * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 1.1.2.2 nathanw * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 1.1.2.2 nathanw * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 1.1.2.2 nathanw * SUCH DAMAGE. 24 1.1.2.2 nathanw */ 25 1.1.2.2 nathanw 26 1.1.2.2 nathanw #include <sys/param.h> 27 1.1.2.2 nathanw #include <sys/systm.h> 28 1.1.2.2 nathanw #include <sys/device.h> 29 1.1.2.2 nathanw 30 1.1.2.2 nathanw #include <uvm/uvm_extern.h> 31 1.1.2.2 nathanw 32 1.1.2.2 nathanw #include <machine/cpu.h> 33 1.1.2.2 nathanw #include <machine/bus.h> 34 1.1.2.2 nathanw #include <machine/bus_dma_hpcmips.h> 35 1.1.2.2 nathanw 36 1.1.2.2 nathanw #include <hpcmips/vr/vripif.h> 37 1.1.2.2 nathanw #include <hpcmips/vr/dcureg.h> 38 1.1.2.2 nathanw 39 1.1.2.2 nathanw #ifdef VRDCU_DEBUG 40 1.1.2.2 nathanw int vrdcu_debug = VRDCU_DEBUG; 41 1.1.2.2 nathanw #define DPRINTFN(n,x) if (vrdcu_debug>(n)) printf x; 42 1.1.2.2 nathanw #else 43 1.1.2.2 nathanw #define DPRINTFN(n,x) 44 1.1.2.2 nathanw #endif 45 1.1.2.2 nathanw 46 1.1.2.2 nathanw struct vrdcu_softc { 47 1.1.2.2 nathanw struct device sc_dev; 48 1.1.2.2 nathanw bus_space_tag_t sc_iot; 49 1.1.2.2 nathanw bus_space_handle_t sc_ioh; 50 1.1.2.2 nathanw struct vrdcu_chipset_tag sc_chipset; 51 1.1.2.2 nathanw int sc_status; /* DMA status */ 52 1.1.2.2 nathanw }; 53 1.1.2.2 nathanw 54 1.1.2.2 nathanw int vrdcu_match(struct device *, struct cfdata *, void *); 55 1.1.2.2 nathanw void vrdcu_attach(struct device *, struct device *, void *); 56 1.1.2.2 nathanw 57 1.1.2.2 nathanw struct cfattach vrdcu_ca = { 58 1.1.2.2 nathanw sizeof(struct vrdcu_softc), vrdcu_match, vrdcu_attach 59 1.1.2.2 nathanw }; 60 1.1.2.2 nathanw 61 1.1.2.2 nathanw int vrdcu_enable_aiuin(vrdcu_chipset_tag_t); 62 1.1.2.2 nathanw int vrdcu_enable_aiuout(vrdcu_chipset_tag_t); 63 1.1.2.2 nathanw int vrdcu_enable_fir(vrdcu_chipset_tag_t); 64 1.1.2.2 nathanw void vrdcu_disable(vrdcu_chipset_tag_t); 65 1.1.2.2 nathanw void vrdcu_fir_direction(vrdcu_chipset_tag_t, int); 66 1.1.2.2 nathanw int _vrdcu_dmamem_alloc(bus_dma_tag_t, bus_size_t, bus_size_t, 67 1.1.2.2 nathanw bus_size_t, bus_dma_segment_t *, int, int *, int); 68 1.1.2.2 nathanw 69 1.1.2.2 nathanw struct bus_dma_tag vrdcu_bus_dma_tag = { 70 1.1.2.2 nathanw NULL, 71 1.1.2.2 nathanw { 72 1.1.2.2 nathanw _hpcmips_bd_map_create, 73 1.1.2.2 nathanw _hpcmips_bd_map_destroy, 74 1.1.2.2 nathanw _hpcmips_bd_map_load, 75 1.1.2.2 nathanw _hpcmips_bd_map_load_mbuf, 76 1.1.2.2 nathanw _hpcmips_bd_map_load_uio, 77 1.1.2.2 nathanw _hpcmips_bd_map_load_raw, 78 1.1.2.2 nathanw _hpcmips_bd_map_unload, 79 1.1.2.2 nathanw _hpcmips_bd_map_sync, 80 1.1.2.2 nathanw _vrdcu_dmamem_alloc, 81 1.1.2.2 nathanw _hpcmips_bd_mem_free, 82 1.1.2.2 nathanw _hpcmips_bd_mem_map, 83 1.1.2.2 nathanw _hpcmips_bd_mem_unmap, 84 1.1.2.2 nathanw _hpcmips_bd_mem_mmap, 85 1.1.2.2 nathanw }, 86 1.1.2.2 nathanw }; 87 1.1.2.2 nathanw 88 1.1.2.2 nathanw int 89 1.1.2.2 nathanw vrdcu_match(struct device *parent, struct cfdata *cf, void *aux) 90 1.1.2.2 nathanw { 91 1.1.2.2 nathanw return 2; /* 1st attach group of vrip */ 92 1.1.2.2 nathanw } 93 1.1.2.2 nathanw 94 1.1.2.2 nathanw void 95 1.1.2.2 nathanw vrdcu_attach(struct device *parent, struct device *self, void *aux) 96 1.1.2.2 nathanw { 97 1.1.2.2 nathanw struct vrip_attach_args *va = aux; 98 1.1.2.2 nathanw struct vrdcu_softc *sc = (void*)self; 99 1.1.2.2 nathanw 100 1.1.2.2 nathanw sc->sc_iot = va->va_iot; 101 1.1.2.2 nathanw sc->sc_chipset.dc_sc = sc; 102 1.1.2.2 nathanw sc->sc_chipset.dc_enable_aiuin = vrdcu_enable_aiuin; 103 1.1.2.2 nathanw sc->sc_chipset.dc_enable_aiuout = vrdcu_enable_aiuout; 104 1.1.2.2 nathanw sc->sc_chipset.dc_enable_fir = vrdcu_enable_fir; 105 1.1.2.2 nathanw sc->sc_chipset.dc_disable = vrdcu_disable; 106 1.1.2.2 nathanw sc->sc_chipset.dc_fir_direction = vrdcu_fir_direction; 107 1.1.2.2 nathanw 108 1.1.2.2 nathanw if (bus_space_map(sc->sc_iot, va->va_addr, va->va_size, 109 1.1.2.2 nathanw 0 /* no flags */, &sc->sc_ioh)) { 110 1.1.2.2 nathanw printf("%s: can't map i/o space\n", sc->sc_dev.dv_xname); 111 1.1.2.2 nathanw return; 112 1.1.2.2 nathanw } 113 1.1.2.2 nathanw printf("\n"); 114 1.1.2.2 nathanw vrip_register_dcu(va->va_vc, &sc->sc_chipset); 115 1.1.2.2 nathanw 116 1.1.2.2 nathanw sc->sc_status = DMASDS; 117 1.1.2.2 nathanw /* reset DCU */ 118 1.1.2.2 nathanw bus_space_write_2(sc->sc_iot, sc->sc_ioh, DMARST_REG_W, DMARST); 119 1.1.2.2 nathanw } 120 1.1.2.2 nathanw 121 1.1.2.2 nathanw int 122 1.1.2.2 nathanw vrdcu_enable_aiuin(vrdcu_chipset_tag_t dc) 123 1.1.2.2 nathanw { 124 1.1.2.2 nathanw struct vrdcu_softc *sc = dc->dc_sc; 125 1.1.2.2 nathanw int mask; 126 1.1.2.2 nathanw 127 1.1.2.2 nathanw DPRINTFN(1, ("vrdcu_enable_aiuin\n")); 128 1.1.2.2 nathanw 129 1.1.2.2 nathanw if (sc->sc_status){ 130 1.1.2.2 nathanw mask = bus_space_read_2(sc->sc_iot, sc->sc_ioh, DMAMSK_REG_W); 131 1.1.2.2 nathanw if (mask & DMAMSKAIN) { 132 1.1.2.2 nathanw DPRINTFN(0, ("vrdcu_enable_aiuin: already enabled\n")); 133 1.1.2.2 nathanw return 0; 134 1.1.2.2 nathanw } else { 135 1.1.2.2 nathanw DPRINTFN(0, ("vrdcu_enable_aiuin: device busy\n")); 136 1.1.2.2 nathanw return EBUSY; 137 1.1.2.2 nathanw } 138 1.1.2.2 nathanw } 139 1.1.2.2 nathanw sc->sc_status = DMASEN; 140 1.1.2.2 nathanw bus_space_write_2(sc->sc_iot, sc->sc_ioh, DMAMSK_REG_W, DMAMSKAIN); 141 1.1.2.2 nathanw bus_space_write_2(sc->sc_iot, sc->sc_ioh, DMASEN_REG_W, sc->sc_status); 142 1.1.2.2 nathanw return 0; 143 1.1.2.2 nathanw } 144 1.1.2.2 nathanw 145 1.1.2.2 nathanw int 146 1.1.2.2 nathanw vrdcu_enable_aiuout(vrdcu_chipset_tag_t dc) 147 1.1.2.2 nathanw { 148 1.1.2.2 nathanw struct vrdcu_softc *sc = dc->dc_sc; 149 1.1.2.2 nathanw int mask; 150 1.1.2.2 nathanw 151 1.1.2.2 nathanw DPRINTFN(1, ("vrdcu_enable_aiuout\n")); 152 1.1.2.2 nathanw 153 1.1.2.2 nathanw if (sc->sc_status){ 154 1.1.2.2 nathanw mask = bus_space_read_2(sc->sc_iot, sc->sc_ioh, DMAMSK_REG_W); 155 1.1.2.2 nathanw if (mask & DMAMSKAOUT) { 156 1.1.2.2 nathanw DPRINTFN(0, ("vrdcu_enable_aiuout: already enabled\n")); 157 1.1.2.2 nathanw return 0; 158 1.1.2.2 nathanw } else { 159 1.1.2.2 nathanw DPRINTFN(0, ("vrdcu_enable_aiuout: device busy\n")); 160 1.1.2.2 nathanw return EBUSY; 161 1.1.2.2 nathanw } 162 1.1.2.2 nathanw } 163 1.1.2.2 nathanw sc->sc_status = DMASEN; 164 1.1.2.2 nathanw bus_space_write_2(sc->sc_iot, sc->sc_ioh, DMAMSK_REG_W, DMAMSKAOUT); 165 1.1.2.2 nathanw bus_space_write_2(sc->sc_iot, sc->sc_ioh, DMASEN_REG_W, sc->sc_status); 166 1.1.2.2 nathanw return 0; 167 1.1.2.2 nathanw } 168 1.1.2.2 nathanw 169 1.1.2.2 nathanw int 170 1.1.2.2 nathanw vrdcu_enable_fir(vrdcu_chipset_tag_t dc) 171 1.1.2.2 nathanw { 172 1.1.2.2 nathanw struct vrdcu_softc *sc = dc->dc_sc; 173 1.1.2.2 nathanw int mask; 174 1.1.2.2 nathanw 175 1.1.2.2 nathanw DPRINTFN(1, ("vrdcu_enable_fir\n")); 176 1.1.2.2 nathanw 177 1.1.2.2 nathanw if (sc->sc_status){ 178 1.1.2.2 nathanw mask = bus_space_read_2(sc->sc_iot, sc->sc_ioh, DMAMSK_REG_W); 179 1.1.2.2 nathanw if (mask & DMAMSKFOUT) { 180 1.1.2.2 nathanw DPRINTFN(0, ("vrdcu_enable_fir: already enabled\n")); 181 1.1.2.2 nathanw return 0; 182 1.1.2.2 nathanw } else { 183 1.1.2.2 nathanw DPRINTFN(0, ("vrdcu_enable_fir: device busy\n")); 184 1.1.2.2 nathanw return EBUSY; 185 1.1.2.2 nathanw } 186 1.1.2.2 nathanw } 187 1.1.2.2 nathanw sc->sc_status = DMASEN; 188 1.1.2.2 nathanw bus_space_write_2(sc->sc_iot, sc->sc_ioh, DMAMSK_REG_W, DMAMSKFOUT); 189 1.1.2.2 nathanw bus_space_write_2(sc->sc_iot, sc->sc_ioh, DMASEN_REG_W, sc->sc_status); 190 1.1.2.2 nathanw return 0; 191 1.1.2.2 nathanw } 192 1.1.2.2 nathanw 193 1.1.2.2 nathanw void 194 1.1.2.2 nathanw vrdcu_disable(vrdcu_chipset_tag_t dc) 195 1.1.2.2 nathanw { 196 1.1.2.2 nathanw struct vrdcu_softc *sc = dc->dc_sc; 197 1.1.2.2 nathanw 198 1.1.2.2 nathanw DPRINTFN(1, ("vrdcu_disable\n")); 199 1.1.2.2 nathanw 200 1.1.2.2 nathanw sc->sc_status = DMASDS; 201 1.1.2.2 nathanw bus_space_write_2(sc->sc_iot, sc->sc_ioh, DMASEN_REG_W, sc->sc_status); 202 1.1.2.2 nathanw } 203 1.1.2.2 nathanw 204 1.1.2.2 nathanw void 205 1.1.2.2 nathanw vrdcu_fir_direction(vrdcu_chipset_tag_t dc, int dir) 206 1.1.2.2 nathanw { 207 1.1.2.2 nathanw struct vrdcu_softc *sc = dc->dc_sc; 208 1.1.2.2 nathanw 209 1.1.2.2 nathanw DPRINTFN(1, ("vrdcu_fir_direction: dir %d\n", dir)); 210 1.1.2.2 nathanw 211 1.1.2.2 nathanw bus_space_write_2(sc->sc_iot, sc->sc_ioh, 212 1.1.2.2 nathanw DMATD_REG_W, dir & DMATDMASK); 213 1.1.2.2 nathanw } 214 1.1.2.2 nathanw 215 1.1.2.2 nathanw int 216 1.1.2.2 nathanw _vrdcu_dmamem_alloc(bus_dma_tag_t t, bus_size_t size, bus_size_t alignment, 217 1.1.2.2 nathanw bus_size_t boundary, bus_dma_segment_t *segs, 218 1.1.2.2 nathanw int nsegs, int *rsegs, int flags) 219 1.1.2.2 nathanw { 220 1.1.2.2 nathanw extern paddr_t avail_start, avail_end; /* XXX */ 221 1.1.2.2 nathanw paddr_t high; 222 1.1.2.2 nathanw 223 1.1.2.2 nathanw DPRINTFN(1, ("_vrdcu_dmamem_alloc\n")); 224 1.1.2.2 nathanw 225 1.1.2.2 nathanw high = (avail_end < VRDMAAU_BOUNCE_THRESHOLD ? 226 1.1.2.2 nathanw avail_end : VRDMAAU_BOUNCE_THRESHOLD) - PAGE_SIZE; 227 1.1.2.2 nathanw alignment = alignment > VRDMAAU_ALIGNMENT ? 228 1.1.2.2 nathanw alignment : VRDMAAU_ALIGNMENT; 229 1.1.2.2 nathanw 230 1.1.2.2 nathanw return _hpcmips_bd_mem_alloc_range(t, size, alignment, boundary, 231 1.1.2.2 nathanw segs, nsegs, rsegs, flags, 232 1.1.2.2 nathanw avail_start, high); 233 1.1.2.2 nathanw } 234
Indexes created Thu Oct 23 22:10:10 GMT 2025