vrgiu.c revision 1.12
1 /* $NetBSD: vrgiu.c,v 1.12 2000/09/24 12:32:35 jdolecek Exp $ */ 2 /*- 3 * Copyright (c) 1999 4 * Shin Takemura and PocketBSD Project. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by the PocketBSD project 17 * and its contributors. 18 * 4. Neither the name of the project nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/device.h> 39 #include <sys/malloc.h> 40 #include <sys/queue.h> 41 #define TAILQ_EMPTY(head) ((head)->tqh_first == NULL) 42 43 #include <mips/cpuregs.h> 44 #include <machine/bus.h> 45 46 #include <hpcmips/vr/vripreg.h> 47 #include <hpcmips/vr/vripvar.h> 48 #include <hpcmips/vr/vrgiureg.h> 49 50 #include "locators.h" 51 52 #define VRGIUDEBUG 53 #ifdef VRGIUDEBUG 54 #define DEBUG_IO 1 55 #define DEBUG_INTR 2 56 #ifndef VRGIUDEBUG_CONF 57 #define VRGIUDEBUG_CONF 0 58 #endif /* VRGIUDEBUG_CONF */ 59 int vrgiu_debug = VRGIUDEBUG_CONF; 60 #define DPRINTF(flag, arg) if (vrgiu_debug & flag) printf arg; 61 #define DDUMP_IO(flag, sc) if (vrgiu_debug & flag) vrgiu_dump_io(sc); 62 #define DDUMP_IOSETTING(flag, sc) \ 63 if (vrgiu_debug & flag) vrgiu_dump_iosetting(sc); 64 #define VPRINTF(flag, arg) \ 65 if (bootverbose || vrgiu_debug & flag) printf arg; 66 #define VDUMP_IO(flag, sc) \ 67 if (bootverbose || vrgiu_debug & flag) vrgiu_dump_io(sc); 68 #define VDUMP_IOSETTING(flag, sc) \ 69 if (bootverbose || vrgiu_debug & flag) vrgiu_dump_iosetting(sc); 70 #else 71 #define DPRINTF(flag, arg) 72 #define DDUMP_IO(flag, sc) 73 #define DDUMP_IOSETTING(flag, sc) 74 #define VPRINTF(flag, arg) if (bootverbose) printf arg; 75 #define VDUMP_IO(flag, sc) if (bootverbose) vrgiu_dump_io(sc); 76 #define VDUMP_IOSETTING(flag, sc) \ 77 if (bootverbose) vrgiu_dump_iosetting(sc); 78 #endif 79 80 #define LEGAL_INTR_PORT(x) ((x) >= 0 && (x) < MAX_GPIO_INOUT) 81 #define LEGAL_OUT_PORT(x) ((x) >= 0 && (x) < MAX_GPIO_OUT) 82 83 int vrgiu_match __P((struct device*, struct cfdata*, void*)); 84 void vrgiu_attach __P((struct device*, struct device*, void*)); 85 int vrgiu_intr __P((void*)); 86 int vrgiu_print __P((void*, const char*)); 87 void vrgiu_callback __P((struct device*)); 88 89 void vrgiu_dump_regs(struct vrgiu_softc *sc); 90 void vrgiu_dump_io(struct vrgiu_softc *sc); 91 void vrgiu_dump_iosetting(struct vrgiu_softc *sc); 92 u_int32_t vrgiu_regread_4 __P((vrgiu_chipset_tag_t, bus_addr_t)); 93 u_int16_t vrgiu_regread __P((vrgiu_chipset_tag_t, bus_addr_t)); 94 void vrgiu_regwrite_4 __P((vrgiu_chipset_tag_t, bus_addr_t, u_int32_t)); 95 void vrgiu_regwrite __P((vrgiu_chipset_tag_t, bus_addr_t, u_int16_t)); 96 97 int vrgiu_port_read __P((vrgiu_chipset_tag_t, int)); 98 int vrgiu_port_write __P((vrgiu_chipset_tag_t, int, int)); 99 100 void *vrgiu_intr_establish __P((vrgiu_chipset_tag_t, int, int, int, int (*)(void *), void*)); 101 void vrgiu_intr_disestablish __P((vrgiu_chipset_tag_t, void*)); 102 103 struct vrgiu_function_tag vrgiu_functions = { 104 vrgiu_port_read, 105 vrgiu_port_write, 106 vrgiu_regread_4, 107 vrgiu_regwrite_4, 108 vrgiu_intr_establish, 109 vrgiu_intr_disestablish 110 }; 111 112 struct cfattach vrgiu_ca = { 113 sizeof(struct vrgiu_softc), vrgiu_match, vrgiu_attach 114 }; 115 116 int 117 vrgiu_match(parent, cf, aux) 118 struct device *parent; 119 struct cfdata *cf; 120 void *aux; 121 { 122 return 2; /* 1st attach group of vrip */ 123 } 124 125 void 126 vrgiu_attach(parent, self, aux) 127 struct device *parent; 128 struct device *self; 129 void *aux; 130 { 131 struct vrip_attach_args *va = aux; 132 struct vrgiu_softc *sc = (void*)self; 133 struct gpbus_attach_args gpa; 134 int i; 135 136 sc->sc_vc = va->va_vc; 137 sc->sc_iot = va->va_iot; 138 bus_space_map(sc->sc_iot, va->va_addr, va->va_size, 139 0 /* no cache */, &sc->sc_ioh); 140 /* 141 * Disable all interrupts. 142 */ 143 sc->sc_intr_mask = 0; 144 printf("\n"); 145 #ifdef WINCE_DEFAULT_SETTING 146 #warning WINCE_DEFAULT_SETTING 147 #else 148 VPRINTF(DEBUG_IO, ("WIN setting: ")); 149 VDUMP_IOSETTING(DEBUG_IO, sc); 150 VPRINTF(DEBUG_IO, ("\n")); 151 vrgiu_regwrite_4(sc, GIUINTEN_REG, sc->sc_intr_mask); 152 #endif 153 154 for (i = 0; i < MAX_GPIO_INOUT; i++) 155 TAILQ_INIT(&sc->sc_intr_head[i]); 156 if (!(sc->sc_ih = vrip_intr_establish(va->va_vc, va->va_intr, IPL_BIO, 157 vrgiu_intr, sc))) { 158 printf("%s: can't establish interrupt\n", sc->sc_dev.dv_xname); 159 return; 160 } 161 vrgiu_functions.gf_intr_establish = vrgiu_intr_establish; 162 vrgiu_functions.gf_intr_disestablish = vrgiu_intr_disestablish; 163 /* 164 * Register functions to upper interface. 165 */ 166 vrip_giu_function_register(va->va_vc, &vrgiu_functions, self); 167 168 /* Display port status (Input/Output) for debugging */ 169 VPRINTF(DEBUG_IO, ("I/O setting: ")); 170 DDUMP_IOSETTING(DEBUG_IO, sc); 171 VPRINTF(DEBUG_IO, ("\n")); 172 VPRINTF(DEBUG_IO, (" data:")); 173 VDUMP_IO(DEBUG_IO, sc); 174 175 /* 176 * General purpose bus 177 */ 178 gpa.gpa_busname = "gpbus"; 179 gpa.gpa_gc = sc; 180 gpa.gpa_gf = &vrgiu_functions; 181 while (config_found(self, &gpa, vrgiu_print)) ; 182 /* 183 * GIU-ISA bridge 184 */ 185 #if 1 /* XXX Sometimes mounting root device failed. Why? XXX*/ 186 config_defer(self, vrgiu_callback); 187 #else 188 vrgiu_callback(self); 189 #endif 190 } 191 192 void 193 vrgiu_callback(self) 194 struct device *self; 195 { 196 struct vrgiu_softc *sc = (void*)self; 197 struct gpbus_attach_args gpa; 198 199 gpa.gpa_busname = "vrisab"; 200 gpa.gpa_gc = sc; 201 gpa.gpa_gf = &vrgiu_functions; 202 config_found(self, &gpa, vrgiu_print); 203 } 204 205 int 206 vrgiu_print(aux, pnp) 207 void *aux; 208 const char *pnp; 209 { 210 if (pnp) 211 return (QUIET); 212 return (UNCONF); 213 } 214 215 void 216 vrgiu_dump_iosetting(sc) 217 struct vrgiu_softc *sc; 218 { 219 long iosel, inten, useupdn, termupdn; 220 u_int32_t m; 221 iosel= vrgiu_regread_4(sc, GIUIOSEL_REG); 222 inten= vrgiu_regread_4(sc, GIUINTEN_REG); 223 useupdn = vrgiu_regread(sc, GIUUSEUPDN_REG_W); 224 termupdn = vrgiu_regread(sc, GIUTERMUPDN_REG_W); 225 for (m = 0x80000000; m; m >>=1) 226 printf ("%c" , (useupdn&m) ? 227 ((termupdn&m) ? 'U' : 'D') : 228 ((iosel&m) ? 'o' : ((inten&m)?'I':'i'))); 229 } 230 231 void 232 vrgiu_dump_io(sc) 233 struct vrgiu_softc *sc; 234 { 235 u_int32_t preg[2]; 236 237 preg[0] = vrgiu_regread_4(sc, GIUPIOD_REG); 238 preg[1] = vrgiu_regread_4(sc, GIUPODAT_REG); 239 240 bitdisp64(preg); 241 } 242 243 void 244 vrgiu_dump_regs(sc) 245 struct vrgiu_softc *sc; 246 { 247 if (sc == NULL) { 248 panic("%s(%d): VRGIU device not initialized\n", 249 __FILE__, __LINE__); 250 } 251 printf(" IOSEL: %08x\n", vrgiu_regread_4(sc, GIUIOSEL_REG)); 252 printf(" PIOD: %08x\n", vrgiu_regread_4(sc, GIUPIOD_REG)); 253 printf(" PODAT: %08x\n", vrgiu_regread_4(sc, GIUPODAT_REG)); 254 printf(" INTSTAT: %08x\n", vrgiu_regread_4(sc, GIUINTSTAT_REG)); 255 printf(" INTEN: %08x\n", vrgiu_regread_4(sc, GIUINTEN_REG)); 256 printf(" INTTYP: %08x\n", vrgiu_regread_4(sc, GIUINTTYP_REG)); 257 printf(" INTALSEL: %08x\n", vrgiu_regread_4(sc, GIUINTALSEL_REG)); 258 printf(" INTHTSEL: %08x\n", vrgiu_regread_4(sc, GIUINTHTSEL_REG)); 259 } 260 /* 261 * GIU regster access method. 262 */ 263 u_int32_t 264 vrgiu_regread_4(vc, offs) 265 vrgiu_chipset_tag_t vc; 266 bus_addr_t offs; 267 { 268 struct vrgiu_softc *sc = (void*)vc; 269 u_int16_t reg[2]; 270 bus_space_read_region_2 (sc->sc_iot, sc->sc_ioh, offs, reg, 2); 271 return reg[0]|(reg[1]<<16); 272 } 273 274 u_int16_t 275 vrgiu_regread(vc, off) 276 vrgiu_chipset_tag_t vc; 277 bus_addr_t off; 278 { 279 struct vrgiu_softc *sc = (void*)vc; 280 return bus_space_read_2(sc->sc_iot, sc->sc_ioh, off); 281 } 282 283 void 284 vrgiu_regwrite_4(vc, offs, data) 285 vrgiu_chipset_tag_t vc; 286 bus_addr_t offs; 287 u_int32_t data; 288 { 289 struct vrgiu_softc *sc = (void*)vc; 290 291 u_int16_t reg[2]; 292 reg[0] = data & 0xffff; 293 reg[1] = (data>>16)&0xffff; 294 bus_space_write_region_2 (sc->sc_iot, sc->sc_ioh, offs, reg, 2); 295 } 296 297 void 298 vrgiu_regwrite(vc, off, data) 299 vrgiu_chipset_tag_t vc; 300 bus_addr_t off; 301 u_int16_t data; 302 { 303 struct vrgiu_softc *sc = (void*)vc; 304 bus_space_write_2(sc->sc_iot, sc->sc_ioh, off, data); 305 } 306 307 /* 308 * PORT 309 */ 310 int 311 vrgiu_port_read(vc, port) 312 vrgiu_chipset_tag_t vc; 313 int port; 314 { 315 int on; 316 317 if (!LEGAL_OUT_PORT(port)) 318 panic("vrgiu_port_read: illegal gpio port"); 319 320 if (port < 32) 321 on = (vrgiu_regread_4(vc, GIUPIOD_REG) & (1 << port)); 322 else 323 on = (vrgiu_regread_4(vc, GIUPODAT_REG) & (1 << (port - 32))); 324 325 return (on ? 1 : 0); 326 } 327 328 int 329 vrgiu_port_write(vc, port, onoff) 330 vrgiu_chipset_tag_t vc; 331 int port; 332 int onoff; 333 { 334 u_int32_t reg[2]; 335 int bank; 336 337 if (!LEGAL_OUT_PORT(port)) 338 panic("vrgiu_port_write: illegal gpio port"); 339 340 reg[0] = vrgiu_regread_4(vc, GIUPIOD_REG); 341 reg[1] = vrgiu_regread_4(vc, GIUPODAT_REG); 342 bank = port < 32 ? 0 : 1; 343 if (bank == 1) 344 port -= 32; 345 346 if (onoff) 347 reg[bank] |= (1<<port); 348 else 349 reg[bank] &= ~(1<<port); 350 vrgiu_regwrite_4(vc, GIUPIOD_REG, reg[0]); 351 vrgiu_regwrite_4(vc, GIUPODAT_REG, reg[1]); 352 353 return 0; 354 } 355 /* 356 * For before autoconfiguration. 357 */ 358 void 359 __vrgiu_out(port, data) 360 int port; 361 int data; 362 { 363 u_int16_t reg; 364 u_int32_t addr; 365 int offs; 366 367 if (!LEGAL_OUT_PORT(port)) 368 panic("__vrgiu_out: illegal gpio port"); 369 if (port < 16) { 370 addr = MIPS_PHYS_TO_KSEG1((VRIP_GIU_ADDR + GIUPIOD_L_REG_W)); 371 offs = port; 372 } else if (port < 32) { 373 addr = MIPS_PHYS_TO_KSEG1((VRIP_GIU_ADDR + GIUPIOD_H_REG_W)); 374 offs = port - 16; 375 } else if (port < 48) { 376 addr = MIPS_PHYS_TO_KSEG1((VRIP_GIU_ADDR + GIUPODAT_L_REG_W)); 377 offs = port - 32; 378 } else { 379 addr = MIPS_PHYS_TO_KSEG1((VRIP_GIU_ADDR + GIUPODAT_H_REG_W)); 380 offs = port - 48; 381 panic ("__vrgiu_out: not coded yet."); 382 } 383 DPRINTF(DEBUG_IO, ("__vrgiu_out: addr %08x bit %d\n", addr, offs)); 384 385 wbflush(); 386 reg = *((volatile u_int16_t*)addr); 387 if (data) { 388 reg |= (1 << offs); 389 } else { 390 reg &= ~(1 << offs); 391 } 392 *((volatile u_int16_t*)addr) = reg; 393 wbflush(); 394 } 395 /* 396 * Interrupt staff 397 */ 398 void * 399 vrgiu_intr_establish(ic, port, mode, level, ih_fun, ih_arg) 400 vrgiu_chipset_tag_t ic; 401 int port; /* GPIO pin # */ 402 int mode; /* GIU trigger setting */ 403 int level; /* XXX not yet */ 404 int (*ih_fun) __P((void*)); 405 void *ih_arg; 406 { 407 struct vrgiu_softc *sc = (void*)ic; 408 int s; 409 u_int32_t reg, mask; 410 struct vrgiu_intr_entry *ih; 411 412 if (!LEGAL_INTR_PORT(port)) 413 panic ("vrgiu_intr_establish: bogus interrupt line."); 414 if (sc->sc_intr_mode[port] && mode != sc->sc_intr_mode[port]) 415 panic ("vrgiu_intr_establish: bogus interrupt type."); 416 else 417 sc->sc_intr_mode[port] = mode; 418 mask = (1 << port); 419 420 s = splhigh(); 421 422 if (!(ih = malloc(sizeof(struct vrgiu_intr_entry), M_DEVBUF, M_NOWAIT))) 423 panic ("vrgiu_intr_establish: no memory."); 424 425 ih->ih_port = port; 426 ih->ih_fun = ih_fun; 427 ih->ih_arg = ih_arg; 428 TAILQ_INSERT_TAIL(&sc->sc_intr_head[port], ih, ih_link); 429 #ifdef WINCE_DEFAULT_SETTING 430 #warning WINCE_DEFAULT_SETTING 431 #else 432 /* 433 * Setup registers 434 */ 435 /* Input mode */ 436 reg = vrgiu_regread_4(sc, GIUIOSEL_REG); 437 reg &= ~mask; 438 vrgiu_regwrite_4(sc, GIUIOSEL_REG, reg); 439 440 /* interrupt type */ 441 reg = vrgiu_regread_4(sc, GIUINTTYP_REG); 442 DPRINTF(DEBUG_INTR, ("[%s->",reg & mask ? "edge" : "level")); 443 if (mode & VRGIU_INTR_EDGE) { 444 DPRINTF(DEBUG_INTR, ("edge]")); 445 reg |= mask; /* edge */ 446 } else { 447 DPRINTF(DEBUG_INTR, ("level]")); 448 reg &= ~mask; /* level */ 449 } 450 vrgiu_regwrite_4(sc, GIUINTTYP_REG, reg); 451 452 /* interrupt level */ 453 if (!(mode & VRGIU_INTR_EDGE)) { 454 reg = vrgiu_regread_4(sc, GIUINTALSEL_REG); 455 DPRINTF(DEBUG_INTR, ("[%s->",reg & mask ? "high" : "low")); 456 if (mode & VRGIU_INTR_HIGH) { 457 DPRINTF(DEBUG_INTR, ("high]")); 458 reg |= mask; /* high */ 459 } else { 460 DPRINTF(DEBUG_INTR, ("low]")); 461 reg &= ~mask; /* low */ 462 } 463 vrgiu_regwrite_4(sc, GIUINTALSEL_REG, reg); 464 } 465 /* hold or through */ 466 reg = vrgiu_regread_4(sc, GIUINTHTSEL_REG); 467 DPRINTF(DEBUG_INTR, ("[%s->",reg & mask ? "hold" : "through")); 468 if (mode & VRGIU_INTR_HOLD) { 469 DPRINTF(DEBUG_INTR, ("hold]")); 470 reg |= mask; /* hold */ 471 } else { 472 DPRINTF(DEBUG_INTR, ("through]")); 473 reg &= ~mask; /* through */ 474 } 475 vrgiu_regwrite_4(sc, GIUINTHTSEL_REG, reg); 476 #endif 477 /* 478 * clear interrupt status 479 */ 480 reg = vrgiu_regread_4(sc, GIUINTSTAT_REG); 481 reg &= ~mask; 482 vrgiu_regwrite_4(sc, GIUINTSTAT_REG, reg); 483 /* 484 * enable interrupt 485 */ 486 #ifdef WINCE_DEFAULT_SETTING 487 #warning WINCE_DEFAULT_SETTING 488 #else 489 sc->sc_intr_mask |= mask; 490 vrgiu_regwrite_4(sc, GIUINTEN_REG, sc->sc_intr_mask); 491 /* Unmask GIU level 2 mask register */ 492 vrip_intr_setmask2(sc->sc_vc, sc->sc_ih, (1<<port), 1); 493 #endif 494 splx(s); 495 496 DPRINTF(DEBUG_INTR, ("\n")); 497 498 return ih; 499 } 500 501 void 502 vrgiu_intr_disestablish(ic, arg) 503 vrgiu_chipset_tag_t ic; 504 void *arg; 505 { 506 struct vrgiu_intr_entry *ihe = arg; 507 struct vrgiu_softc *sc = (void*)ic; 508 int port = ihe->ih_port; 509 struct vrgiu_intr_entry *ih; 510 int s; 511 512 s = splhigh(); 513 TAILQ_FOREACH(ih, &sc->sc_intr_head[port], ih_link) { 514 if (ih == ihe) { 515 TAILQ_REMOVE(&sc->sc_intr_head[port], ih, ih_link); 516 free(ih, M_DEVBUF); 517 if (TAILQ_EMPTY(&sc->sc_intr_head[port])) { 518 /* Disable interrupt */ 519 #ifdef WINCE_DEFAULT_SETTING 520 #warning WINCE_DEFAULT_SETTING 521 #else 522 sc->sc_intr_mask &= ~(1<<port); 523 vrgiu_regwrite_4(sc, GIUINTEN_REG, sc->sc_intr_mask); 524 #endif 525 } 526 splx(s); 527 return; 528 } 529 } 530 panic("vrgiu_intr_disetablish: no such a handle."); 531 /* NOTREACHED */ 532 } 533 534 int 535 vrgiu_intr(arg) 536 void *arg; 537 { 538 #ifdef DUMP_GIU_LEVEL2_INTR 539 #warning DUMP_GIU_LEVEL2_INTR 540 static u_int32_t oreg; 541 #endif 542 struct vrgiu_softc *sc = arg; 543 int i; 544 u_int32_t reg; 545 /* Get Level 2 interrupt status */ 546 vrip_intr_get_status2 (sc->sc_vc, sc->sc_ih, ®); 547 #ifdef DUMP_GIU_LEVEL2_INTR 548 #warning DUMP_GIU_LEVEL2_INTR 549 { 550 u_int32_t uedge, dedge, j; 551 for (j = 0x80000000; j > 0; j >>=1) 552 printf ("%c" , reg&j ? '|' : '.'); 553 uedge = (reg ^ oreg) & reg; 554 dedge = (reg ^ oreg) & ~reg; 555 if (uedge || dedge) { 556 for (j = 0; j < 32; j++) { 557 if (uedge & (1 << j)) 558 printf ("+%d", j); 559 else if (dedge & (1 << j)) 560 printf ("-%d", j); 561 } 562 } 563 oreg = reg; 564 printf ("\n"); 565 } 566 #endif 567 /* Clear interrupt */ 568 vrgiu_regwrite_4(sc, GIUINTSTAT_REG, vrgiu_regread_4(sc, GIUINTSTAT_REG)); 569 570 /* Dispatch handler */ 571 for (i = 0; i < MAX_GPIO_INOUT; i++) { 572 if (reg & (1 << i)) { 573 register struct vrgiu_intr_entry *ih; 574 TAILQ_FOREACH(ih, &sc->sc_intr_head[i], ih_link) { 575 ih->ih_fun(ih->ih_arg); 576 } 577 } 578 } 579 580 return 0; 581 } 582
Indexes created Sun Sep 28 07:09:56 GMT 2025